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1.1 root 1: /* opcd.c */
2: # include "mode.h"
3: # include "extern.h"
4: # include "functs.h"
5: # include "defs.h"
6:
7: /* The following array contains the number of
8: extra parcels for the instruction getter. It
9: contains the assembler format for the
10: instruction printer. It is machine dependent.
11: */
12:
13: struct itable itable[ ] = {
14: {"ERR %d%d%d", 0, 0 },
15: {(char *)0, 0, 0200},
16: {(char *)0, 0, 0222},
17: {(char *)0, 0, 0233},
18: {"EX %d%d%d", 0, 0 },
19: {"J B%w%d%d", 0, 0 },
20: {"J %d%d%d%8O", 1, 0 },
21: {"R %d%d%d%8O", 1, 0 },
22: /* 010 starting the conditional jumps */
23: {(char *)0, 1, 0240},
24: {(char *)0, 1, 0242},
25: {(char *)0, 1, 0244},
26: {(char *)0, 1, 0246},
27: {(char *)0, 1, 0250},
28: {(char *)0, 1, 0252},
29: {(char *)0, 1, 0254},
30: {(char *)0, 1, 0256},
31: /* 020 transmits */
32: {"A%d %d%d%8O", 1, 0 },
33: {"A%d #%d%d%8O", 1, 0 },
34: {"A%d %d%d", 0, 0 },
35: {(char *)0, 0, 0260},
36: {"A%d B%d%d", 0, 0 },
37: {"B%w%d%d A%b%b%b%d", 0, 0 },
38: {(char *)0, 0, 0262},
39: {(char *)0, 0, 0265},
40: /* 030 a-register arithmetic and register load */
41: {(char *)0, 0, 0267},
42: {(char *)0, 0, 0272},
43: {"A%d A%d*A%d", 0, 0 },
44: {(char *)0, 0, 0276},
45: {"B%w%d%d,A%b%b%b%d 0,A0", 0, 0 },
46: {"0,A0 B%w%d%d,A%b%b%b%d",0, 0 },
47: {"T%w%d%d,A%b%b%b%d 0,A0", 0, 0 },
48: {"0,A0 T%w%d%d,A%b%b%b%d",0, 0 },
49: /* 040 */
50: {"S%d %d%d%8O", 1, 0 },
51: {"S%d #%d%d%8O", 1, 0 },
52: {(char *)0, 0, 0301},
53: {(char *)0, 0, 0304},
54: {(char *)0, 0, 0306},
55: {(char *)0, 0, 0311},
56: {(char *)0, 0, 0313},
57: {(char *)0, 0, 0316},
58: /* 050 logical arithmetic and shifting */
59: {(char *)0, 0, 0323},
60: {(char *)0, 0, 0325},
61: {"S0 S%d<%d%d", 0, 0 },
62: {"S0 S%d>0100-%d%d",0, 0 },
63: {"S%d S%b%d<%d%d", 0, 0 },
64: {"S%d S%b%d>0100-%d%d",0, 0 },
65: {(char *)0, 0, 0332},
66: {(char *)0, 0, 0335},
67: /* 060 floating-point arithmetic */
68: {"S%d S%d+S%d", 0, 0 },
69: {(char *)0, 0, 0340},
70: {(char *)0, 0, 0342},
71: {(char *)0, 0, 0344},
72: {"S%d S%d*FS%d", 0, 0 },
73: {"S%d S%d*HS%d", 0, 0 },
74: {"S%d S%d*RS%d", 0, 0 },
75: {"S%d S%d*IS%d", 0, 0 },
76: /* 070 transmits */
77: {"S%d \\HS%d", 0, 0 },
78: {(char *)0, 0, 0346},
79: {(char *)0, 0, 0356},
80: {(char *)0, 0, 0361},
81: {"S%d T%d%d", 0, 0 },
82: {"T%w%d%d S%b%b%b%d", 0, 0 },
83: {"S%d V%d,A%d", 0, 0 },
84: {(char *)0, 0, 0370},
85: /* 0100 read from memory to a-register */
86: {(char *)0, 1, 0372},
87: {(char *)0, 1, 0372},
88: {(char *)0, 1, 0372},
89: {(char *)0, 1, 0372},
90: {(char *)0, 1, 0372},
91: {(char *)0, 1, 0372},
92: {(char *)0, 1, 0372},
93: {(char *)0, 1, 0372},
94: /* 0110 write from a-register to memory */
95: {(char *)0, 1, 0375},
96: {(char *)0, 1, 0375},
97: {(char *)0, 1, 0375},
98: {(char *)0, 1, 0375},
99: {(char *)0, 1, 0375},
100: {(char *)0, 1, 0375},
101: {(char *)0, 1, 0375},
102: {(char *)0, 1, 0375},
103: /* 0120 read from memory to s-register */
104: {(char *)0, 1, 0400},
105: {(char *)0, 1, 0400},
106: {(char *)0, 1, 0400},
107: {(char *)0, 1, 0400},
108: {(char *)0, 1, 0400},
109: {(char *)0, 1, 0400},
110: {(char *)0, 1, 0400},
111: {(char *)0, 1, 0400},
112: /* 0130 write from s-register to memory */
113: {(char *)0, 1, 0403},
114: {(char *)0, 1, 0403},
115: {(char *)0, 1, 0403},
116: {(char *)0, 1, 0403},
117: {(char *)0, 1, 0403},
118: {(char *)0, 1, 0403},
119: {(char *)0, 1, 0403},
120: {(char *)0, 1, 0403},
121: /* 0140 v-register logical instructions */
122: {"V%d S%d&V%d", 0, 0 },
123: {"V%d V%d&V%d", 0, 0 },
124: {(char *)0, 0, 0406},
125: {"V%d V%d!V%d", 0, 0 },
126: {"V%d S%d\\V%d", 0, 0 },
127: {(char *)0, 0, 0410},
128: {(char *)0, 0, 0412},
129: {"V%d V%d!V%d&VM", 0, 0 },
130: /* 0150 shifting and v-register integer arithmetic */
131: {(char *)0, 0, 0414},
132: {(char *)0, 0, 0416},
133: {(char *)0, 0, 0420},
134: {(char *)0, 0, 0422},
135: {"V%d S%d+V%d", 0, 0 },
136: {"V%d V%d+V%d", 0, 0 },
137: {(char *)0, 0, 0424},
138: {"V%d V%d-V%d", 0, 0 },
139: /* 0160 v-register floating-point arithmetic */
140: {"V%d S%d*FV%d", 0, 0 },
141: {"V%d V%d*FV%d", 0, 0 },
142: {"V%d S%d*HV%d", 0, 0 },
143: {"V%d V%d*HV%d", 0, 0 },
144: {"V%d S%d*RV%d", 0, 0 },
145: {"V%d V%d*RV%d", 0, 0 },
146: {"V%d S%d*IV%d", 0, 0 },
147: {"V%d V%d*IV%d", 0, 0 },
148: /* 0170 v-register floating-point, vector masking,etc. */
149: {(char *)0, 0, 0426},
150: {"V%d V%d+FV%d", 0, 0 },
151: {(char *)0, 0, 0430},
152: {"V%d V%d-FV%d", 0, 0 },
153: {(char *)0, 0, 0432},
154: {(char *)0, 0, 0435},
155: {(char *)0, 0, 0445},
156: {(char *)0, 0, 0450},
157:
158: /* Subinstructions for instruction type 001 */
159: {"CA,A%w%d A%d", 0, 0 },
160: {"CL,A%w%d A%d", 0, 0 },
161: {"CI,A%w%d", 0, 0 },
162: {"MC,A%w%d", 0, 0 },
163: {"XA A%w%d", 0, 0 },
164: {"RT S%w%d", 0, 0 },
165: {"SIPI %w%d", 0, 0 },
166: {"CIPI", 0, 0 },
167: {"CLN %w%d", 0, 0 },
168: {"PCI S%w%d", 0, 0 },
169: {"CCI", 0, 0 },
170: {"ECI", 0, 0 },
171: {"DCI", 0, 0 },
172: {"select perf mon", 0, 0 },
173: {"set maint read", 0, 0 },
174: {"load diag byte", 0, 0 },
175: {"set maint write 1", 0, 0 },
176: {"set maint write 2", 0, 0 },
177: /* Subinstructions for instruction type 002 */
178: {"VL A%w%w%d", 0, 0 },
179: {"VL 1", 0, 0 },
180: {"EFI", 0, 0 },
181: {"DFI", 0, 0 },
182: {"ERI", 0, 0 },
183: {"DRI", 0, 0 },
184: {"DBM", 0, 0 },
185: {"EBM", 0, 0 },
186: {"CMR", 0, 0 },
187: /* Subinstructions for instruction type 003 */
188: {"VM S%w%d", 0, 0 },
189: {"VM 0", 0, 0 },
190: {"SM%w%d%d 1,TS", 0, 0 },
191: {"SM%w%d%d 0", 0, 0 },
192: {"SM%w%d%d 1", 0, 0 },
193: /* Subinstructions for instruction type 010 */
194: {"JAZ %d%d%d%8O", 1, 0 },
195: {"A0 %d%d%d%8O", 1, 0 },
196: /* Subinstructions for instruction type 011 */
197: {"JAN %d%d%d%8O", 1, 0 },
198: {"A1 %d%d%d%8O", 1, 0 },
199: /* Subinstructions for instruction type 012 */
200: {"JAP %d%d%d%8O", 1, 0 },
201: {"A2 %d%d%d%8O", 1, 0 },
202: /* Subinstructions for instruction type 013 */
203: {"JAM %d%d%d%8O", 1, 0 },
204: {"A3 %d%d%d%8O", 1, 0 },
205: /* Subinstructions for instruction type 014 */
206: {"JSZ %d%d%d%8O", 1, 0 },
207: {"A4 %d%d%d%8O", 1, 0 },
208: /* Subinstructions for instruction type 015 */
209: {"JSN %d%d%d%8O", 1, 0 },
210: {"A5 %d%d%d%8O", 1, 0 },
211: /* Subinstructions for instruction type 016 */
212: {"JSP %d%d%d%8O", 1, 0 },
213: {"A6 %d%d%d%8O", 1, 0 },
214: /* Subinstructions for instruction type 017 */
215: {"JSM %d%d%d%8O", 1, 0 },
216: {"A7 %d%d%d%8O", 1, 0 },
217: /* Subinstructions for instruction type 023 */
218: {"A%d S%d", 0, 0 },
219: {"A%d VL", 0, 0 },
220: /* Subinstructions for instruction type 026 */
221: {"A%d PS%d", 0, 0 },
222: {"A%d QS%d", 0, 0 },
223: {"A%d SB%d", 0, 0 },
224: /* Subinstructions for instruction type 027 */
225: {"A%d ZS%d", 0, 0 },
226: {"SB%w%d A%b%b%d", 0, 0 },
227: /* Subinstructions for instruction type 030 */
228: {"A%d A%d+A%d", 0, 0 },
229: {"A%d A%w%d", 0, 0 },
230: {"A%d A%d+1", 0, 0 },
231: /* Subinstructions for instruction type 031 */
232: {"A%d A%d-A%d", 0, 0 },
233: {"A%d -1", 0, 0 },
234: {"A%d -A%w%d", 0, 0 },
235: {"A%d A%d-1", 0, 0 },
236: /* Subinstructions for instruction type 033 */
237: {"A%d CI", 0, 0 },
238: {"A%d CA,A%d", 0, 0 },
239: {"A%d CE,A%d", 0, 0 },
240: /* Subinstructions for instruction type 042 */
241: {"S%d <0100-%d%d", 0, 0 },
242: {"S%d 1", 0, 0 },
243: {"S%d -1", 0, 0 },
244: /* Subinstructions for instruction type 043 */
245: {"S%d >%d%d", 0, 0 },
246: {"S%d 0", 0, 0 },
247: /* Subinstructions for instruction type 044 */
248: {"S%d S%d&S%d", 0, 0 },
249: {"S%d S%d&SB", 0, 0 },
250: {"S%d SB&S%d", 0, 0 },
251: /* Subinstructions for instruction type 045 */
252: {"S%d #S%w%d&S%b%b%d",0, 0 },
253: {"S%d #SB&S%d", 0, 0 },
254: /* Subinstructions for instruction type 046 */
255: {"S%d S%d\\S%d", 0, 0 },
256: {"S%d S%d\\SB", 0, 0 },
257: {"S%d SB\\S%d", 0, 0 },
258: /* Subinstructions for instruction type 047 */
259: {"S%d #S%d\\S%d", 0, 0 },
260: {"S%d #S%w%d", 0, 0 },
261: {"S%d #S%d\\SB", 0, 0 },
262: {"S%d #SB\\S%d", 0, 0 },
263: {"S%d #SB", 0, 0 },
264: /* Subinstructions for instruction type 050 */
265: {"S%d S%d!S%b%b%d&S%w%d",0,0 },
266: {"S%d S%d!S%b%b%d&SB",0, 0 },
267: /* Subinstructions for instruction type 051 */
268: {"S%d S%d!S%d", 0, 0 },
269: {"S%d S%w%d", 0, 0 },
270: {"S%d S%d!SB", 0, 0 },
271: {"S%d SB!S%d", 0, 0 },
272: {"S%d SB", 0, 0 },
273: /* Subinstructions for instruction type 056 */
274: {"S%d S%b%d,S%d<A%d",0, 0 },
275: {"S%d S%b%d,S%d<1",0, 0 },
276: {"S%d S%b%d<A%d", 0, 0 },
277: /* Subinstructions for instruction type 057 */
278: {"S%d S%d,S%b%b%d>A%w%d",0,0 },
279: {"S%d S%d,S%b%b%d>1",0, 0 },
280: {"S%d S%b%d>A%w%d",0, 0 },
281: /* Subinstructions for instruction type 061 */
282: {"S%d S%d-S%d", 0, 0 },
283: {"S%d -S%w%d", 0, 0 },
284: /* Subinstructions for instruction type 062 */
285: {"S%d S%d+FS%d", 0, 0 },
286: {"S%d +FS%w%d", 0, 0 },
287: /* Subinstructions for instruction type 063 */
288: {"S%d S%d-FS%d", 0, 0 },
289: {"S%d -FS%w%d", 0, 0 },
290: /* Subinstructions for instruction type 071 */
291: {"S%d A%w%d", 0, 0 },
292: {"S%d +A%w%d", 0, 0 },
293: {"S%d +FA%w%d", 0, 0 },
294: {"S%d 0.6", 0, 0 },
295: {"S%d 0.4", 0, 0 },
296: {"S%d 1.", 0, 0 },
297: {"S%d 2.", 0, 0 },
298: {"S%d 4.", 0, 0 },
299: /* Subinstructions for instruction type 072 */
300: {"S%d RT", 0, 0 },
301: {"S%d SM", 0, 0 },
302: {"S%d ST%d", 0, 0 },
303: /* Subinstructions for instruction type 073 */
304: {"S%d VM", 0, 0 },
305: {"S%d SR%d", 0, 0 },
306: {"read perf count", 0, 0 },
307: {"incr perf count", 0, 0 },
308: {"clear maint modes", 0, 0 },
309: {"SM S%d", 0, 0 },
310: {"ST%w%d S%b%b%d", 0, 0 },
311: /* Subinstructions for instruction type 077 */
312: {"V%d,A%w%d S%b%b%d", 0, 0 },
313: {"V%d,A%w%d 0", 0, 0 },
314: /* Subinstructions for instruction type 10h */
315: {"A%d %d%d%8O,A%d", 1, 0 },
316: {"A%d %d%d%8O,0", 1, 0 },
317: {"A%d 0,A%w%w%w%d", 1, 0 },
318: /* Subinstructions for instruction type 11h */
319: {"%w%d%d%8O,A%d A%b%b%b%b%b%d",1,0 },
320: {"%w%d%d%8O,0 A%b%b%b%b%d",1,0 },
321: {"0,A%w%w%w%w%d A%b%b%b%b%b%d",1,0 },
322: /* Subinstructions for instruction type 12h */
323: {"S%d %d%d%8O,A%d", 1, 0 },
324: {"S%d %d%d%8O,0", 1, 0 },
325: {"S%d 0,A%w%w%w%d", 1, 0 },
326: /* Subinstructions for instruction type 13h */
327: {"%w%d%d%8O,A%d S%b%b%b%b%b%d",1,0 },
328: {"%w%d%d%8O,0 S%b%b%b%b%d",1,0 },
329: {"0,A%w%w%w%w%d S%b%b%b%b%b%d",1,0 },
330: /* Subinstructions for instruction type 142 */
331: {"V%d S%d!V%d", 0, 0 },
332: {"V%d V%w%d", 0, 0 },
333: /* Subinstructions for instruction type 145 */
334: {"V%d V%d\\V%d", 0, 0 },
335: {"V%d 0", 0, 0 },
336: /* Subinstructions for instruction type 146 */
337: {"V%d S%d!V%d&VM", 0, 0 },
338: {"V%d #VM&V%w%d", 0, 0 },
339: /* Subinstructions for instruction type 150 */
340: {"V%d V%d<A%d", 0, 0 },
341: {"V%d V%d<1", 0, 0 },
342: /* Subinstructions for instruction type 151 */
343: {"V%d V%d>A%d", 0, 0 },
344: {"V%d V%d>1", 0, 0 },
345: /* Subinstructions for instruction type 152 */
346: {"V%d V%d,V%b%d<A%d",0, 0 },
347: {"V%d V%d,V%b%d<1",0, 0 },
348: /* Subinstructions for instruction type 153 */
349: {"V%d V%d,V%b%d>A%d",0, 0 },
350: {"V%d V%d,V%b%d>1",0, 0 },
351: /* Subinstructions for instruction type 156 */
352: {"V%d S%d-V%d", 0, 0 },
353: {"V%d -V%w%d", 0, 0 },
354: /* Subinstructions for instruction type 170 */
355: {"V%d S%d+FV%d", 0, 0 },
356: {"V%d +FV%w%d", 0, 0 },
357: /* Subinstructions for instruction type 172 */
358: {"V%d S%d-FV%d", 0, 0 },
359: {"V%d -FV%w%d", 0, 0 },
360: /* Subinstructions for instruction type 174 */
361: {"V%d \\HV%d", 0, 0 },
362: {"V%d PV%d", 0, 0 },
363: {"V%d QV%d", 0, 0 },
364: /* Subinstructions for instruction type 175 */
365: {"VM V%w%d,Z", 0, 0 },
366: {"VM V%w%d,N", 0, 0 },
367: {"VM V%w%d,P", 0, 0 },
368: {"VM V%w%d,M", 0, 0 },
369: {"V%d,VM V%d,Z", 0, 0 },
370: {"V%d,VM V%d,N", 0, 0 },
371: {"V%d,VM V%d,P", 0, 0 },
372: {"V%d,VM V%d,M", 0, 0 },
373: /* Subinstructions for instruction type 176 */
374: {"V%d ,A0,A%w%d", 0, 0 },
375: {"V%d ,A0,1", 0, 0 },
376: {"V%d ,A0,V%w%d", 0, 0 },
377: /* Subinstructions for instruction type 177 */
378: {",A0,A%w%w%d V%b%b%d",0, 0 },
379: {",A0,1 V%w%d", 0, 0 },
380: {",A0,V%w%w%d V%b%b%d",0, 0 },
381: };
382:
383: /* The second parameter ins is the numeric op code for the instruction.
384: */
385: void printins(idsp, ins)
386: int idsp;
387: long ins;
388: {
389: long ops[5];
390: long blank = -99;
391: int itaboffs;
392: if (dot & 01) {
393: adbpr("not on parcel boundary\n");
394: return;
395: }
396: ins = ins >> 48;
397: ins = ins & 0177777;
398: dotinc = setins ( (unsigned long)ins, dot , idsp);
399: ops[0] = instr.opi;
400: ops[1] = instr.opj;
401: ops[2] = instr.opk;
402: ops[3] = instr.opother;
403: ops[4] = instr.oph;
404: if (itable[instr.opcode].iformat == 0) {
405: itaboffs = getoffs (itable[instr.opcode].ioffset);
406: adbpr (itable[itaboffs].iformat, blank, ops);
407: }
408: else
409: adbpr ( itable[instr.opcode].iformat , blank, ops );
410: }
411:
412: /* Routine setins is used by the disassembler and by
413: the instruction stepper to build the global instr
414: structure and to set dotinc to the size of the
415: instruction. Upon entry, the first parcel of the
416: instruction is in the unsigned long w.
417: */
418: int setins ( w, mydot, idsp)
419: register unsigned long w;
420: long mydot;
421: int idsp;
422: {
423: instr.opcode = (w >> 9) & 0177;
424: instr.oph = (w >> 9) & 07;
425: instr.opi = (w >> 6) & 07;
426: instr.opj = (w >> 3) & 07;
427: instr.opk = (w) & 07;
428: parcels = itable[instr.opcode].iparcels;
429: if (parcels == 1)
430: instr.opother = (unsigned long)(get(mydot+2,idsp)>>48);
431: return(2 * (1+parcels));
432: }
433:
434: /* Routine getoffs is what is used to handle those opcodes that could
435: represent more than one instruction. This routine is simply one large
436: switch with a manual lookup into the subinstruction part of the table
437: */
438: int
439: getoffs (ioffs)
440: int ioffs;
441: {
442: switch (ioffs) {
443: /*001*/ case 0200: switch(instr.opi) {
444: case 0: break;
445: case 1: ioffs += 01; break;
446: case 2: if(instr.opk == 0) ioffs += 02;
447: else ioffs += 03;
448: break;
449: case 3: ioffs += 04; break;
450: case 4: switch(instr.opk) {
451: case 0: if (instr.opj == 2) ioffs += 07;
452: else ioffs += 05;
453: break;
454: case 1: ioffs += 06; break;
455: case 3:
456: case 4:
457: case 5:
458: case 6:
459: case 7:
460: ioffs = ioffs + 05 + instr.opk;
461: break;
462: }
463: case 5: if (instr.opk == 0) ioffs += 015;
464: else ioffs = ioffs + 016 + instr.opj;
465: break;
466: }
467: /*002*/ case 0222: if (instr.opk != 0) break;
468: else ioffs = ioffs + 01 + instr.opi;
469: break;
470: /*003*/ case 0233: switch(instr.opi) {
471: case 0: if (instr.opj != 0) break;
472: else ioffs += 01;
473: break;
474: case 4: ioffs += 02; break;
475: case 6: ioffs += 03; break;
476: case 7: ioffs += 04; break;
477: }
478: /*010*/ case 0240:
479: /*011*/ case 0242:
480: /*012*/ case 0244:
481: /*013*/ case 0246:
482: /*014*/ case 0250:
483: /*015*/ case 0252:
484: /*016*/ case 0254:
485: /*017*/ case 0256: if ((instr.opi>>2)&01 == 1) ioffs += 01;
486: break;
487: /*023*/ case 0260: if (instr.opk == 1)
488: ioffs += 01;
489: break;
490: /*026*/ case 0262: switch(instr.opk) {
491: case 0: break;
492: case 1: ioffs += 01; break;
493: case 7: ioffs += 02; break;
494: }
495: /*027*/ case 0265: if (instr.opk == 7)
496: ioffs += 01;
497: break;
498: /*030*/ case 0267: if (instr.opj == 0) ioffs += 01;
499: if (instr.opk == 0) ioffs += 02;
500: break;
501: /*031*/ case 0272: if (instr.opj == 0) {
502: if (instr.opk == 0) ioffs += 01;
503: else ioffs += 02;
504: break;
505: }
506: if (instr.opk == 0) ioffs += 03;
507: break;
508: /*033*/ case 0276: if (instr.opj == 0) break;
509: if (instr.opk == 0) ioffs += 01;
510: else ioffs += 02;
511: break;
512: /*042*/ case 0301: if ((instr.opj==0)&(instr.opk == 0)) ioffs += 02;
513: if ((instr.opj==7)&(instr.opk == 7)) ioffs += 01;
514: break;
515: /*043*/ case 0304: if ((instr.opj == 0) & (instr.opk == 0)) ioffs += 01;
516: break;
517: /*044*/ case 0306: switch (instr.opk) {
518: case 0: if (instr.opj == 0) ioffs += 01;
519: else ioffs += 02;
520: break;
521: default: break;
522: }
523: /*045*/ case 0311:
524: /*050*/ case 0323:
525: /*150*/ case 0414:
526: /*151*/ case 0416:
527: /*152*/ case 0420:
528: /*153*/ case 0422:
529: if (instr.opk == 0) ioffs += 01;
530: break;
531: /*046*/ case 0313: switch (instr.opk) {
532: case 0: if (instr.opj == 0) ioffs += 01;
533: else ioffs += 02;
534: break;
535: default: break;
536: }
537: /*047*/ case 0316:
538: /*051*/ case 0325:
539: if (instr.opk == 0) {
540: if (instr.opj == 0) ioffs += 04;
541: else ioffs += 03;
542: break;
543: }
544: else if (instr.opj == 0) ioffs += 01;
545: break;
546: /*056*/ case 0332:
547: /*057*/ case 0335:
548: if (instr.opj == 0) ioffs += 02;
549: if (instr.opk == 0) ioffs += 01;
550: break;
551: /*061*/ case 0340:
552: /*062*/ case 0342:
553: /*063*/ case 0344:
554: /*077*/ case 0370:
555: /*142*/ case 0406:
556: /*146*/ case 0412:
557: /*156*/ case 0424:
558: /*170*/ case 0426:
559: /*172*/ case 0430:
560: if (instr.opj == 0) ioffs += 01;
561: break;
562: /*071*/ case 0346: ioffs += instr.opj;
563: break;
564: /*072*/ case 0356: switch (instr.opk) {
565: case 0: break;
566: case 2: ioffs += 01; break;
567: case 3: ioffs += 02; break;
568: }
569: /*073*/ case 0361: switch (instr.opk) {
570: case 0: break;
571: case 1: ioffs = ioffs + 01 + instr.opj; break;
572: case 2: ioffs += 05; break;
573: case 3: ioffs += 06; break;
574: }
575: /*10h*/ case 0372:
576: /*11h*/ case 0375:
577: /*12h*/ case 0400:
578: /*13h*/ case 0403:
579: if (instr.oph == 0) ioffs += 01;
580: else if((instr.opj==0)&(instr.opk==0)&(instr.opother==0))
581: ioffs += 02;
582: break;
583: /*145*/ case 0410: if ((instr.opi == instr.opj) == instr.opk)
584: ioffs += 01;
585: break;
586: /*174*/ case 0432:
587: /*175*/ case 0435:
588: ioffs += instr.opk;
589: break;
590: /*176*/ case 0445: if (instr.opj == 1) ioffs += 02;
591: else if (instr.opk == 0) ioffs += 01;
592: break;
593: /*177*/ case 0450: if (instr.opi == 1) {ioffs += 02; break;}
594: if (instr.opk == 0) ioffs += 01;
595: break;
596: }
597: return (ioffs);
598: }
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