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1.1 root 1: #include "an.h"
2: #if NAN > 0
3:
4: #include "../h/param.h"
5: #include "../h/systm.h"
6: #include "../h/buf.h"
7: #include "../h/conf.h"
8: #include "../h/dir.h"
9: #include "../h/user.h"
10: #include "../h/pte.h"
11: #include "../h/map.h"
12: #include "../h/vm.h"
13: #include "../h/anet.h"
14: #include "../h/cmap.h"
15: #include "../h/ubareg.h"
16: #include "../h/ubavar.h"
17: #include "../h/cpu.h"
18: #include "../h/proc.h"
19: #include "../h/status.h"
20:
21:
22: #ifdef ANDEBUG
23: int andebug = 1;
24: #else
25: int andebug = 0;
26: #endif
27:
28: /* flags for status */
29: #define INPUT 1
30: #define OUTPUT 2
31:
32: #define min(x,y) ((x) < (y) ? (x) : (y))
33: #define swab(x) (((x<<8) | ((x&0xFF00)>>8)) & 0xFFFF)
34:
35: #define ANPRI 28
36:
37: struct device {
38: short drcs;
39: short drout;
40: short drin;
41: };
42:
43: /* Command and Status word */
44: #define CSR0 0x1
45: #define CSR1 0x2
46: #define RIE 0x20
47: #define TIE 0x40
48: #define TEMPTY 0x80
49: #define RFULL 0x8000
50:
51: /*
52: * CSR1 CSR0
53: * 0 0 Write Data
54: * 0 1 Write EOP
55: * 1 0 Write Command
56: * 1 1 Read Status
57: */
58: #define DATA_MODE (RIE)
59: #define EOP_MODE (CSR0 | RIE)
60: #define CMD_MODE (CSR1 | RIE)
61: #define STATUS_MODE (CSR0 | CSR1 | RIE)
62:
63: #define MAXMSGLEN 2042
64: #define IBUF 1
65: #define OBUF 2
66:
67: struct an_dev {
68: char open;
69: char flag;
70: short uid;
71: short icnt, ocnt;
72: short ibuf[MAXMSGLEN/2];
73: short obuf[MAXMSGLEN/2];
74: } an_dev[NAN];
75:
76: #ifdef TIMEOUT
77: #define CKFUZZ 4 /* number of timeouts we wait for a response */
78: #define CKTICKS (hz/4) /* number of ticks per timeout */
79:
80: int an_state;
81: #define OPEN 1 /* set if at least one sn? is open */
82: #define TIMER 2 /* set if at timer is running */
83:
84: int cktimchk();
85: int an_opncnt;
86: #endif TIMEOUT
87:
88: /*struct anmach anmach[8] = {
89: { 1, 255 },
90: { 2, 254 },
91: { 3, 253 },
92: { 4, 252 },
93: { 5, 251 },
94: { 6, 250 },
95: { 7, 249 },
96: { 8, 248 } };*/
97:
98: #define RETURN(x) {u.u_error = x; return(0);}
99:
100: int anprobe(), anattach();
101: struct uba_device *andinfo[NAN];
102: u_short anstd[] = {0};
103: struct uba_driver andriver =
104: { anprobe, 0, anattach, 0, anstd, "an", andinfo};
105:
106: anprobe(reg)
107: caddr_t reg;
108: {
109: register int br, cvec; /* value result */
110:
111: br = 0x15;
112: cvec = 0510;
113: return(1);
114: }
115:
116: anattach()
117: {
118: register struct device *draddr;
119: register struct uba_device *ui;
120:
121: ui = andinfo[0];
122: draddr = (struct device *)ui->ui_addr;
123: draddr->drcs = CMD_MODE;
124: draddr->drout = 0;
125: draddr->drout = MASTER_CLEAR;
126: draddr->drout = 0;
127: draddr->drout = BOARD_RESET;
128: draddr->drout = 0;
129: draddr->drcs = STATUS_MODE;
130: printf("S/NET BIB #%d\n", (draddr->drin>>10)&0xF);
131:
132: }
133:
134: /*
135: open the argus network
136: */
137:
138: anopen(dev)
139: register dev_t dev;
140: {
141: register struct device *draddr;
142: register struct an_dev *an;
143: register struct uba_device *ui;
144: int net = NET(dev);
145:
146: if(andebug)
147: printf("anopen(%x)\n", dev);
148: if(net >= NAN || (ui = andinfo[net]) == 0 || ui->ui_alive == 0)
149: RETURN(ENXIO);
150: draddr = (struct device *)ui->ui_addr;
151:
152: an = &an_dev[net];
153: spl6();
154: if (an->open++ != 0) {
155: spl0();
156: RETURN(EBUSY);
157: }
158: an->uid = u.u_uid;
159: #ifdef TIMEOUT
160: sn_opncnt++;
161: sn_state |= OPEN;
162: if ((sn_state & TIMER) == 0) {
163: sn_state |= TIMER;
164: timeout(cktimchk, (caddr_t)0, CKTICKS);
165: }
166: #endif TIMEOUT
167: draddr->drcs = CMD_MODE;
168: draddr->drout = 0;
169: draddr->drout = BOARD_RESET;
170: draddr->drout = 0;
171: draddr->drcs = DATA_MODE;
172:
173: spl0();
174: return(1);
175: }
176:
177: anclose(dev)
178: {
179: struct uba_device *ui;
180: register struct an_dev *an;
181: int net = NET(dev);
182:
183: if(andebug)
184: printf("anclose(%x)\n", dev);
185: if(net >= NAN)
186: RETURN(ENXIO)
187: an = &an_dev[net];
188: spl6();
189: an->open = 0;
190: spl0();
191: }
192:
193: anread(dev)
194: dev_t dev;
195: {
196: int net;
197: register struct device *draddr;
198: register struct an_dev *an;
199: register struct uba_device *ui;
200: short stat;
201:
202: net = NET(dev);
203: if(net >= NAN)
204: RETURN(ENXIO)
205: ui = andinfo[net];
206: draddr = (struct device *)ui->ui_addr;
207: an = &an_dev[net];
208: if(an->open == 0) RETURN(ENXIO)
209: spl6();
210: if((an->flag&IBUF) == 0)
211: RETURN(EIO);
212: if(copyout(an->ibuf, u.u_base, an->icnt))
213: {
214: spl0();
215: RETURN(EFAULT);
216: }
217: u.u_count -= an->icnt;
218: an->flag &= ~IBUF;
219: spl0();
220: }
221:
222: anwrite(dev)
223: dev_t dev;
224: {
225: int net;
226: register struct device *draddr;
227: register struct an_dev *an;
228: register struct uba_device *ui;
229: short stat;
230:
231: net = NET(dev);
232: if(net >= NAN)
233: RETURN(ENXIO)
234: ui = andinfo[net];
235: draddr = (struct device *)ui->ui_addr;
236: an = &an_dev[net];
237: if(an->open == 0) RETURN(ENXIO)
238: if((an->ocnt = u.u_count) > MAXMSGLEN)
239: an->ocnt = MAXMSGLEN;
240: if(an->ocnt < 2)
241: RETURN(EIO);
242: if(copyin(u.u_base, an->obuf, an->ocnt))
243: RETURN(EFAULT);
244: if(andebug)
245: printf("write on dev %d of %d bytes, sh[0]=%x, sh[1]=%x\n",
246: net, u.u_count, an->obuf[0], an->obuf[1]);
247: an->flag |= OBUF;
248: if(anxstart(net))
249: u.u_count -= an->ocnt;
250: }
251:
252: anrint(net)
253: int net;
254: {
255: register struct an_dev *an;
256: register short *dp, *sp;
257: register struct device *draddr;
258: register struct uba_device *ui;
259: short stat;
260: int i, len, clen;
261:
262: an = &an_dev[net];
263: if(an->flag&IBUF)
264: {
265: andrain(net);
266: return;
267: }
268: ui = andinfo[net];
269: draddr = (struct device *)ui->ui_addr;
270: dp = &draddr->drin;
271:
272: len = *dp;
273: len = swab(len);
274: if(len > MAXMSGLEN)
275: len = MAXMSGLEN;
276: sp = an->ibuf;
277: an->icnt = len;
278: for(i = (len+1)/2; i; i--)
279: *sp++ = *dp;
280: draddr->drcs = STATUS_MODE;
281: *sp = *dp;
282: draddr->drcs = DATA_MODE;
283: i = spl6();
284: an->flag |= IBUF;
285: splx(i);
286: if ((*sp&INBUF_E) == 0)
287: andrain(net);
288: }
289:
290: andrain(net)
291: int net;
292: {
293: register struct an_dev *an;
294: register short *dp;
295: short sp;
296: register struct device *draddr;
297: register struct uba_device *ui;
298: short stat;
299: int i, len;
300:
301: ui = andinfo[net];
302: draddr = (struct device *)ui->ui_addr;
303: dp = &draddr->drin;
304:
305: do {
306: len = *dp;
307: len = swab(len);
308: if(len > MAXMSGLEN)
309: len = MAXMSGLEN;
310: for(i = (len+1)/2; i; i--)
311: sp = *dp;
312: sp = *dp;
313: sp = *dp;
314: draddr->drcs = STATUS_MODE;
315: sp = *dp;
316: draddr->drcs = DATA_MODE;
317: } while((sp&INBUF_E) == 0);
318: }
319:
320: anxstart(net)
321: int net;
322: {
323: register struct an_dev *an;
324: register short *dp, *sp;
325: register struct device *draddr;
326: register struct uba_device *ui;
327: int retrys, nreps;
328: int i, len;
329:
330: ui = andinfo[net];
331: draddr = (struct device *)ui->ui_addr;
332: an = &an_dev[net];
333: dp = &draddr->drout;
334: draddr->drcs = STATUS_MODE;
335:
336: i = draddr->drin;
337: nreps = retrys = 0;
338: if ( (i&OUTBUF_E) == 0 ) {
339: do {
340: if(++retrys > 100000)
341: {
342: nreps++;
343: printf("anxstart: %d retrys on OUTBUF_E loop\n", nreps*retrys);
344: retrys = 0;
345: draddr->drcs = CMD_MODE;
346: if(nreps >= 2)
347: {
348: printf("S/NET: MASTER CLEAR\n");
349: draddr->drout = 0;
350: draddr->drout = MASTER_CLEAR;
351: }
352: draddr->drout = 0;
353: draddr->drout = BOARD_RESET;
354: draddr->drout = 0;
355: draddr->drcs = DATA_MODE;
356: if(nreps >= 3) return(0);
357: }
358: i = draddr->drin;
359: } while( (i&OUTBUF_E) == 0 );
360: }
361: retrys = 0;
362: len = an->ocnt;
363:
364: loop:
365: sp = an->obuf;
366: draddr->drcs = CMD_MODE;
367: *dp = *sp++;
368: draddr->drcs = DATA_MODE;
369: for(i = (len+1)/2-1; i > 1; i--)
370: *dp = *sp++;
371: draddr->drcs = EOP_MODE;
372: *dp = *sp;
373:
374: draddr->drcs = STATUS_MODE;
375: i = draddr->drin;
376: draddr->drcs = DATA_MODE;
377: if(i&SNACK) {
378: if(++retrys < 100)
379: goto loop;
380: else
381: return(0);
382: }
383: return(1);
384: }
385:
386: anioctl(dev, cmd, addr, flag)
387: caddr_t addr;
388: dev_t dev;
389: {
390: int i;
391: int error;
392: int net = NET(dev);
393:
394: if(net >= NAN)
395: RETURN(ENXIO)
396: switch(cmd)
397: {
398: case ANRESET:
399: /*if(copyin(addr, (caddr_t)&args, sizeof(args)))
400: RETURN(EFAULT)*/
401: break;
402: }
403: }
404:
405: #ifdef TIMEOUT
406: cktimchk()
407: {
408: register struct chdat *cp;
409: register struct sninfo *sninfop;
410: int unit;
411: int s;
412:
413: for(cp=sn_chans; cp < &sn_chans[NUMLCH]; cp++) {
414: if( cp->flags&(SENTDATA|SENTRDY) && --cp->ckticks == 0 ) {
415: unit = cp->snunit;
416: sninfop = &sn_sninfo[unit];
417: sninfop->snsched++;
418: sninfop->snenqlost[cp->machno]++;
419: cp->flags |= RETRY;
420: if (cp->flags & SENTDATA) {
421: wakeup((caddr_t)cp->output.buf);
422: } else {
423: wakeup((caddr_t)cp->input.buf);
424: }
425: }
426: }
427: s = spl6();
428: if (sn_state & OPEN) {
429: timeout(cktimchk, (caddr_t)0, CKTICKS);
430: } else {
431: sn_state &= ~TIMER;
432: }
433: splx(s);
434: }
435: #endif TIMEOUT
436:
437: #endif
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