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1.1 root 1: /*
2: * Information about nexus's.
3: *
4: * Each machine has an address of backplane slots (nexi).
5: * Each nexus is some type of adapter, whose code is the low
6: * byte of the first word of the adapter address space.
7: * At boot time the system looks through the array of available
8: * slots and finds the interconnects for the machine.
9: */
10: #if VAX780
11: #define NNEX780 16
12: #define NEX780 ((struct nexus *)0x20000000)
13: #endif
14: #if VAX750
15: #define NNEX750 16
16: #define NEX750 ((struct nexus *)0xf20000)
17: #endif
18: #if VAX7ZZ
19: #define NNEX7ZZ 16
20: #define NEX7ZZ ((struct nexus *)0xf20000)
21: #endif
22: #define NEXSIZE 0x2000
23:
24: #define MAXNNEXUS 16
25:
26: #ifndef LOCORE
27: struct nexus {
28: union nexcsr {
29: long nex_csr;
30: u_char nex_type;
31: } nexcsr;
32: long nex_pad[NEXSIZE / sizeof (long) - 1];
33: };
34: #ifdef KERNEL
35: struct nexus nexus[MAXNNEXUS];
36: #endif
37: #endif
38:
39: /*
40: * Bits in high word of nexus's.
41: */
42: #define SBI_PARFLT (1<<31) /* sbi parity fault */
43: #define SBI_WSQFLT (1<<30) /* write sequence fault */
44: #define SBI_URDFLT (1<<29) /* unexpected read data fault */
45: #define SBI_ISQFLT (1<<28) /* interlock sequence fault */
46: #define SBI_MXTFLT (1<<27) /* multiple transmitter fault */
47: #define SBI_XMTFLT (1<<26) /* transmit fault */
48:
49: #define NEX_CFGFLT (0xfc000000)
50:
51: #ifndef LOCORE
52: #if VAX780
53: #define NEXFLT_BITS \
54: "\20\40PARFLT\37WSQFLT\36URDFLT\35ISQFLT\34MXTFLT\33XMTFLT"
55: #endif
56: #endif
57:
58: #define NEX_APD (1<<23) /* adaptor power down */
59: #define NEX_APU (1<<22) /* adaptor power up */
60:
61: #define MBA_OT (1<<21) /* overtemperature */
62:
63: #define UBA_UBINIT (1<<18) /* unibus init */
64: #define UBA_UBPDN (1<<17) /* unibus power down */
65: #define UBA_UBIC (1<<16) /* unibus initialization complete */
66:
67: /*
68: * Types for nex_type.
69: */
70: #define NEX_ANY 0 /* pseudo for handling 11/750 */
71: #define NEX_MEM4 0x08 /* 4K chips, non-interleaved mem */
72: #define NEX_MEM4I 0x09 /* 4K chips, interleaved mem */
73: #define NEX_MEM16 0x10 /* 16K chips, non-interleaved mem */
74: #define NEX_MEM16I 0x11 /* 16K chips, interleaved mem */
75: #define NEX_MBA 0x20 /* Massbus adaptor */
76: #define NEX_UBA0 0x28 /* Unibus adaptor */
77: #define NEX_UBA1 0x29 /* 4 flavours for 4 addr spaces */
78: #define NEX_UBA2 0x2a
79: #define NEX_UBA3 0x2b
80: #define NEX_DR32 0x30 /* DR32 user i'face to SBI */
81: #define NEX_MPM0 0x40 /* Multi-port mem */
82: #define NEX_MPM1 0x41 /* Who knows why 4 different ones ? */
83: #define NEX_MPM2 0x42
84: #define NEX_MPM3 0x43
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