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1.1 root 1: /*
2: * VAX UNIBUS adapter registers
3: */
4: #ifndef LOCORE
5: /*
6: * UBA hardware registers
7: */
8: struct uba_regs
9: {
10: int uba_cnfgr; /* configuration register */
11: int uba_cr; /* control register */
12: int uba_sr; /* status register */
13: int uba_dcr; /* diagnostic control register */
14: int uba_fmer; /* failed map entry register */
15: int uba_fubar; /* failed UNIBUS address register */
16: int pad1[2];
17: int uba_brsvr[4];
18: int uba_brrvr[4]; /* receive vector registers */
19: int uba_dpr[16]; /* buffered data path register */
20: int pad2[480];
21: struct pte uba_map[496]; /* unibus map register */
22: int pad3[16]; /* no maps for device address space */
23: };
24: #endif
25:
26: #if VAX780
27: /* uba_cnfgr */
28: #define UBACNFGR_UBINIT 0x00040000 /* unibus init asserted */
29: #define UBACNFGR_UBPDN 0x00020000 /* unibus power down */
30: #define UBACNFGR_UBIC 0x00010000 /* unibus init complete */
31:
32: /* uba_cr */
33: #define UBACR_MRD16 0x40000000 /* map reg disable bit 4 */
34: #define UBACR_MRD8 0x20000000 /* map reg disable bit 3 */
35: #define UBACR_MRD4 0x10000000 /* map reg disable bit 2 */
36: #define UBACR_MRD2 0x08000000 /* map reg disable bit 1 */
37: #define UBACR_MRD1 0x04000000 /* map reg disable bit 0 */
38: #define UBACR_IFS 0x00000040 /* interrupt field switch */
39: #define UBACR_BRIE 0x00000020 /* BR interrupt enable */
40: #define UBACR_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */
41: #define UBACR_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */
42: #define UBACR_CNFIE 0x00000004 /* configuration IE */
43: #define UBACR_UPF 0x00000002 /* UNIBUS power fail */
44: #define UBACR_ADINIT 0x00000001 /* adapter init */
45:
46: /* uba_sr */
47: #define UBASR_BR7FULL 0x08000000 /* BR7 receive vector reg full */
48: #define UBASR_BR6FULL 0x04000000 /* BR6 receive vector reg full */
49: #define UBASR_BR5FULL 0x02000000 /* BR5 receive vector reg full */
50: #define UBASR_BR4FULL 0x01000000 /* BR4 receive vector reg full */
51: #define UBASR_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */
52: #define UBASR_RDS 0x00000200 /* read data substitute */
53: #define UBASR_CRD 0x00000100 /* corrected read data */
54: #define UBASR_CXTER 0x00000080 /* command transmit error */
55: #define UBASR_CXTMO 0x00000040 /* command transmit timeout */
56: #define UBASR_DPPE 0x00000020 /* data path parity error */
57: #define UBASR_IVMR 0x00000010 /* invalid map register */
58: #define UBASR_MRPF 0x00000008 /* map register parity failure */
59: #define UBASR_LEB 0x00000004 /* lost error */
60: #define UBASR_UBSTO 0x00000002 /* UNIBUS select timeout */
61: #define UBASR_UBSSYNTO 0x00000001 /* UNIBUS slave sync timeout */
62:
63: #define UBASR_BITS \
64: "\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"
65:
66: /* uba_brrvr[] */
67: #define UBABRRVR_AIRI 0x80000000 /* adapter interrupt request */
68: #define UBABRRVR_DIV 0x0000ffff /* device interrupt vector field */
69: #endif VAX780
70:
71: /* uba_dpr */
72: #if VAX780
73: #define UBADPR_BNE 0x80000000 /* buffer not empty - purge */
74: #define UBADPR_BTE 0x40000000 /* buffer transfer error */
75: #define UBADPR_DPF 0x20000000 /* DP function (RO) */
76: #define UBADPR_BS 0x007f0000 /* buffer state field */
77: #define UBADPR_BUBA 0x0000ffff /* buffered UNIBUS address */
78: #define UBA_PURGE780(uba, bdp) \
79: ((uba)->uba_dpr[bdp] |= UBADPR_BNE)
80: #endif VAX780
81: #if VAX750
82: #define UBADPR_ERROR 0x80000000 /* error occurred */
83: #define UBADPR_NXM 0x40000000 /* nxm from memory */
84: #define UBADPR_UCE 0x20000000 /* uncorrectable error */
85: #define UBADPR_PURGE 0x00000001 /* purge bdp */
86: #define UBA_PURGE750(uba, bdp) \
87: ((uba)->uba_dpr[bdp] |= (UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE))
88: #endif VAX750
89:
90: /*
91: * Macros for fast buffered data path purging in time-critical routines.
92: *
93: * Too bad C pre-processor doesn't have the power of LISP in macro
94: * expansion...
95: */
96: #if defined(VAX780) && defined(VAX750)
97: #define UBAPURGE(uba, bdp) { \
98: switch (cpu) { \
99: case VAX_780: UBA_PURGE780((uba), (bdp)); break; \
100: case VAX_750: UBA_PURGE750((uba), (bdp)); break; \
101: } \
102: }
103: #endif
104: #if defined(VAX780) && !defined(VAX750)
105: #define UBAPURGE(uba, bdp) { \
106: if (cpu==VAX_780) { \
107: UBA_PURGE780((uba), (bdp)); \
108: } \
109: }
110: #endif
111: #if !defined(VAX780) && defined(VAX750)
112: #define UBAPURGE(uba, bdp) { \
113: if (cpu==VAX_750) { \
114: UBA_PURGE750((uba), (bdp)); break; \
115: } \
116: }
117: #endif
118: #if !defined(VAX780) && !defined(VAX750)
119: #define IF_UBAPURGE(uba, bdp)
120: #endif
121:
122: /* uba_mr[] */
123: #define UBAMR_MRV 0x80000000 /* map register valid */
124: #define UBAMR_BO 0x02000000 /* byte offset bit */
125: #define UBAMR_DPDB 0x01e00000 /* data path designator field */
126: #define UBAMR_SBIPFN 0x000fffff /* SBI page address field */
127:
128: #define UBAMR_DPSHIFT 21 /* shift to data path designator */
129:
130: /*
131: * Number of UNIBUS map registers. We can't use the last 8k of UNIBUS
132: * address space for i/o transfers since it is used by the devices,
133: * hence have slightly less than 256K of UNIBUS address space.
134: */
135: #define NUBMREG 496
136:
137: /*
138: * Number of unibus buffered data paths and possible uba's per cpu type.
139: */
140: #define NBDP780 15
141: #define NBDP750 3
142: #define NBDP7ZZ 0
143: #define MAXNBDP 15
144:
145: #define NUBA780 4
146: #define NUBA750 1
147: #define NUBA7ZZ 1
148: #if VAX780
149: #define MAXNUBA 4
150: #else
151: #define MAXNUBA 1
152: #endif
153:
154: /*
155: * Formulas for locations of the last 8k of UNIBUS memory
156: * for each possible uba.
157: */
158: #if VAX7ZZ
159: #define UMEM7ZZ ((u_short *)(0xffe000))
160: #endif
161: #if VAX750
162: #define UMEM750(i) ((u_short *)(0xffe000-(i)*0x40000))
163: #endif
164: #if VAX780
165: #define UMEM780(i) ((u_short *)(0x2013e000+(i)*0x40000))
166: #endif
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