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1.1 root 1: #ifndef lint
2: static char sccsid[] = "@(#)inst.c 1.1 86/02/03 Copyr 1985 Sun Micro";
3: #endif
4:
5: /*
6: * Copyright (c) 1985 by Sun Microsystems, Inc.
7: */
8:
9:
10: #include "as.h"
11:
12: #if AS
13: extern int no_op(), stop(), one_op(), ctrl_op(), two_op(),
14: jbrnch_op(), cbrnch_op(), branch_op(), brnchs_op(),
15: regmem_op(), shift_op(), reg_op(), postinc(), quick_op(),
16: bit_op(), memreg_op(), exg_op(), addr_op(), link_op(),
17: move_op(), movem_op(), movep_op(), moveq_op(), movec_op(), moves_op(),
18: trap(), rts_op(), lea_op();
19: extern int chk2_op(), div_op(), callm_op(), bitf_op(), bitfr_op(),
20: cas1_op(), cas2_op(), brnchl_op(),pack_op();
21: extern int ascii_op(), byteword(), comm_op(), ctrl_op(), csect_op(),
22: proc_op(), globl_op();
23: extern int even_op(), skip_op(), stab_op(), float_op(), cpid_op() ;
24: extern int cp_general(), cp_move(), cp_regpair(), cp_movecr(), cp_movem() ;
25: extern int cp_oneop(), cp_conditional(), cp_branch(), cp_oneword() ;
26:
27: #define I( a, b, c, d, e, f, g, h, i ) { a, b, c, d, e, 1, f, g, h, i },
28: #define P( a, b, c, d, e, f, g, h ) { a, b, c, d, e, f, 0, {g}, h },
29:
30: #define A_ONE( a ) { a }
31: #define A_TWO( a, b ) { a, b }
32: #define A_TH3( a, b, c ) { a, b, c }
33: #define A_4R( a, b, c, d ) { a, b, c, d }
34: #define A_5V( a, b, c, d, e ) { a, b, c, d, e }
35: #define A_6X( a, b, c, d, e, f ) { a, b, c, d, e, f }
36: #define A_SEVEN( a, b, c, d, e, f, g ) { a, b, c, d, e, f, g }
37: #define A_EIGHT( a, b, c, d, e, f, g, h ) { a, b, c, d, e, f, g, h }
38:
39: #define T_X 0
40: #define T_ONE(a) (((a)<<TOUCHWIDTH)<<TOUCHWIDTH)
41: #define T_TWO(a,b) ((((a)<<TOUCHWIDTH)|(b))<<TOUCHWIDTH)
42: #define T_THREE(a,b,c) (((((a)<<TOUCHWIDTH)|(b))<<TOUCHWIDTH)|(c))
43:
44: #define ASCII ascii_op
45: #define BIT bit_op
46: #define BITF bitf_op
47: #define BITFR bitfr_op
48: #define BRANCH branch_op
49: #define BRNCHS brnchs_op
50: #define BRNCHL brnchl_op
51: #define BYTE byteword
52: #define CALLM callm_op
53: #define CAS1 cas1_op
54: #define CAS2 cas2_op
55: #define CBRNCH cbrnch_op
56: #define CHK2 chk2_op
57: #define COMM comm_op
58: #define CPID cpid_op
59: #define CTRL ctrl_op
60: #define DATA csect_op
61: #define DIV_OP div_op
62: #define DBRA branch_op
63: #define EVEN even_op
64: #define EXG exg_op
65: #define EXIT rts_op
66: #define FLOAT float_op
67: #define PROC proc_op
68: #define GLOBL globl_op
69: #define JBRNCH jbrnch_op
70: #define LEA lea_op
71: #define LINK link_op
72: #define MEMREG memreg_op
73: #define MOVE move_op
74: #define MOVEC movec_op
75: #define MOVEM movem_op
76: #define MOVEP movep_op
77: #define MOVEQ moveq_op
78: #define MOVS moves_op
79: #define NO no_op
80: #define ONE_OP one_op
81: #define PACK pack_op
82: #define POSTINC postinc
83: #define QUICK quick_op
84: #define REG_OP reg_op
85: #define REGMEM regmem_op
86: #define RTS rts_op
87: #define SHIFT_OP shift_op
88: #define SKIP skip_op
89: #define STAB stab_op
90: #define STOP stop
91: #define TRAP trap
92: #define TWO_OP two_op
93: #endif
94:
95: /* List of 68000 op codes */
96: struct ins_bkt op_codes[] = {
97:
98: #if C2
99: # include "characteristics"
100: #else
101: #if AS
102: # include "as_charac"
103: #else
104: #include "NO FLAVOR"
105: #endif
106: #endif
107:
108: 0 };
109:
110: d_ins()
111: {
112: register struct ins_bkt *insp;
113: register struct ins_ptr *ipp;
114: register int save;
115: char *calloc();
116:
117: inst = (struct ins_ptr *) calloc( sizeof op_codes / sizeof op_codes[0], sizeof *inst);
118: if (inst == NULL) sys_error("could not allocate instruction symbol space ");
119: for ( ipp = &inst[0], insp = &op_codes[0]; insp->text_i; ipp++, insp++){
120: ipp->this_p = insp;
121: ipp->name_p = insp->text_i;
122: ipp->next_p = ins_hash_tab[save = hash(ipp->name_p)];
123: ins_hash_tab[save] = ipp;
124: }
125: }
126:
127: struct regdef{ char * name_r ; short regno_r; } defregs[] = {
128: { "d0", D0REG+0 },
129: { "d1", D0REG+1 },
130: { "d2", D0REG+2 },
131: { "d3", D0REG+3 },
132: { "d4", D0REG+4 },
133: { "d5", D0REG+5 },
134: { "d6", D0REG+6 },
135: { "d7", D0REG+7 },
136: { "a0", A0REG+0 },
137: { "a1", A0REG+1 },
138: { "a2", A0REG+2 },
139: { "a3", A0REG+3 },
140: { "a4", A0REG+4 },
141: { "a5", A0REG+5 },
142: { "a6", A6REG },
143: { "a7", A7REG },
144: { "sp", A7REG },
145: { "pc", PCREG },
146: { "cc", CCREG },
147: { "sr", SRREG },
148: { "usp", USPREG+0 },
149: { "sfc", USPREG+1 },
150: { "dfc", USPREG+2 },
151: { "vbr", USPREG+3 },
152: { "cacr",USPREG+4 },
153: { "caar",USPREG+5 },
154: { "msp", USPREG+6 },
155: { "isp", USPREG+7 },
156: { "fp0", FP0REG+0 },
157: { "fp1", FP0REG+1 },
158: { "fp2", FP0REG+2 },
159: { "fp3", FP0REG+3 },
160: { "fp4", FP0REG+4 },
161: { "fp5", FP0REG+5 },
162: { "fp6", FP0REG+6 },
163: { "fp7", FP0REG+7 },
164: { "fpc", FPCREG },
165: { "fps", FPSREG },
166: { "fpi", FPIREG },
167: 0, 0
168: };
169:
170: unsigned reg_access[] = {
171: /* d0 d1 d2 d3 d4 d5 d6 d7 */
172: AM_DREG, AM_DREG, AM_DREG, AM_DREG, AM_DREG, AM_DREG, AM_DREG, AM_DREG,
173: /* a0 a1 a2 a3 a4 a5 a6 a7 */
174: AM_AREG, AM_AREG, AM_AREG, AM_AREG, AM_AREG, AM_AREG, AM_AREG, AM_AREG,
175: /* pc cc sr usp */
176: AM_PCREG,AM_CCREG,AM_CCREG,AM_USPREG|AM_CTRLREG,
177: /* src dfc vbr cacr */
178: AM_CTRLREG, AM_CTRLREG, AM_CTRLREG, AM_CTRLREG,
179: /* caar msp isp */
180: AM_CTRLREG, AM_CTRLREG, AM_CTRLREG,
181: /* fp0 fp1 fp2 fp3 fp4 fp5 fp6 fp7 */
182: AM_FREG, AM_FREG, AM_FREG, AM_FREG, AM_FREG, AM_FREG, AM_FREG, AM_FREG,
183: /* fpc fps fpi */
184: AM_FCTRLREG, AM_FCTRLREG, AM_FCTRLREG,
185: };
186:
187: init_regs()
188: { register struct sym_bkt *sbp;
189: register struct regdef *p = defregs;
190: register i;
191:
192: i = 0;
193: while (p->name_r) {
194: sbp = lookup(p->name_r); /* Make a sym_bkt for it */
195: sbp->value_s = p->regno_r; /* Load the sym_bkt */
196: sbp->csect_s = C_UNDEF;
197: sbp->attr_s = S_DEC | S_DEF | S_REG;
198: p++;
199: i++;
200: }
201: }
202:
203: #if C2
204: struct def_builtin { char *bname; short ruse[4]; } def_builtins[] = {
205: "lmult", LR+LW, LR+LW, 0, 0,
206: "ulmult", LR+LW, LR+LW, 0, 0,
207: "ldivt", LR+LW, LR+LW, 0, 0,
208: "lmodt", LR+LW, LR+LW, 0, 0,
209: "uldivt", LR+LW, LR+LW, 0, 0,
210: "ulmodt", LR+LW, LR+LW, 0, 0,
211: "mcount", 0, 0, LR, 0,
212: /* floating-point, too */
213: "fvaddi", LR+LW, LR+LW, LR+LW, LW,
214: "fvsubi", LR+LW, LR+LW, LR+LW, LW,
215: "fvmuli", LR+LW, LR+LW, LR+LW, LW,
216: "fvdivi", LR+LW, LR+LW, LR+LW, LW,
217: "fvcmpi", LR+LW, LR+LW, LR+LW, LW,
218: "fvaddis", LR+LW, LR+LW, LW, LW,
219: "fvsubis", LR+LW, LR+LW, LW, LW,
220: "fvmulis", LR+LW, LR+LW, LW, LW,
221: "fvdivis", LR+LW, LR+LW, LW, LW,
222: "fvcmpis", LR+LW, LR+LW, LW, LW,
223: "fvflti", LR+LW, LW, LW, LW,
224: "fvfltis", LR+LW, LW, LW, LW,
225: "fvfixi", LR+LW, LR+LW, LW, LW,
226: "fvfixis", LR+LW, LW, LW, LW,
227: "fvdoublei", LR+LW, LW, LW, LW,
228: "fvsinglei", LR+LW, LR+LW, LW, LW,
229: 0
230: };
231:
232: init_builtins(){
233: register struct def_builtin * d; register i; register struct sym_bkt *s;
234: d = def_builtins;
235: while (d->bname){
236: s = lookup(d->bname);
237: s->csect_s = C_UNDEF;
238: s->attr_s = S_DEC | S_CRT;
239: for (i=0; i < sizeof d->ruse / sizeof d->ruse[0] ; i++){
240: s->builtin_s[i] = d->ruse[i];
241: }
242: d++;
243: }
244: }
245: #endif
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