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1.1 ! root 1: /* static char Y2681_h[]="@(#)2681.h 2.1.1.2"; */ ! 2: /* ! 3: * Signetics 2681 Dual UART ! 4: */ ! 5: ! 6: #ifndef _2681 ! 7: #define _2681 ! 8: ! 9: /* ! 10: * ! 11: * ! 12: * READ WRITE ! 13: * 7 0 7 0 ! 14: * +--------+ +--------+ ! 15: * (struct duart *) ->mr1_2a | | | | ! 16: * +--------+ +--------+ ! 17: * ! 18: * +--------+ +--------+ ! 19: * ->a_sr_csr | SRA | | CSRA | ! 20: * +--------+ +--------+ ! 21: * ! 22: * +--------+ ! 23: * ->a_cmnd RESERVED | CRA | ! 24: * +--------+ ! 25: * ! 26: * +--------+ +--------+ ! 27: * ->a_data | RHRA | | TXRA | ! 28: * +--------+ +--------+ ! 29: * ! 30: * +--------+ +--------+ ! 31: * ->ipc_acr | IPCR | | ACR | ! 32: * +--------+ +--------+ ! 33: * ! 34: * +--------+ +--------+ ! 35: * ->is_imr | ISR | | IMR | ! 36: * +--------+ +--------+ ! 37: * ! 38: * +--------+ +--------+ ! 39: * ->ctur | CTU | | CTUR | ! 40: * +--------+ +--------+ ! 41: * ! 42: * +--------+ +--------+ ! 43: * ->ctlr | CTL | | CTLR | ! 44: * +--------+ +--------+ ! 45: * ! 46: * +--------+ +--------+ ! 47: * ->mr1_2b | | | | ! 48: * +--------+ +--------+ ! 49: * ! 50: * +--------+ +--------+ ! 51: * ->b_sr_csr | SRB | | CSRB | ! 52: * +--------+ +--------+ ! 53: * ! 54: * +--------+ ! 55: * ->b_cmnd RESERVED | CRB | ! 56: * +--------+ ! 57: * ! 58: * +--------+ +--------+ ! 59: * ->b_data | RHRB | | THRB | ! 60: * +--------+ +--------+ ! 61: * ! 62: * +--------+ +--------+ ! 63: * ->ip_opcr | In.Prt | | OPCR | ! 64: * +--------+ +--------+ ! 65: * ! 66: * +--------+ +--------+ ! 67: * ->scc_sopbc | SCC | | SOPBC | ! 68: * +--------+ +--------+ ! 69: * ! 70: * +--------+ +--------+ ! 71: * ->scc_ropbc | SCC | | ROPBC | ! 72: * +--------+ +--------+ ! 73: */ ! 74: ! 75: struct duart ! 76: { ! 77: int : 16; int :8; unsigned char mr1_2a; /* Mode Register A Channels 1 & 2 */ ! 78: int : 16; int :8; unsigned char a_sr_csr; /* Status Reg. A / Clock Select Reg. A */ ! 79: int : 16; int :8; unsigned char a_cmnd; /* Command Register A */ ! 80: int : 16; int :8; unsigned char a_data; /* RX Holding / TX Holding Register A */ ! 81: ! 82: int : 16; int :8; unsigned char ipc_acr; /* Input Port Change / Aux. Control Register A */ ! 83: int : 16; int :8; unsigned char is_imr; /* Interrupt Status / Interrupt Mask Register A */ ! 84: int : 16; int :8; unsigned char ctur; /* Counter/Timer Upper Register */ ! 85: int : 16; int :8; unsigned char ctlr; /* Counter/Timer Lower Register */ ! 86: ! 87: int : 16; int :8; unsigned char mr1_2b; /* Mode Register B Channels 1 & 2 */ ! 88: int : 16; int :8; unsigned char b_sr_csr; /* Status Reg. B / Clock Select Reg. B */ ! 89: int : 16; int :8; unsigned char b_cmnd; /* Command Register B */ ! 90: int : 16; int :8; unsigned char b_data; /* RX Holding / TX Holding Register B */ ! 91: ! 92: int : 16; int :8; int :8; /* RESERVED */ ! 93: ! 94: int : 16; int :8; unsigned char ip_opcr; /* Input Port / Output Port Conf. Reg. */ ! 95: int : 16; int :8; unsigned char scc_sopbc;/* Start Counter Command / Set Output Port Bits Command */ ! 96: int : 16; int :8; unsigned char scc_ropbc;/* Stop Counter Command / Reset Output Port Bits Command */ ! 97: }; ! 98: ! 99: /* Register Bit Format Defines */ ! 100: ! 101: /* ! 102: * Mode Register 1 Channel A and B Defines ! 103: */ ! 104: ! 105: #define ENB_RX_RTS 0x80 ! 106: #define ENB_RXINT 0x40 ! 107: #define BLCK_ERR 0x20 ! 108: #define CHAR_ERR 0x00 ! 109: #define PAR_ENB 0x00 ! 110: #define FRC_PAR 0x08 ! 111: #define NO_PAR 0x10 ! 112: #define SPECIAL 0x18 ! 113: #define EVN_PAR 0x00 ! 114: #define ODD_PAR 0x04 ! 115: #define CBITS5 0x00 ! 116: #define CBITS6 0x01 ! 117: #define CBITS7 0x02 ! 118: #define CBITS8 0x03 ! 119: ! 120: /* ! 121: * Mode Register 2 Channel A and B Defines ! 122: */ ! 123: ! 124: #define NRML_MOD 0x00 ! 125: #define ENB_ECHO 0x40 ! 126: #define LCL_LOOP 0x80 ! 127: #define REM_LOOP 0xc0 ! 128: ! 129: #define ENB_TXRTS 0x20 ! 130: #define ENB_CTSTX 0x10 ! 131: ! 132: #define ZEROP563SB 0x00 ! 133: #define ZEROP625SB 0x01 ! 134: #define ZEROP688SB 0x02 ! 135: #define ZEROP750SB 0x03 ! 136: #define ZEROP813SB 0x04 ! 137: #define ZEROP875SB 0x05 ! 138: #define ZEROP938SB 0x06 ! 139: ! 140: #define ONEP000SB 0x07 ! 141: #define ONEP563SB 0x08 ! 142: #define ONEP625SB 0x09 ! 143: #define ONEP688SB 0x0a ! 144: #define ONEP750SB 0x0b ! 145: #define ONEP813SB 0x0c ! 146: #define ONEP875SB 0x0d ! 147: #define ONEP938SB 0x0e ! 148: ! 149: #define TWOP000SB 0x0f ! 150: ! 151: /* ! 152: * Clock Select Register Defines ! 153: */ ! 154: ! 155: #define BD50BPS 0x00 ! 156: #define BD75BPS 0x00 /* ACR[7]=SET2 */ ! 157: #define BD110BPS 0x11 ! 158: #define BD134BPS 0x22 ! 159: #define BD150BPS 0x33 /* ACR[7]=SET2 */ ! 160: #define BD200BPS 0x33 ! 161: #define BD300BPS 0x44 ! 162: #define BD600BPS 0x55 ! 163: #define BD1200BPS 0x66 ! 164: #define BD1050BPS 0x77 ! 165: #define BD1800BPS 0xaa /* ACR[7]=SET2 */ ! 166: #define BD2000BPS 0x77 /* ACR[7]=SET2 */ ! 167: #define BD2400BPS 0x88 ! 168: #define BD4800BPS 0x99 ! 169: #define BD7200BPS 0xaa ! 170: #define BD9600BPS 0xbb ! 171: #define BD19200BPS 0xcc /* ACR[7]=SET2 */ ! 172: #define BD38400BPS 0xcc ! 173: ! 174: /* ! 175: * Miscellaneous Commands for CRA/CRB ! 176: */ ! 177: ! 178: #define NO_OP 0x00 ! 179: #define RESET_MR 0x10 ! 180: #define RESET_RECV 0x20 ! 181: #define RESET_TRANS 0x30 ! 182: #define RESET_ERR 0x40 ! 183: #define RST_A_BCI 0x50 ! 184: #define STRT_BRK 0x60 ! 185: #define STOP_BRK 0x70 ! 186: #define DIS_TX 0x08 ! 187: #define ENB_TX 0x04 ! 188: #define DIS_RX 0x02 ! 189: #define ENB_RX 0x01 ! 190: ! 191: /* ! 192: * Status Register Defines for SRA/SRB ! 193: */ ! 194: ! 195: #define RCVD_BRK 0x80 ! 196: #define FRM_ERR 0x40 ! 197: #define PAR_ERR 0x20 ! 198: #define OVR_RUN 0x10 ! 199: #define XMT_EMT 0x08 ! 200: #define XMT_RDY 0x04 ! 201: #define FIFOFULL 0x02 ! 202: #define RCV_RDY 0x01 ! 203: ! 204: /* ! 205: * Register Defines for IPCR/OPCR ! 206: */ ! 207: ! 208: #define DCDA 0x01 ! 209: #define DCDB 0x02 ! 210: #define DTRA 0x01 ! 211: #define DTRB 0x02 ! 212: ! 213: #endif
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