![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to stin CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Research Unix] / researchv9 / jerq / sgs / comp|
Return to stin CVS log | Up to [Research Unix] / researchv9 / jerq / sgs / comp |
1.1 root 1: # @(#) stin : 1.12 4/20/84
2: # stin - input description for pcc2 code generator
3: #
4: #
5:
6: SHAPES
7:
8: # basic shapes
9:
10: F: 'FREE'; # evaluate for effects only
11: CC: 'CC'; # evaluate for condition codes (ignore value)
12:
13: # Different flavors of constants
14: Cplit: POSRANGE 6:0; # 0 - 63: positive literal
15: Cb: POSRANGE 8:1; # -128 - 127
16: Cs: SGRANGE 15:2; # -32768 - 32767
17: C: :4; # constant
18:
19: N: 'NAME' :8; # including address constants
20: T: 'TEMP' :5; # temporary
21: A: 'AUTO' :5; # auto
22: P: 'PARAM' :5; # incoming arg
23: R: 'REG' :0; # "register"
24:
25: # addressing modes
26:
27: STK: T, A, P; # K(%sp) or K(%ap)
28: ROFF: R, R+C, R-C;
29: OREG: *(*ROFF):9, *STK:9, *ROFF:5; # PCC1 "OREG" node
30: AWD1: STK, R, OREG, N; # addressable words
31: AWD: AWD1, *N:11; # same, including indirect of global
32: AWDnR: STK, OREG, N; # addressable words that aren't in registers
33: DAWD: STK, R, N; # directly addressable word
34: IAWD: OREG, *N:11; # AWD without DAWD
35:
36: AAWD: & AWD1:1;
37: STAWD: AWD1, AAWD, C; # structure AWD
38:
39: BC: 'CONV' AWD[cuc]; # character converted to int or short
40: SC: 'CONV' AWD[s]; # short converted to int
41: USC: 'CONV' AWD[us]; # unsigned short converted to int
42:
43: MEMADR: 'UAND' STK:1; # address of stack items
44:
45: BSRC: AWD[cuc], BC[iui], Cb; # character operand
46: HSRC: AWD[s], SC[iui], Cs; # short operands to int operations
47: HSRCnconv: AWD[sus], Cs; # any halfword source with no convert
48: # used for assignment, since there
49: # won't be a convert.
50: UHSRC: AWD[us], USC[iui], Cs;
51: WSRC: AWD[iuip], C;
52:
53: WSRCnC: AWD[iuip], C; # no conversion
54: UWSRCnC: AWD[uip]; # unsigned
55: SWSRCnC: AWD[i], C; # signed
56:
57: BDST: AWD[cuc];
58: HDST: AWD[sus];
59: SHDST: AWD[s];
60: WDST: AWD[iuip];
61:
62: SSRC: AWD[f]; # single
63: DSRC: AWD[d]; # double
64: SSRCconv: 'CONV' SSRC; # converted (to double) single
65: DSRCconv: 'CONV' DSRC; # converted (to single) double
66: FSRC: SSRC, DSRC, C;
67:
68: SDST: AWD[f];
69: DDST: AWD[d];
70: FDST: SDST,DDST;
71:
72: # useful subtrees to recognize
73:
74: FLD: 'FLD' AWD[cucsusiui]; # bit field
75: BFLD: 'FLD' AWD[cuc];
76: HFLD: 'FLD' AWD[sus];
77: WFLD: 'FLD' AWD[iui];
78:
79:
80: OPCODES
81:
82: DCOST :8; # default opcode cost
83:
84: # convert to/from double
85:
86: 'CONV' [iuip] SSRC {$1 $< $C} " movtsw AL,A1\n":24;
87: 'CONV' [iuip] DSRC {$1 $l $< $C} " movtdw AL,A1\n":24;
88: 'CONV' [sus] SSRC {$1 $< $C} "\tmovtsw\tAL,A1\n\tmovtwh\tA1,A1\n":32;
89: 'CONV' [sus] DSRC {$1 $< $l $C} "\tmovtdw\tAL,A1\n\tmovtwh\tA1,A1\n":32;
90: 'CONV' [cuc] SSRC {$1 $< $C} "\tmovtsw\tAL,A1\n\tmovtwb\tA1,A1\n":32;
91: 'CONV' [cuc] DSRC {$1 $< $l $C} "\tmovtdw\tAL,A1\n\tmovtwb\tA1,A1\n":32;
92: 'CONV' [f] WSRC {$1 $< $C} " movws AL,A1\n":24;
93: 'CONV' [d] WSRC {$1 $P $< $C} " movwd AL,A1\n":24;
94: 'CONV' [d] SSRC {$1 $P $< $C} " movsd AL,A1\n":24;
95: 'CONV' [f] DSRC {$1 $l $< $C} " movds AL,A1\n":24;
96: 'CONV' [f] AWD[us] {$1 $< $C} "\tmovzhw\tAL,A1\n\tmovws\tA1,A1\n":32;
97: 'CONV' [f] AWD[s] {$1 $< $C} "\tmovbhw\tAL,A1\n\tmovws\tA1,A1\n":32;
98: 'CONV' [f] AWD[cuc] {$1 $< $C} "\tmovzbw\tAL,A1\n\tmovws\tA1,A1\n":32;
99: 'CONV' [d] AWD[us] {$1 $P $l $< $C} "\tmovzhw\tAL,A1\n\tmovwd\tA1,A1\n":32;
100: 'CONV' [d] AWD[s] {$1 $P $l $< $C} "\tmovbhw\tAL,A1\n\tmovwd\tA1,A1\n":32;
101: 'CONV' [d] AWD[cuc] {$1 $P $l $< $C} "\tmovzbw\tAL,A1\n\tmovwd\tA1,A1\n":32;
102:
103: # integral conversions
104:
105: 'CONV'[sus] AWD[cuc] {$1 $<} "RL!1 movzbh AL,A1\n":14;
106: 'CONV'[sus] AWD[cuc] {$1 $< $C} " movzbh AL,A1\n":14;
107: 'CONV'[iuip] AWD[cuc] {$1 $< $C} " movzbw AL,A1\n":14;
108:
109: 'CONV'[iuip] AWD[s] {$1 $< $C} " movbhw AL,A1\n":14;
110: 'CONV'[iuip] AWD[us] {$1 $< $C} " movzhw AL,A1\n":14;
111:
112: 'CONV'[cuc] AWD[sus] {$1 $<} "RL!1 movthb AL,A1\n":14;
113: 'CONV'[cuc] AWD[iuip] {$1 $<} "RL!1 movtwb AL,A1\n":14;
114: 'CONV'[sus] AWD[iuip] {$1 $<} "RL!1 movtwh AL,A1\n":14;
115: 'CONV'[cuc] AWD[sus] {$1 $< $C} " movthb AL,A1\n":14;
116: 'CONV'[cuc] AWD[iuip] {$1 $< $C} " movtwb AL,A1\n":14;
117: 'CONV'[sus] AWD[iuip] {$1 $< $C} " movtwh AL,A1\n":14;
118:
119: # leaf nodes (Also matches some conversions of leaves)
120:
121: 'FLD' AWD {$1 $< $C} " extzv &ZHR,&SR,AL,A1\n":16;
122:
123: BSRC {$C} " cmpb AR,&0\nZb";
124: HSRC {$C} " cmph AR,&0\nZb";
125: WSRC {$C} " cmpw AR,&0\nZb";
126: AWD[f] {$C $r} " fcmps AR,&0.0\nZb":24;
127: AWD[d] {$C $r} " fcmpd AR,&0.0\nZb":24;
128:
129: WSRC {$1 $> } "RR!1 movw AR,A1\n";
130: HSRC {$1 $C $> } " movbhw AR,A1\n";
131: UHSRC {$1 $C $> } " movzhw AR,A1\n";
132: BSRC {$1 $C $> } " movzbw AR,A1\n";
133: AWD[f] {$1 $r $P $> } " movsd AR,A1\n";
134: DAWD[d] {$1 $r $P $>} "\tmovw AR,A1\n\tmovw ZDR,ZD1\n";
135: IAWD[d] {$1 $r $P $>} " movdd AR,A1\n";
136:
137: # constant initialization
138:
139: 'INIT' [cuc] C {$N} " ZB";
140: 'INIT' [sus] C {$N} " .half CL\n";
141: 'INIT' [iuip] C {$N} " .word CL\n";
142: 'INIT' [f] C {$N} " .single CL\n";
143: 'INIT' [d] C {$N} " .double CL\n";
144:
145: # function arguments
146:
147: 'ARG' WSRCnC {$N} " pushw AL\n";
148: 'ARG' AWD[s] {$N 1} "\tmovbhw\tAL,A1\n\tpushw\tA1\n":16;
149: 'ARG' AWD[us] {$N 1} "\tmovzhw\tAL,A1\n\tpushw\tA1\n":16;
150: 'ARG' AWD[c] {$N 1} "\tmovzbw\tAL,A1\n\tpushw\tA1\n":16;
151: 'ARG' DAWD[f] {1 $P $l} "\tmovsd\tAL,A1\n\tpushw\tA1\n\tpushw\tZD1\n":24;
152: 'ARG' IAWD[f] {1 $P $l $C} "\tmovsd\tAL,A1\n\taddw2\t&8,%sp\n\tmovdd\tA1,-8(%sp)\n":32;
153: 'ARG' DAWD[d] {$N $l} "\tpushw\tAL\n\tpushw\tZDL\n":24;
154: 'ARG' IAWD[d] {$N $l} "\taddw2\t&8,%sp\n\tmovdd\tAL,-8(%sp)\n":24;
155: 'ARG' MEMADR {$N} " pushaw A(LL)\n";
156:
157: # take address of
158:
159: 'UAND' AWDnR {$1 $<} " movaw AL,A1\n";
160:
161: = AWD,MEMADR {$L} " movaw A(RL),AL\n";
162: = AWD,MEMADR {$R} " movaw A(RL),AL\n";
163:
164: # arithmetic ops -- take advantage of mod N bit arithmetic
165:
166: + BSRC,BSRC {$1 $< $> $C}
167: "RR=1 addb2 AL,ARERL=1 addb2 AR,ALE addb3 AR,AL,A1\n";
168: + HSRC,HSRC {$1 $< $> $C}
169: "RR=1 addh2 AL,ARERL=1 addh2 AR,ALE addh3 AR,AL,A1\n";
170: + WSRC,WSRC {$1 $< $> $C}
171: "RR=1 addw2 AL,ARERL=1 addw2 AR,ALE addw3 AR,AL,A1\n";
172: + DSRC,DSRC {$1 $P $l $r $< $> $C}
173: "RR=1 faddd2 AL,ARERL=1 faddd2 AR,ALE faddd3 AR,AL,A1\n":6;
174:
175: - BSRC,BSRC {$1 $< $> $C} "RL!1\tsubb3\tAR,AL,A1\nRL=1\tsubb2\tAR,AL\n";
176: - HSRC,HSRC {$1 $< $> $C} "RL!1\tsubh3\tAR,AL,A1\nRL=1\tsubh2\tAR,AL\n";
177: - WSRC,WSRC {$1 $< $> $C} "RL!1\tsubw3\tAR,AL,A1\nRL=1\tsubw2\tAR,AL\n";
178: - DSRC,DSRC {$1 $P $l $r $< $> $C}
179: "RL!1 fsubd3 AR,AL,A1\nRL=1 fsubd2 AR,AL\n":6;
180:
181: 'UMINUS' BSRC {$1 $<} " \\M\\N\\E\\G\\B AL,A1\n";
182: 'UMINUS' HSRC {$1 $<} " mnegh AL,A1\n";
183: 'UMINUS' WSRC {$1 $<} " mnegw AL,A1\n";
184: 'UMINUS' DSRC {$1 $P $l $< $C} "\tfsubd3\tAL,&0.0,A1\n":24;
185:
186: # looks so gross because "expand" uses caps for itself
187: # BC and SC templates are used to reach around conversions explicitly
188: # because optim doesn't push down conversions around *.
189:
190: * BC[iuisus],BC[iuisus] {$1 $< $> $C}
191: "R(RL)=1 \\M\\U\\L\\B2 AL,ARER(LL)=1 \\M\\U\\L\\B2 AR,ALE \\M\\U\\L\\B3 AR,AL,A1\n":16;
192: * BSRC,BSRC {$1 $< $> $C} " \\M\\U\\L\\B3 AR,AL,A1\n":16;
193: * SC,SC {$1 $< $> $C}
194: "R(RL)=1 \\M\\U\\L\\H2 AL,ARER(LL)=1 \\M\\U\\L\\H2 AR,ALE \\M\\U\\L\\H3 AR,AL,A1\n":16;
195: * HSRC,HSRC {$1 $< $> $C} " \\M\\U\\L\\H3 AR,AL,A1\n":16;
196: * WSRC,WSRC {$1 $< $> $C}
197: "RR=1 mulw2 AL,ARERL=1 mulw2 AR,ALE mulw3 AR,AL,A1\n":16;
198: * DSRC,DSRC {$1 $P $l $r $[ $] $C}
199: "RR=1 fmuld2 AL,ARERL=1 fmuld2 AR,ALE fmuld3 AR,AL,A1\n":24;
200:
201: / UWSRCnC,WSRCnC {$1 $< $> $C} "RL!1\tudivw3\tAR,AL,A1\nRL=1\tudivw2\tAR,AL\n":18;
202: / WSRCnC,UWSRCnC {$1 $< $> $C} "RL!1\tudivw3\tAR,AL,A1\nRL=1\tudivw2\tAR,AL\n":18;
203: / WSRCnC,WSRCnC {$1 $< $> $C} "RL!1\tdivw3\tAR,AL,A1\nRL=1\tdivw2\tAR,AL\n":18;
204: / DSRC,DSRC {$1 $P $l $r $< $> $C}
205: "RL!1 fdivd3 AR,AL,A1\nRL=1 fdivd2 AR,AL\n":32;
206:
207: % UWSRCnC,WSRCnC {$1 $< $> $C} "RL!1\tumodw3\tAR,AL,A1\nRL=1\tumodw2\tAR,AL\n":18;
208: % WSRCnC,UWSRCnC {$1 $< $> $C} "RL!1\tumodw3\tAR,AL,A1\nRL=1\tumodw2\tAR,AL\n":18;
209: % WSRCnC,WSRCnC {$1 $< $> $C} "RL!1\tmodw3\tAR,AL,A1\nRL=1\tmodw2\tAR,AL\n":18;
210:
211: # logical ops -- again, take advantage
212: #
213: # WE 32000 versions of these instructions actually do set
214: # condition codes correctly, even though IS25 doesn't require it
215:
216: & BSRC,BSRC {$C} " bitb AL,AR\n";
217: & HSRC,HSRC {$C} " bith AL,AR\n";
218: & WSRC,WSRC {$C} " bitw AL,AR\n";
219:
220: & BSRC,BSRC {$C $1 $> $<}
221: "RR=1 andb2 AL,ARERL=1 andb2 AR,ALE andb3 AR,AL,A1\n";
222: & HSRC,HSRC {$C $1 $> $<}
223: "RR=1 andh2 AL,ARERL=1 andh2 AR,ALE andh3 AR,AL,A1\n";
224: & WSRC,WSRC {$C $1 $> $<}
225: "RR=1 andw2 AL,ARERL=1 andw2 AR,ALE andw3 AR,AL,A1\n";
226:
227: | BSRC,BSRC {$C $1 $> $<}
228: "RR=1 orb2 AL,ARERL=1 orb2 AR,ALE orb3 AR,AL,A1\n";
229: | HSRC,HSRC {$C $1 $> $<}
230: "RR=1 orh2 AL,ARERL=1 orh2 AR,ALE orh3 AR,AL,A1\n";
231: | WSRC,WSRC {$C $1 $> $<}
232: "RR=1 orw2 AL,ARERL=1 orw2 AR,ALE orw3 AR,AL,A1\n";
233:
234: ^ BSRC,BSRC {$C $1 $> $<}
235: "RR=1 xorb2 AL,ARERL=1 xorb2 AR,ALE xorb3 AR,AL,A1\n";
236: ^ HSRC,HSRC {$C $1 $> $<}
237: "RR=1 xorh2 AL,ARERL=1 xorh2 AR,ALE xorh3 AR,AL,A1\n";
238: ^ WSRC,WSRC {$C $1 $> $<}
239: "RR=1 xorw2 AL,ARERL=1 xorw2 AR,ALE xorw3 AR,AL,A1\n";
240:
241: ~ BSRC {$1 $<} " mcomb AL,A1\n";
242: ~ HSRC {$1 $<} " mcomh AL,A1\n";
243: ~ WSRC {$1 $<} " mcomw AL,A1\n";
244:
245: # shifts
246:
247: << WSRCnC,WSRCnC {$1 $> $< $C} "\t\\L\\L\\S\\W3\tAR,AL,A1\n";
248:
249: >> WSRCnC,WSRCnC {$1 $> $< $C} "\t\\L\\R\\S\\W3\tAR,AL,A1\n";
250:
251: # assignment ops -- mod N bits!
252:
253: += BDST,BSRC {$L $C} " addb2 AR,AL\n";
254: += HDST,HSRC {$L $C} " addh2 AR,AL\n";
255: += WDST,WSRC {$L $C} " addw2 AR,AL\n";
256: += DDST,DSRC {$L $r $l $C} " faddd2 AR,AL\n":24;
257:
258: -= BDST,BSRC {$L $C} " subb2 AR,AL\n";
259: -= HDST,HSRC {$L $C} " subh2 AR,AL\n";
260: -= WDST,WSRC {$L $C} " subw2 AR,AL\n";
261: -= DDST,DSRC {$L $r $l $C} " fsubd2 AR,AL\n":24;
262:
263: *= BDST,BSRC {$L $C} "\t\\M\\U\\L\\B2\tAR,AL\n":16;
264: *= HDST,HSRC {$L $C} "\t\\M\\U\\L\\H2\tAR,AL\n":16;
265: *= WDST,WSRC {$L $C} " mulw2 AR,AL\n":16;
266: *= DDST,DSRC {$L $r $l $C} " fmuld2 AR,AL\n":32;
267:
268: /= WDST,UWSRCnC {$L $C} " udivw2 AR,AL\n":18;
269: /= AWD[uip],WSRCnC { } " udivw2 AR,AL\n":18;
270: /= AWD[iuip],WSRCnC { } " divw2 AR,AL\n":18;
271: /= DDST,DSRC {$L $r $l $C} " fdivd2 AR,AL\n":32;
272:
273: %= AWD[uip],WSRCnC { } " umodw2 AR,AL\n":18;
274: %= WDST,UWSRCnC {$L $C} " umodw2 AR,AL\n":18;
275: %= WDST,WSRCnC {$L $C} " modw2 AR,AL\n":18;
276:
277: |= BDST,BSRC {$L} " orb2 AR,AL\n";
278: |= HDST,HSRC {$L} " orh2 AR,AL\n";
279: |= WDST,WSRC {$L} " orw2 AR,AL\n";
280:
281: &= BDST,BSRC {$L} " andb2 AR,AL\n";
282: &= HDST,HSRC {$L} " andh2 AR,AL\n";
283: &= WDST,WSRC {$L} " andw2 AR,AL\n";
284:
285: ^= BDST,BSRC {$L} " xorb2 AR,AL\n";
286: ^= HDST,HSRC {$L} " xorh2 AR,AL\n";
287: ^= WDST,WSRC {$L} " xorw2 AR,AL\n";
288:
289: <<= WDST,WSRCnC {$L $C} "\t\\L\\L\\S\\W3\tAR,AL,AL\n";
290:
291: >>= WDST,WSRCnC {$L $C} "\t\\L\\R\\S\\W3\tAR,AL,AL\n";
292:
293: # comparisons
294:
295: 'CMP' WSRC,WSRC {$C} " cmpw AL,AR\nZb";
296: 'CMP' HSRC,HSRC {$C } " cmph AL,AR\nZb";
297: 'CMP' BSRC,BSRC {$C} " cmpb AL,AR\nZb";
298:
299: 'CMP' SSRC,SSRC {$C} " fcmps AL,AR\nZb";
300: 'CMP' SSRCconv,SSRCconv {$C} " fcmps AL,AR\nZb";
301: 'CMP' DSRC,DSRC {$C} " fcmpd AL,AR\nZb";
302:
303: # post increment, decrement (rhs is amount)
304:
305: ++ BDST,C {$N} " addb2 &CR,AL\n";
306: ++ HDST,C {$N} " addh2 &CR,AL\n";
307: ++ WDST,C {$N} " addw2 &CR,AL\n";
308: ++ DDST,C {$l $N} " faddd2 &CR,AL\n":24;
309:
310: ++ BDST,C {$1 $l} " movb AL,A1\n addb2 &CR,AL\n":16;
311: ++ HDST,C {$1 $l} " movh AL,A1\n addh2 &CR,AL\n":16;
312: ++ WDST,C {$1 $l} " movw AL,A1\n addw2 &CR,AL\n":16;
313: ++ DAWD[d],C {$1 $P $l $l $l} "\tmovw\tAL,A1\n\tmovw\tZDL,ZD1\n\tfaddd2\t&CR,AL\n":20;
314: ++ IAWD[d],C {$1 $P $l $l $l} " movdd AL,A1\n faddd2 &CR,AL\n":32;
315:
316: -- BDST,C {$N} " subb2 &CR,AL\n";
317: -- HDST,C {$N} " subh2 &CR,AL\n";
318: -- WDST,C {$N} " subw2 &CR,AL\n";
319: -- DDST,C {$l $N} " fsubd2 &CR,AL\n":24;
320:
321: -- BDST,C {$1 $l} " movb AL,A1\n subb2 &CR,AL\n":16;
322: -- HDST,C {$1 $l} " movh AL,A1\n subh2 &CR,AL\n":16;
323: -- WDST,C {$1 $l} " movw AL,A1\n subw2 &CR,AL\n":16;
324: -- DAWD[d],C {$1 $P $l $l $l} "\tmovw\tAL,A1\n\tmovw\tZDL,ZD1\n\tfsubd2\t&CR,AL\n":24;
325: -- IAWD[d],C {$1 $P $l $l $l} " movdd AL,A1\n fsubd2 &CR,AL\n":24;
326:
327: -- BFLD,C {1 $N}
328: "\textzv\t&ZHL,&SL,AL,A1\n\tsubb2\t&CR,A1\n\tinsv\tA1,&ZHL,&SL,AL\n";
329: -- HFLD,C {1 $N}
330: "\textzv\t&ZHL,&SL,AL,A1\n\tsubh2\t&CR,A1\n\tinsv\tA1,&ZHL,&SL,AL\n";
331: -- WFLD,C {1 $N}
332: "\textzv\t&ZHL,&SL,AL,A1\n\tsubw2\t&CR,A1\n\tinsv\tA1,&ZHL,&SL,AL\n";
333:
334: -- BFLD,C {2 $1 $l}
335: "\textzv\t&ZHL,&SL,AL,A1\n\tmovw\tA1,A2\n\tsubb2\t&CR,A2\n\tinsv\tA2,&ZHL,&SL,AL\n":16;
336: -- HFLD,C {2 $1 $l}
337: "\textzv\t&ZHL,&SL,AL,A1\n\tmovw\tA1,A2\n\tsubh2\t&CR,A2\n\tinsv\tA2,&ZHL,&SL,AL\n":16;
338: -- WFLD,C {2 $1 $l}
339: "\textzv\t&ZHL,&SL,AL,A1\n\tmovw\tA1,A2\n\tsubw2\t&CR,A2\n\tinsv\tA2,&ZHL,&SL,AL\n":16;
340:
341: # assignment
342:
343: # same size or smaller integers
344:
345: = WDST,WSRC {$L} "RL!R movw AR,AL\n";
346: = HDST,HSRCnconv {$L} "RL!R movh AR,AL\n";
347: = BDST,BSRC {$L} "RL!R movb AR,AL\n";
348: = WDST,WSRC {$R $C} " movw AR,AL\n";
349: = HDST,HSRCnconv {$R $C} " movh AR,AL\n";
350: = BDST,BSRC {$R $C} " movb AR,AL\n";
351:
352: # bigger integers
353:
354: = HDST,BSRC {$L $C} " movzbh AR,AL\n":14;
355: = WDST,BSRC {$L $C} " movzbw AR,AL\n":14;
356:
357: = WDST,HSRC {$L $C} " movbhw AR,AL\n":14;
358: = WDST,UHSRC {$L $C} " movzhw AR,AL\n":14;
359:
360: # floating point -- better have conversions where appropriate!
361:
362: = SDST,SSRC {$L} " movw AR,AL\n";
363: = SDST,SSRC {$R} " movw AR,AL\n";
364: = DAWD[d],DAWD[d] {$L $r $l} "\tmovw\tAR,AL\n\tmovw\tZDR,ZDL\n":24;
365: = IAWD[d],DSRC {$L $r $l} " movdd AR,AL\n":24;
366: = DDST,IAWD[d] {$L $r $l} " movdd AR,AL\n":24;
367: = DAWD[d],DAWD[d] {$R $r $l} "\tmovw\tAR,AL\n\tmovw\tZDR,ZDL\n":24;
368: = IAWD[d],DSRC {$R $r $l} " movdd AR,AL\n":24;
369: = DDST,IAWD[d] {$R $r $l} " movdd AR,AL\n":24;
370: = SDST,DSRCconv[f] {$L $r} " movds AR,AL\n":24;
371: = DDST,SSRCconv[d] {$L $l} " movsd AR,AL\n":24;
372:
373: = FLD,BSRC {$L 1 $C}
374: "RR!1\tmovzbw AR,A1\n\tinsv\tA1,&ZHL,&SL,AL\n":18;
375: = FLD,HSRC {$L 1 $C}
376: "RR!1\tmovzhw AR,A1\n\tinsv\tA1,&ZHL,&SL,AL\n":18;
377: = FLD,UHSRC {$L 1 $C}
378: "RR!1\tmovzhw AR,A1\n\tinsv\tA1,&ZHL,&SL,AL\n":18;
379: = FLD,WSRC {$L 1 $C} "\tinsv\tAR,&ZHL,&SL,AL\n":16;
380:
381: # structure assignment, arguments
382:
383: # complicated. do it in zzzcode()
384:
385: 'STASG' STAWD,STAWD {$L 3 $]} "ZS":24;
386:
387: 'STARG' STAWD {$N 3 $[} "Zs":24;
388:
389: # goto (for fortran)
390:
391: 'GOTO' C {$N} " jmp CL\n";
392: 'GOTO' STK {$N} " jmp *AL\n";
393:
394: # comma (list separator)
395:
396: 'CM' F,F {$N} "";
397:
398: # comma op (eval left, eval right, return right value)
399:
400: 'COMOP' F,F {$N} "";
401: 'COMOP' F,R {$R} "";
402: 'COMOP' F,CC {$C} "";
403:
404: # CALL
405:
406: 'CALL' C,F {$A $1} "\tcall\t&Zc,CL\n";
407: 'CALL' R,F {$A $1} "\tcall\t&Zc,0(AL)\n";
408: 'CALL' N,F {$A $1} "\tcall\t&Zc,*AL\n";
409: 'CALL' STK,F {$A $1} "\tcall\t&Zc,*AL\n";
410:
411: 'UCALL' C {$A $1} " call &Zc,CL\n";
412: 'UCALL' R {$A $1} " call &Zc,0(AL)\n";
413: 'UCALL' N {$A $1} " call &Zc,*AL\n";
414: 'UCALL' STK {$A $1} " call &Zc,*AL\n";
415:
416: # generate a label
417:
418: 'GENLAB' F {$N} ".\\LL:\n";
419: 'GENLAB' R {$L} ".\\LL:\n";
420: 'GENLAB' CC {$C} ".\\LL:\n";
421:
422: # conditional branch
423:
424: 'GENBR' CC {$N} " ZC";
425:
426: # generate a branch
427:
428: 'GENUBR' F {$N} " jmp .\\LL\n";
429: 'GENUBR' C {$N} " jmp .\\LL\n";
430: 'GENUBR' R {$N} " jmp 0(AL)\n";
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.