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1.1 root 1: #include "asm.pri"
2: #include "m68kasm.h"
3: #include "format.pub"
4: #include "core.pub"
5: SRCFILE("m68kasm.c")
6:
7: M68kInstr::M68kInstr(Asm*a,long l):(a,l&1?l+1:l) { tab = 0; display(); }
8: Instr *M68kAsm::newInstr(long a) { return (Instr*) new M68kInstr(this,a); }
9: M68kAsm::M68kAsm(Core *c):(c) { }
10: char *M68kAsm::literaldelimiter() { return "&"; }
11:
12: const short SZ_MASK = 00300, SZ_SHIFT = 6; // bits (7-6)
13: const short DEA_MASK = 00077; // bits (5-0)
14: const short DRG_MASK = 00007; // bits (2-0)
15: const short DRGL_MASK = 07000; // bits (11-9)
16: const short DBR_MASK = 00377; // bits (7-0)
17: const short DAQ_MASK = 07000; // bits (11-9)
18: const short DEAM_MASK = 07700; // bits (11-6)
19: const short DMQ_MASK = 00377; // bits (7-0)
20:
21: short OpMask[] = {
22: 0, // DIG 0 /* ignore this address */
23: DEA_MASK, // DEA 1 /* E.A. to low order 6 bits */
24: DRG_MASK, // DRG 2 /* register to low order 3 bits */
25: DRGL_MASK, // DRGL 3 /* register to bits 11-9 */
26: DBR_MASK, // DBR 4 /* branch offset (short) */
27: DMQ_MASK, // DMQ 5 /* move-quick 8-bit value */
28: DAQ_MASK, // DAQ 6 /* add-quick 3-bit value in 11-9 */
29: 0, // DIM 7 /* Immediate value, according to size */
30: DEAM_MASK, // DEAM 8 /* E.A. to bits 11-6 as in move */
31: 0, // DBCC 9 /* branch address as in "dbcc" */
32: 0, // DIMH 10 /* Immediate forced to be 1 word */
33: 0, // D2L 11 /* register to bits 0-2 of next word */
34: 0, // D2H 12 /* register to bits 12-14 of next word */
35: 0, // DBL 13 /* qty in bits 0-5 of next word */
36: 0, // DBH 14 /* qty in bits 6-11 of next word */
37: 0, // DCR 15 /* control reg a bit combination in 0-11 */
38: };
39:
40: char *M68kInstr::dotbwl()
41: {
42: // must be +/- 1?
43: if( (tab[1].opname && !strcmp(tab->opname, tab[1].opname))
44: || (tab[-1].opname && !strcmp(tab->opname, tab[-1].opname))
45: || tab->size == BWL )
46: switch( size ){
47: case B : return "b";
48: case W : return "w";
49: case L : return "l";
50: }
51: return "";
52: }
53:
54: int M68kInstr::imm_bytes(short addr, short disp)
55: {
56: int bytes = 0;
57: switch( disp ){
58: case DIMH: bytes = 2; break;
59: case DIM: switch(size){
60: case B:
61: case W: bytes = 2; break;
62: case L: bytes = 4; break;
63: }
64: if( addr&H ) bytes = 2; break;
65: }
66: switch(bytes){
67: case 2: immval = _asm->core->peekcode(next)->sht; break;
68: case 4: immval = _asm->core->peekcode(next)->lng; break;
69: }
70: return bytes;
71: }
72:
73: short M68kInstr::sizemask()
74: {
75: static char bwl[4] = { B, W, L, 0 };
76: size = tab->size;
77: if( size!=BWL ) return 0;
78: size = bwl[(opword0>>SZ_SHIFT)&3];
79: return size ? SZ_MASK : 0;
80: }
81:
82: char *M68kInstr::ea()
83: {
84: if( mode>=1 && mode<=6 ) reg += 8;
85: switch( mode ){
86: case 0: return regarg("%s%s", fmt&F_SYMBOLIC|F_NONE);
87: case 1: return regarg("%s%s", fmt&F_SYMBOLIC|F_NONE);
88: case 2: return regarg("%s(%s)", fmt&F_SYMBOLIC|F_NONE);
89: case 3: return regarg("%s(%s)+", fmt&F_SYMBOLIC|F_NONE);
90: case 4: return regarg("%s-(%s)", fmt&F_SYMBOLIC|F_NONE);
91: case 5: m = m.sht; next += 2;
92: return regarg("%s(%s)", fmt|F_MASKEXT16);
93: case 6: short brief = m.sht; next+= 2;
94: if( brief & 0400 ) return "full";
95: char ireg = (brief>>12)&15;
96: m = (char)brief;
97: int scale = (brief>>9)&3;
98: scale = 1<<scale;
99: char *wl = brief&04000 ? "l" : "w";
100: char *pre = regarg("%s(%s,", fmt&F_SYMBOLIC|F_NONE);
101: return sf("%s%s.%s*%d)", pre, _asm->core->regname(ireg), wl, scale);
102: case 7:
103: switch( reg ){
104: case 0: m = m.sht; next += 2; return symbolic();
105: case 1: m = m.lng; next += 4; return symbolic();
106: case 4: switch( size ){
107: case B: m = m.sht; next += 2; return literal(F_MASKEXT8|fmt);
108: case W: m = m.sht; next += 2; return literal(F_MASKEXT16|fmt);
109: case L: m = m.lng; next += 4; return literal(fmt);
110: }
111: return "<imm?>";
112: }
113: }
114: return sf("mode=%d:reg=%d", mode, reg);
115: }
116:
117: char *M68kInstr::dbr(char x)
118: {
119: switch( x ){
120: case 0: m = next + m.sht; next += 2; break;
121: case -1: m = next + m.lng; next += 4; break;
122: default: m = next + x;
123: }
124: return symbolic();
125: }
126:
127: char *M68kInstr::dbh()
128: {
129: if( opword1&0004000 ){
130: reg = (opword1>>6)&7;
131: return regarg("%s%s", fmt&F_SYMBOLIC|F_NONE);
132: }
133: m = (opword1>>6)&31;
134: return literal(fmt);
135: }
136:
137: char *M68kInstr::dbl()
138: {
139: if( opword1&0000040 ){
140: reg = opword1&7;
141: return regarg("%s%s", fmt&F_SYMBOLIC|F_NONE);
142: }
143: m = opword1&31;
144: return literal(fmt);
145: }
146:
147: char *M68kInstr::dcr()
148: {
149: next += 2;
150: switch( opword1&0xFFF ){
151: case 0x000: return "sfc";
152: case 0x001: return "dfc";
153: case 0x002: return "cacr";
154: case 0x800: return "usp";
155: case 0x801: return "vbr";
156: case 0x802: return "caar";
157: case 0x803: return "msp";
158: case 0x804: return "vbr";
159: }
160: return "<dcr>";
161: }
162:
163: char *M68kInstr::arg(int i)
164: {
165: short disp;
166: short addr;
167: switch( i ){ // !!
168: case 0: disp = tab->a1disp; addr = tab->addr1; break;
169: case 1: disp = tab->a2disp; addr = tab->addr2; break;
170: case 2: disp = tab->a3disp; addr = tab->addr3; break;
171: case 3: disp = tab->a4disp; addr = tab->addr4; break;
172: }
173:
174: disp &= 15;
175: short mask = OpMask[disp];
176: short x = mask ? (opword0&mask)/(((((~mask)+1)^(~mask))+1)>>1) : 0;
177: m = *_asm->core->peekcode(next);
178: switch( addr ){
179: case AREG+C: return "ccr";
180: case AREG+SR: return "sr";
181: }
182: switch( disp ){
183: case DEA: mode = x>>3; reg = x&7; return ea();
184: case DRG: // fall thru
185: case DRGL:reg = x;
186: if( addr&A ) reg += 8;
187: return regarg("%s%s",fmt&F_SYMBOLIC|F_NONE);
188: case DBR: return dbr(x);
189: case DMQ: m = (long)(char)x; return literal(F_MASKEXT16|fmt);
190: case DAQ: if( !x ) x = 8; m = x; return literal(fmt);
191: case DIMH: // fall thru
192: case DIM: if( (addr&H)
193: || addr==AIMM ) { m = immval; return literal(F_MASKEXT16|fmt);}
194: return "DIM";
195: case DEAM:mode = x&7; reg = x>>3; return ea();
196: case DBCC:m = m.sht+next; next += 2; return symbolic();
197: case D2L: return "D2L";
198: case D2H: reg = (opword1>>12)&15;
199: return regarg("%s%s", fmt&F_SYMBOLIC|F_NONE);
200: case DBH: return dbh();
201: case DBL: return dbl();
202: case DCR: return dcr();
203: }
204: return Instr::arg(i);
205: }
206:
207: int M68kInstr::nargs()
208: {
209: if( !tab->addr1 ) return 0;
210: if( !tab->addr2 ) return 1;
211: if( !tab->addr3 ) return 2;
212: if( !tab->addr4 ) return 3;
213: return 4;
214: }
215:
216: int M68kInstr::argtype(int)
217: {
218: return 0;
219: }
220:
221: struct m68koptab M68kOpTab[] = {
222:
223: {0140400,"abcd",B, SIG, AREG+D, DRG, AREG+D, DRGL, 0},
224: {0140410,"abcd",B, SIG, ADEC, DRG, ADEC, DRGL, 0},
225:
226: {0050000,"add", BWL, SD, AIMM+Q, DAQ, AGEN+AL,DEA, 0},
227: {0003000,"add", BWL, SD, AIMM, DIM, AGEN+AL+DA,DEA, 0},
228: {0150000,"add", BWL, SD, AGEN, DEA, AREG+D, DRGL, 0},
229: {0150400,"add", BWL, SD, AREG+D, DRGL, AGEN+AM,DEA, 0},
230: {0150300,"add", W, SIG, AGEN, DEA, AREG+A, DRGL, 0},
231: {0150700,"add", L, SIG, AGEN, DEA, AREG+A, DRGL, ISL},
232:
233: {0150400,"addx",BWL, SD, AREG+D, DRG, AREG+D, DRGL, 0},
234: {0150410,"addx",BWL, SD, ADEC, DRG, ADEC, DRGL, 0},
235:
236: {0001174,"and", W, SIG, AIMM, DIM, AREG+SR,DIG, 0},
237: {0001074,"and", B, SIG, AIMM, DIM, AREG+C, DIG, 0},
238: {0001000,"and", BWL, SD, AIMM, DIM, AGEN+AL+DA,DEA, 0},
239: {0140000,"and", BWL, SD, AGEN+DA,DEA, AREG+D, DRGL, 0},
240: {0140400,"and", BWL, SD, AREG+D, DRGL, AGEN+AM,DEA, 0},
241:
242: {0160700,"asl", W, SIG, AIMM+O, DIG, AGEN+AM,DEA, ISH},
243: {0160400,"asl", BWL, SD, AIMM+Q, DAQ, AREG+D, DRG, ISH},
244: {0160440,"asl", BWL, SD, AREG+D, DRGL, AREG+D, DRG, ISH},
245:
246: {0160300,"asr", W, SIG, AIMM+O, DIG, AGEN+AM,DEA, ISH},
247: {0160000,"asr", BWL, SD, AIMM+Q, DAQ, AREG+D, DRG, ISH},
248: {0160040,"asr", BWL, SD, AREG+D, DRGL, AREG+D, DRG, ISH},
249:
250: {0165300,"bfchg",0, 0, AGEN+BF,DEA, ABIT, DBH, I2W, 0, ABIT, DBL},
251: {0166300,"bfclr",0, 0, AGEN+BF,DEA, ABIT, DBH, I2W, 0, ABIT, DBL},
252: {0165700,"bfexts",0, 0, AGEN+BF,DEA, ABIT, DBH, I2W, 0, ABIT, DBL, AREG+D, D2H},
253: {0164700,"bfextu",0, 0, AGEN+BF,DEA, ABIT, DBH, I2W, 0, ABIT, DBL, AREG+D, D2H},
254: {0166700,"bfffo",0, 0, AGEN+BF,DEA, ABIT, DBH, I2W, 0, ABIT, DBL, AREG+D, D2H},
255: {0167700,"bfins",0, 0, AREG+D, D2H, AGEN+BF,DEA, I2W, 0, ABIT, DBH, ABIT, DBL},
256: {0167300,"bfset",0, 0, AGEN+BF,DEA, ABIT, DBH, I2W, 0, ABIT, DBL},
257: {0164300,"bftst",0, 0, AGEN+BF,DEA, ABIT, DBH, I2W, 0, ABIT, DBL},
258:
259: //{0060000,"br", B, SIG, AEXP, DBR, 0, 0, 0},
260: {0060000,"bra", B, SIG, AEXP, DBR, 0, 0, 0},
261: {0061000,"bhi", B, SIG, AEXP, DBR, 0, 0, 0},
262: //{0062000,"bhs", B, SIG, AEXP, DBR, 0, 0, 0},
263: {0062000,"bcc", B, SIG, AEXP, DBR, 0, 0, 0},
264: {0063000,"bne", B, SIG, AEXP, DBR, 0, 0, 0},
265: {0064000,"bvc", B, SIG, AEXP, DBR, 0, 0, 0},
266: {0065000,"bpl", B, SIG, AEXP, DBR, 0, 0, 0},
267: {0066000,"bge", B, SIG, AEXP, DBR, 0, 0, 0},
268: {0067000,"bgt", B, SIG, AEXP, DBR, 0, 0, 0},
269: {0061400,"bls", B, SIG, AEXP, DBR, 0, 0, 0},
270: //{0062400,"blo", B, SIG, AEXP, DBR, 0, 0, 0},
271: {0062400,"bcs", B, SIG, AEXP, DBR, 0, 0, 0},
272: {0063400,"beq", B, SIG, AEXP, DBR, 0, 0, 0},
273: {0064400,"bvs", B, SIG, AEXP, DBR, 0, 0, 0},
274: {0065400,"bmi", B, SIG, AEXP, DBR, 0, 0, 0},
275: {0066400,"blt", B, SIG, AEXP, DBR, 0, 0, 0},
276: {0067400,"ble", B, SIG, AEXP, DBR, 0, 0, 0},
277:
278: {0000500,"bchg",0, 0, AREG+D, DRGL, AGEN+AL+DA,DEA, 0},
279: {0004100,"bchg",0, 0, AIMM+H, DIM, AGEN+AL+DA,DEA, 0},
280:
281: {0000600,"bclr",0, 0, AREG+D, DRGL, AGEN+AL+DA,DEA, 0},
282: {0004200,"bclr",0, 0, AIMM+H, DIM, AGEN+AL+DA,DEA, 0},
283:
284: {0000700,"bset",0, 0, AREG+D, DRGL, AGEN+AL+DA,DEA, 0},
285: {0004300,"bset",0, 0, AIMM+H, DIM, AGEN+AL+DA,DEA, 0},
286:
287: {0060400,"bsr", B, SIG, AEXP, DBR, 0, 0, 0},
288:
289: {0000400,"btst",0, 0, AREG+D, DRGL, AGEN+DA,DEA, 0},
290: {0004000,"btst",0, 0, AIMM+H, DIM, AGEN+DA,DEA, 0},
291:
292: {0040600,"chk", W, SIG, AGEN, DEA, AREG+D, DRGL, 0},
293:
294: {0041000,"clr", BWL, SD, AGEN+AL+DA,DEA, 0, 0, 0},
295:
296: {0006000,"cmp", BWL, SD, AGEN+AL+DA,DEA, AIMM, DIM, 0},
297: {0130000,"cmp", BWL, SD, AREG+D, DRGL, AGEN, DEA, 0},
298: {0130300,"cmp", W, SIG, AREG+A, DRGL, AGEN, DEA, 0},
299: {0130700,"cmp", L, SIG, AREG+A, DRGL, AGEN, DEA, ISL},
300: {0130410,"cmp", BWL, SD, AINC, DRGL, AINC, DRG, 0},
301:
302: {0050310,"dbt", 0, 0, AREG+D, DRG, AEXP, DBCC, 0},
303: {0051310,"dbhi",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
304: {0052310,"dbhs",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
305: {0053310,"dbne",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
306: {0052310,"dbcc",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
307: {0054310,"dbvc",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
308: {0055310,"dbpl",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
309: {0056310,"dbge",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
310: {0057310,"dbgt",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
311: {0051710,"dbls",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
312: {0050710,"dbr", 0, 0, AREG+D, DRG, AEXP, DBCC, 0},
313: {0050710,"dbf", 0, 0, AREG+D, DRG, AEXP, DBCC, 0},
314: {0050710,"dbra",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
315: {0052710,"dblo",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
316: {0053710,"dbeq",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
317: {0052710,"dbcs",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
318: {0054710,"dbvs",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
319: {0055710,"dbmi",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
320: {0056710,"dblt",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
321: {0057710,"dble",0, 0, AREG+D, DRG, AEXP, DBCC, 0},
322:
323: {0100700,"divs",W, SIG, AGEN+DA,DEA, AREG+D, DRGL, 0},
324: /*
325: * tricky stuff here. divs.l is really a 3 operand instruction but it can be
326: * parsed as a two operand one, in which case the second argument is copied
327: * in outins() and the remainder is discarded. honest, read the 68020 manual.
328: */
329: {0046100,"divs",L, SIG, AGEN+DA,DEA, AREG+D, D2L, I2W, 0004000, AREG+D, D2H},
330: {0046100,"divs3",L, SIG, AGEN+DA,DEA, AREG+D, D2L, I2W, 0004000, AREG+D, D2H},
331:
332: {0046100,"divsl",L, SIG, AGEN+DA,DEA, AREG+D, D2L, I2W, 0006000, AREG+D, D2H},
333:
334: {0100300,"divu",W, SIG, AGEN+DA,DEA, AREG+D, DRGL, 0},
335: {0046100,"divu",L, SIG, AGEN+DA,DEA, AREG+D, D2L, I2W, 0000000, AREG+D, D2H},
336: {0046100,"divu3",L, SIG, AGEN+DA,DEA, AREG+D, D2L, I2W, 0000000, AREG+D, D2H},
337:
338: {0046100,"divul",L, SIG, AGEN+DA,DEA, AREG+D, D2L, I2W, 0002000, AREG+D, D2H},
339:
340: {0005000,"eor", BWL, SD, AIMM, DIM, AGEN+AL+DA,DEA, 0},
341: {0005074,"eor", B, SIG, AIMM, DIM, AREG+C, DIG, 0},
342: {0005174,"eor", W, SIG, AIMM, DIM, AREG+SR,DIG, 0},
343: {0130400,"eor", BWL, SD, AREG+D, DRGL, AGEN+AL+DA,DEA, 0},
344:
345: {0140500,"exg", 0, 0, AREG+D, DRG, AREG+D, DRGL, 0},
346: {0140510,"exg", 0, 0, AREG+A, DRG, AREG+A, DRGL, 0},
347: {0140610,"exg", 0, 0, AREG+A, DRG, AREG+D, DRGL, 0},
348: {0140610,"exg", 0, 0, AREG+D, DRGL, AREG+A, DRG, 0},
349:
350: {0044200,"ext", W, SIG, AREG+D, DRG, 0, 0, 0},
351: {0044300,"ext", L, SIG, AREG+D, DRG, 0, 0, 0},
352: {0044700,"extb",L, SIG, AREG+D, DRG, 0, 0, 0},
353:
354: {0047300,"jmp", 0, 0, AGEN+CT,DEA, 0, 0, 0},
355:
356: {0047200,"jsr", 0, 0, AGEN+CT,DEA, 0, 0, 0},
357:
358: {0040700,"lea", L, SIG, AGEN+CT,DEA, AREG+A, DRGL, 0},
359:
360: {0047120,"link",0, 0, AREG+A, DRG, AIMM+H, DIM, 0},
361:
362: {0161700,"lsl", W, SIG, AIMM+O, DIG, AGEN+AM,DEA, ISH},
363: {0160410,"lsl", BWL, SD, AIMM+Q, DAQ, AREG+D, DRG, ISH},
364: {0160450,"lsl", BWL, SD, AREG+D, DRGL, AREG+D, DRG, ISH},
365:
366: {0161300,"lsr", W, SIG, AIMM+O, DIG, AGEN+AM,DEA, ISH},
367: {0160010,"lsr", BWL, SD, AIMM+Q, DAQ, AREG+D, DRG, ISH},
368: {0160050,"lsr", BWL, SD, AREG+D, DRGL, AREG+D, DRG, ISH},
369:
370: {0070000,"mov", L, SIG, AIMM+M, DMQ, AREG+D, DRGL, 0},
371: {0030000,"mov", W, SIG, AGEN, DEA, AGEN+AL+DA,DEAM,0},
372: {0020000,"mov", L, SIG, AGEN, DEA, AGEN+AL+DA,DEAM,0},
373: {0010000,"mov", B, SIG, AGEN, DEA, AGEN+AL+DA,DEAM,0},
374: {0030100,"mov", W, SIG, AGEN, DEA, AREG+A, DRGL, 0},
375: {0020100,"mov", L, SIG, AGEN, DEA, AREG+A, DRGL, ISL},
376: {0040300,"mov", W, SIG, AREG+SR,DIG, AGEN+AL+DA,DEA, 0},
377: {0043300,"mov", W, SIG, AGEN+DA,DEA, AREG+SR,DIG, 0},
378: {0042300,"mov", W, SIG, AGEN+DA,DEA, AREG+C, DIG, 0},
379: {0041300,"mov", W, SIG, AREG+C, DIG, AGEN+AL+DA,DEA, 0},
380: {0047140,"mov", L, SIG, AREG+A, DRG, AREG+U, DIG, 0},
381: {0047150,"mov", L, SIG, AREG+U, DIG, AREG+A, DRG, 0},
382: {0047172,"mov", L, SIG, AREG+CR,DCR, AREG+D, D2H, I2W, 0000000},
383: {0047172,"mov", L, SIG, AREG+CR,DCR, AREG+A, D2H, I2W, 0100000},
384: {0047173,"mov", L, SIG, AREG+D, D2H, AREG+CR,DCR, I2W, 0000000},
385: {0047173,"mov", L, SIG, AREG+A, D2H, AREG+CR,DCR, I2W, 0100000},
386:
387: {0044200,"movm",W, SIG, AIMM+H, DIMH, AGEN+AM,DEA, 0},
388: {0044300,"movm",L, SIG, AIMM+H, DIMH, AGEN+AM,DEA, 0},
389: {0046200,"movm",W, SIG, AGEN+AM,DEA, AIMM+H, DIMH, 0},
390: {0046300,"movm",L, SIG, AGEN+AM,DEA, AIMM+H, DIMH, 0},
391:
392: {0007000,"movs",BWL, SD, AGEN+AM,DEA, AREG+D, D2H, I2W, 0000000},
393: {0007000,"movs",BWL, SD, AGEN+AM,DEA, AREG+A, D2H, I2W, 0100000},
394: {0007000,"movs",BWL, SD, AREG+D, D2H, AGEN+AM,DEA, I2W, 0004000},
395: {0007000,"movs",BWL, SD, AREG+A, D2H, AGEN+AM,DEA, I2W, 0104000},
396:
397: /*
398: * more tricky stuff. D2L and D2H mean low and high register fields of
399: * second instruction word, NOT low and high components of product.
400: * read the manual.
401: */
402: {0140700,"muls",W, SIG, AGEN+DA,DEA, AREG+D, DRGL, 0},
403: {0046000,"muls",L, SIG, AGEN+DA,DEA, AREG+D, D2H, I2W, 0004000},
404: {0046000,"mulsl",L, SIG, AGEN+DA,DEA, AREG+D, D2L, I2W, 0006000, AREG+D, D2H},
405:
406: {0140300,"mulu",W, SIG, AGEN+DA,DEA, AREG+D, DRGL, 0},
407: {0046000,"mulu",L, SIG, AGEN+DA,DEA, AREG+D, D2H, I2W, 0000000},
408: {0046000,"mulul",L, SIG, AGEN+DA,DEA, AREG+D, D2L, I2W, 0002000, AREG+D, D2H},
409:
410: {0044000,"nbcd",B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
411:
412: {0042000,"neg", BWL, SD, AGEN+AL+DA,DEA, 0, 0, 0},
413:
414: {0040000,"negx",BWL, SD, AGEN+AL+DA,DEA, 0, 0, 0},
415:
416: {0047161,"nop", 0, 0, 0, 0, 0, 0, 0},
417:
418: {0043000,"not", BWL, SD, AGEN+AL+DA,DEA, 0, 0, 0},
419:
420: {0000174,"or", W, SIG, AIMM, DIM, AREG+SR,DIG, 0},
421: {0000074,"or", B, SIG, AIMM, DIM, AREG+C, DIG, 0},
422: {0000000,"or", BWL, SD, AIMM, DIM, AGEN+AL+DA,DEA, 0},
423: {0100000,"or", BWL, SD, AGEN+DA,DEA, AREG+D, DRGL, 0},
424: {0100400,"or", BWL, SD, AREG+D, DRGL, AGEN+AM,DEA, 0},
425:
426: {0100500,"pack",0, 0, AREG+D, DRG, AREG+D, DRGL, 0, 0, AIMM+H, DIMH},
427: {0100510,"pack",0, 0, ADEC, DRG, ADEC, DRGL, 0, 0, AIMM+H, DIMH},
428: {0100600,"unpk",0, 0, AREG+D, DRG, AREG+D, DRGL, 0, 0, AIMM+H, DIMH},
429: {0100610,"unpk",0, 0, ADEC, DRG, ADEC, DRGL, 0, 0, AIMM+H, DIMH},
430:
431: {0044100,"swap",W, SIG, AREG+D, DRG, 0, 0, 0},
432: {0044100,"pea", L, SIG, AGEN+CT,DEA, 0, 0, 0},
433:
434: {0047160,"reset",0, 0, 0, 0, 0, 0, 0},
435:
436: {0163700,"rol", W, SIG, AIMM+O, DIG, AGEN+AM,DEA, ISH},
437: {0160430,"rol", BWL, SD, AIMM+Q, DAQ, AREG+D, DRG, ISH},
438: {0160470,"rol", BWL, SD, AREG+D, DRGL, AREG+D, DRG, ISH},
439:
440: {0163300,"ror", W, SIG, AIMM+O, DIG, AGEN+AM,DEA, ISH},
441: {0160030,"ror", BWL, SD, AIMM+Q, DAQ, AREG+D, DRG, ISH},
442: {0160070,"ror", BWL, SD, AREG+D, DRGL, AREG+D, DRG, ISH},
443:
444: {0162700,"roxl",W, SIG, AIMM+O, DIG, AGEN+AM,DEA, ISH},
445: {0160420,"roxl",BWL, SD, AIMM+Q, DAQ, AREG+D, DRG, ISH},
446: {0160460,"roxl",BWL, SD, AREG+D, DRGL, AREG+D, DRG, ISH},
447:
448: {0162300,"roxr",W, SIG, AIMM+O, DIG, AGEN+AM,DEA, ISH},
449: {0160020,"roxr",BWL, SD, AIMM+Q, DAQ, AREG+D, DRG, ISH},
450: {0160060,"roxr",BWL, SD, AREG+D, DRGL, AREG+D, DRG, ISH},
451:
452: {0047163,"rte", 0, 0, 0, 0, 0, 0, 0},
453:
454: {0047167,"rtr", 0, 0, 0, 0, 0, 0, 0},
455:
456: {0047165,"rts", 0, 0, 0, 0, 0, 0, 0},
457:
458: {0100400,"sbcd",B, SIG, AREG+D, DRG, AREG+D, DRGL, 0},
459: {0100410,"sbcd",B, SIG, ADEC, DRG, ADEC, DRGL, 0},
460:
461: {0050300,"st", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
462: {0051300,"shi", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
463: {0052300,"shs", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
464: {0053300,"sne", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
465: {0052300,"scc", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
466: {0054300,"svc", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
467: {0055300,"spl", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
468: {0056300,"sge", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
469: {0057300,"sgt", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
470: {0050700,"sf", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
471: {0051700,"sls", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
472: {0052700,"slo", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
473: {0053700,"seq", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
474: {0052700,"scs", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
475: {0054700,"svs", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
476: {0055700,"smi", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
477: {0056700,"slt", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
478: {0057700,"sle", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
479:
480: {0047162,"stop",0, 0, AIMM+H, DIMH, 0, 0, 0},
481:
482: {0050400,"sub", BWL, SD, AIMM+Q, DAQ, AGEN+AL,DEA, 0},
483: {0002000,"sub", BWL, SD, AIMM, DIM, AGEN+AL+DA,DEA, 0},
484: {0110000,"sub", BWL, SD, AGEN, DEA, AREG+D, DRGL, 0},
485: {0110400,"sub", BWL, SD, AREG+D, DRGL, AGEN+AM,DEA, 0},
486: {0110300,"sub", W, SIG, AGEN, DEA, AREG+A, DRGL, 0},
487: {0110700,"sub", L, SIG, AGEN, DEA, AREG+A, DRGL, ISL},
488:
489: {0110400,"subx",BWL, SD, AREG+D, DRG, AREG+D, DRGL, 0},
490: {0110410,"subx",BWL, SD, ADEC, DRG, ADEC, DRGL, 0},
491:
492: {0045300,"tas", B, SIG, AGEN+AL+DA,DEA, 0, 0, 0},
493:
494: {0047100,"trap",0, 0, AIMM+V, DMQ, 0, 0, 0},
495:
496: {0047166,"trapv",0, 0, 0, 0, 0, 0, 0},
497:
498: {0045000,"tst", BWL, SD, AGEN+AL+DA, DEA, 0, 0, 0},
499:
500: {0047130,"unlk",0, 0, AREG+A, DRG, 0, 0, 0},
501: {0, 0},
502: };
503:
504: char *M68kInstr::mnemonic()
505: {
506: opword0 = _asm->core->peekcode(addr)->sht;
507: opword1 = _asm->core->peekcode(next = addr+2)->sht;
508: for( tab = M68kOpTab; tab->opname; ++tab ){
509: short m = sizemask();
510: m |= OpMask[tab->a1disp&15] | OpMask[tab->a2disp&15];
511: if( (unsigned short)(opword0 & ~m) == tab->opcode ){
512: next += imm_bytes(tab->addr1, tab->a1disp)
513: + imm_bytes(tab->addr2, tab->a2disp);
514: if( tab->iflag == I2W ) next = addr+4;
515: return sf("%s%s", tab->opname, dotbwl());
516: }
517: }
518: return sf("0%o", opword0);
519: }
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