|
|
1.1 root 1: // Argument syntax types
2:
3: #define AREG 1
4: #define AIMM 2
5: #define AEXP 3
6: #define AIREG 4
7: #define AINC 5
8: #define ADEC 6
9: #define AOFF 7
10: #define ANDX 8
11: #define AGEN 9
12: #define APIC 10
13: #define API2 11
14: #define ABIT 12
15:
16: #define AMASK 017
17:
18: // Modifiers to AREG in op table
19:
20: #define A 0100
21: #define D 0200
22: #define C 0400
23: #define SR 01000
24: #define P 02000
25: #define U 04000
26: #define SP 010000
27: #define CR 020000 /* control registers */
28:
29: // Modifiers to AGEN
30:
31: #define AM 0100 /* alterable memory */
32: #define CT 0200 /* Control */
33: #define AL 0400 /* alterable */
34: #define DA 01000 /* data (not address register) */
35: #define BF 02000 /* bit field - no auto anything */
36:
37: // Modifiers to AIMM
38:
39: #define O 0100 /* 1 */
40: #define Q 0200 /* 1 to 8 */
41: #define M 0400 /* -128 to 127 */
42: #define N 01000 /* -8 to -1 */
43: #define V 02000 /* 0 to 15 */
44: #define H 04000 /* -32K to 32K */
45:
46: // Dispositions of address forms
47:
48: #define DIG 0 /* ignore this address */
49: #define DEA 1 /* E.A. to low order 6 bits */
50: #define DRG 2 /* register to low order 3 bits */
51: #define DRGL 3 /* register to bits 11-9 */
52: #define DBR 4 /* branch offset (short) */
53: #define DMQ 5 /* move-quick 8-bit value */
54: #define DAQ 6 /* add-quick 3-bit value in 11-9 */
55: #define DIM 7 /* Immediate value, according to size */
56: #define DEAM 8 /* E.A. to bits 11-6 as in move */
57: #define DBCC 9 /* branch address as in "dbcc" */
58: #define DIMH 10 /* Immediate forced to be 1 word */
59: #define D2L 11 /* register to bits 0-2 of next word */
60: #define D2H 12 /* register to bits 12-14 of next word */
61: #define DBL 13 /* qty in bits 0-5 of next word */
62: #define DBH 14 /* qty in bits 6-11 of next word */
63: #define DCR 15 /* control reg a bit combination in 0-11 */
64:
65: // Size codes
66:
67: #define B 1 /* byte */
68: #define W 2 /* word */
69: #define L 4 /* long */
70: #define WL 6 /* word or long */
71: #define BWL 7 /* any type */
72:
73: // Size dispositions
74:
75: #define SIG 0 /* Ignore the size */
76: #define SD 1 /* Standard coding in bits 7-6 */
77:
78: #define DREGS 0 /* data registers */
79: #define AREGS 8 /* address registers */
80: #define PCREG 16
81: #define SPREG 17
82: #define CCREG 18
83: #define SRREG 19
84: /* unique to 68020 */
85: #define SFCREG 20 /* source function code */
86: #define DFCREG 21 /* destination function code */
87: #define CACRREG 22 /* cache control */
88: #define USPREG 23 /* user sp */
89: #define VBRREG 24 /* vector base */
90: #define CAARREG 25 /* cache address */
91: #define MSPREG 26 /* master sp */
92: #define ISPREG 27 /* interrupt sp */
93:
94: struct m68koptab {
95: unsigned short opcode;
96: char *opname;
97: short size;
98: short sdisp;
99: short addr1;
100: short a1disp;
101: short addr2;
102: short a2disp;
103: short iflag;
104: unsigned short op2code;
105: short addr3;
106: short a3disp;
107: short addr4;
108: short a4disp;
109: };
110:
111: /* special iflags */
112: #define ISL 01 /* shrinkable long immediate */
113: #define ISH 02 /* shift instruction */
114: #define I2W 04 /* two word instruction code */
115:
116: #define SEGRND 0x1L
117:
118: class M68kInstr : public Instr {
119: char *dotbwl();
120: char *ea();
121: char *dbr(char);
122: char *dbh();
123: char *dbl();
124: short sizemask();
125: int imm_bytes(short,short);
126: char *dcr();
127: char mode;
128: char size;
129: long immval;
130: public:
131: short opword0;
132: short opword1;
133: m68koptab *tab;
134: char *arg(int);
135: char *mnemonic();
136: int argtype(int);
137: int nargs();
138: M68kInstr(Asm*, long);
139: };
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.