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1.1 ! root 1: /* @(#)if_qereg.h 1.2 (ULTRIX) 1/3/85 */ ! 2: ! 3: /************************************************************************ ! 4: * * ! 5: * Copyright (c) 1983 by * ! 6: * Digital Equipment Corporation, Maynard, MA * ! 7: * All rights reserved. * ! 8: * * ! 9: * This software is furnished under a license and may be used and * ! 10: * copied only in accordance with the terms of such license and * ! 11: * with the inclusion of the above copyright notice. This * ! 12: * software or any other copies thereof may not be provided or * ! 13: * otherwise made available to any other person. No title to and * ! 14: * ownership of the software is hereby transferred. * ! 15: * * ! 16: * This software is derived from software received from the * ! 17: * University of California, Berkeley, and from Bell * ! 18: * Laboratories. Use, duplication, or disclosure is subject to * ! 19: * restrictions under license agreements with University of * ! 20: * California and with AT&T. * ! 21: * * ! 22: * The information in this software is subject to change without * ! 23: * notice and should not be construed as a commitment by Digital * ! 24: * Equipment Corporation. * ! 25: * * ! 26: * Digital assumes no responsibility for the use or reliability * ! 27: * of its software on equipment which is not supplied by Digital. * ! 28: * * ! 29: ************************************************************************/ ! 30: ! 31: /* ! 32: * Digital Q-BUS to NI Adapter ! 33: */ ! 34: struct qedevice { ! 35: u_short qe_sta_addr[2]; /* Station address (actually 6 */ ! 36: u_short qe_rcvlist_lo; /* Recieve list lo address */ ! 37: u_short qe_rcvlist_hi; /* Recieve list hi address */ ! 38: u_short qe_xmtlist_lo; /* Transmit list lo address */ ! 39: u_short qe_xmtlist_hi; /* Transmit list hi address */ ! 40: u_short qe_vector; /* Interrupt vector */ ! 41: u_short qe_csr; /* Command and Status Register */ ! 42: }; ! 43: ! 44: /* ! 45: * Command and status bits (csr) ! 46: */ ! 47: #define QE_RCV_ENABLE 0x0001 /* Receiver enable */ ! 48: #define QE_RESET 0x0002 /* Software reset */ ! 49: #define QE_NEX_MEM_INT 0x0004 /* Non existant mem interrupt */ ! 50: #define QE_LOAD_ROM 0x0008 /* Load boot/diag from rom */ ! 51: #define QE_XL_INVALID 0x0010 /* Transmit list invalid */ ! 52: #define QE_RL_INVALID 0x0020 /* Receive list invalid */ ! 53: #define QE_INT_ENABLE 0x0040 /* Interrupt enable */ ! 54: #define QE_XMIT_INT 0x0080 /* Transmit interrupt */ ! 55: #define QE_ILOOP 0x0100 /* Internal loopback */ ! 56: #define QE_ELOOP 0x0200 /* External loopback */ ! 57: #define QE_STIM_ENABLE 0x0400 /* Sanity timer enable */ ! 58: #define QE_POWERUP 0x1000 /* Tranceiver power on */ ! 59: #define QE_CARRIER 0x2000 /* Carrier detect */ ! 60: #define QE_RCV_INT 0x8000 /* Receiver interrupt */ ! 61: ! 62: /* ! 63: * Transmit and receive ring discriptor --------------------------- ! 64: * ! 65: * The QNA uses the flag, status1 and the valid bit as a handshake/semiphore ! 66: * mechinism. ! 67: * ! 68: * The flag word is written on ( bits 15,15 set to 1 ) when it reads the ! 69: * descriptor. If the valid bit is set it considers the address to be valid. ! 70: * When it uses the buffer pointed to by the valid address it sets status word ! 71: * one. ! 72: */ ! 73: struct qe_ring { ! 74: u_short qe_flag; /* Buffer utilization flags */ ! 75: u_short qe_addr_hi:6, /* Hi order bits of buffer addr */ ! 76: qe_odd_begin:1, /* Odd byte begin and end (xmit)*/ ! 77: qe_odd_end:1, ! 78: qe_fill1:4, ! 79: qe_setup:1, /* Setup packet */ ! 80: qe_eomsg:1, /* End of message flag */ ! 81: qe_chain:1, /* Chain address instead of buf */ ! 82: qe_valid:1; /* Address field is valid */ ! 83: u_short qe_addr_lo; /* Low order bits of address */ ! 84: short qe_buf_len; /* Negative buffer length */ ! 85: u_short qe_status1; /* Status word one */ ! 86: u_short qe_status2; /* Status word two */ ! 87: }; ! 88: ! 89: /* ! 90: * Status word definations (receive) ! 91: * word1 ! 92: */ ! 93: #define QE_OVF 0x0001 /* Receiver overflow */ ! 94: #define QE_CRCERR 0x0002 /* CRC error */ ! 95: #define QE_FRAME 0x0004 /* Framing alignment error */ ! 96: #define QE_SHORT 0x0008 /* Packet size < 10 bytes */ ! 97: #define QE_RBL_HI 0x0700 /* Hi bits of receive len */ ! 98: #define QE_RUNT 0x0800 /* Runt packet */ ! 99: #define QE_DISCARD 0x1000 /* Discard the packet */ ! 100: #define QE_ESETUP 0x2000 /* Looped back setup or eloop */ ! 101: #define QE_ERROR 0x4000 /* Receiver error */ ! 102: #define QE_LASTNOT 0x8000 /* Not the last in the packet */ ! 103: /* word2 */ ! 104: #define QE_RBL_LO 0x00ff /* Low bits of receive len */ ! 105: ! 106: /* ! 107: * Status word definations (transmit) ! 108: * word1 ! 109: */ ! 110: #define QE_CCNT 0x00f0 /* Collision count this packet */ ! 111: #define QE_FAIL 0x0100 /* Heart beat check failure */ ! 112: #define QE_ABORT 0x0200 /* Transmission abort */ ! 113: #define QE_STE16 0x0400 /* Sanity timer default on */ ! 114: #define QE_NOCAR 0x0800 /* No carrier */ ! 115: #define QE_LOSS 0x1000 /* Loss of carrier while xmit */ ! 116: /* word2 */ ! 117: #define QE_TDR 0x3fff /* Time domain reflectometry */ ! 118: ! 119: /* ! 120: * General constant definations ! 121: */ ! 122: #define QEALLOC 0 /* Allocate an mbuf */ ! 123: #define QENOALLOC 1 /* No mbuf allocation */ ! 124: #define QEDEALLOC 2 /* Release an mbuf chain */ ! 125: ! 126: #define QE_NOTYET 0x8000 /* Descriptor not in use yet */ ! 127: #define QE_INUSE 0x4000 /* Descriptor being used by QNA */ ! 128: #define QE_MASK 0xc000 /* Lastnot/error/used mask */
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