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Annotation of researchv9/sys.vax/h/mem.h, revision 1.1.1.1

1.1       root        1: /*
                      2:  * Memory controller registers
                      3:  *
                      4:  * The way in which the data is stored in these registers varies
                      5:  * per cpu, so we define macros here to mask that.
                      6:  */
                      7: struct mcr {
                      8:        int     mc_reg[3];
                      9: };
                     10: 
                     11: /*
                     12:  * Compute maximum possible number of memory controllers,
                     13:  * for sizing of the mcraddr array.
                     14:  */
                     15: #if VAX780
                     16: #define        MAXNMCR         4
                     17: #else
                     18: #define        MAXNMCR         1
                     19: #endif
                     20: 
                     21: /*
                     22:  * For each processor type we define 5 macros:
                     23:  *     M???_INH(mcr)           inhibits further crd interrupts from mcr
                     24:  *     M???_ENA(mcr)           enables another crd interrupt from mcr
                     25:  *     M???_ERR(mcr)           tells whether an error is waiting
                     26:  *     M???_SYN(mcr)           gives the syndrome bits of the error
                     27:  *     M???_ADDR(mcr)          gives the address of the error
                     28:  */
                     29: #if VAX780
                     30: #define        M780_ICRD       0x40000000      /* inhibit crd interrupts, in [2] */
                     31: #define        M780_HIER       0x20000000      /* high error rate, in reg[2] */
                     32: #define        M780_ERLOG      0x10000000      /* error log request, in reg[2] */
                     33: /* on a 780, memory crd's occur only when bit 15 is set in the SBIER */
                     34: /* register; bit 14 there is an error bit which we also clear */
                     35: /* these bits are in the back of the ``red book'' (or in the VMS code) */
                     36: 
                     37: #define        M780_INH(mcr)   \
                     38:        (((mcr)->mc_reg[2] = (M780_ICRD|M780_HIER|M780_ERLOG)), mtpr(SBIER, 0))
                     39: #define        M780_ENA(mcr)   \
                     40:        (((mcr)->mc_reg[2] = (M780_HIER|M780_ERLOG)), mtpr(SBIER, 3<<14))
                     41: #define        M780_ERR(mcr)   \
                     42:        ((mcr)->mc_reg[2] & (M780_ERLOG))
                     43: 
                     44: #define        M780_SYN(mcr)   ((mcr)->mc_reg[2] & 0xff)
                     45: #define        M780_ADDR(mcr)  (((mcr)->mc_reg[2] >> 8) & 0xfffff)
                     46: #endif
                     47: 
                     48: #if VAX750
                     49: #define        M750_ICRD       0x10000000      /* enable [sic] crd interrupts, in [1] */
                     50: #define        M750_UNCORR     0xc0000000      /* uncorrectable error, in [0] */
                     51: #define        M750_CORERR     0x20000000      /* correctable error, in [0] */
                     52: 
                     53: #define        M750_INH(mcr)   ((mcr)->mc_reg[1] = 0)
                     54: #define        M750_ENA(mcr)   ((mcr)->mc_reg[0] = (M750_UNCORR|M750_CORERR), \
                     55:                            (mcr)->mc_reg[1] = M750_ICRD)
                     56: #define        M750_ERR(mcr)   ((mcr)->mc_reg[0] & (M750_UNCORR|M750_CORERR))
                     57: 
                     58: #define        M750_SYN(mcr)   ((mcr)->mc_reg[0] & 0x7f)
                     59: #define        M750_ADDR(mcr)  (((mcr)->mc_reg[0] >> 9) & 0x7fff)
                     60: #endif
                     61: 
                     62: #if VAX7ZZ
                     63: #define        M7ZZ_CRD        0x40000000      /* crd, in [1] */
                     64: #define        M7ZZ_FTBPE      0x20000000      /* force tbuf parity error, in [1] */
                     65: #define        M7ZZ_ENACRD     0x10000000      /* enable crd interrupt, in [1] */
                     66: #define        M7ZZ_MME        0x08000000      /* mem-man enable (ala ipr), in [1] */
                     67: #define        M7ZZ_DM         0x04000000      /* diagnostic mode, in [1] */
                     68: #define        M7ZZ_DISECC     0x02000000      /* disable ecc, in [1] */
                     69: 
                     70: #define        M7ZZ_INH(mcr)   ((mcr)->mc_reg[1] = M7ZZ_MME)
                     71: #define        M7ZZ_ENA(mcr)   ((mcr)->mc_reg[1] = (M7ZZ_MME|M7ZZ_ENACRD))
                     72: #define        M7ZZ_ERR(mcr)   ((mcr)->mc_reg[1] & M7ZZ_CRD)
                     73: #define        M7ZZ_SYN(mcr)   ((mcr)->mc_reg[0] & 0x7f)
                     74: #define        M7ZZ_ADDR(mcr)  (((mcr)->mc_reg[0] >> 8) & 0x7fff)
                     75: #endif
                     76: 
                     77: #define        MEMINTVL        (60*60*30)              /* 30 minutes */
                     78: 
                     79: #ifdef KERNEL
                     80: int    nmcr;
                     81: struct mcr *mcraddr[MAXNMCR];
                     82: #endif

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