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Annotation of researchv9/sys.vax/h/mtpr.h, revision 1.1.1.1

1.1       root        1: /*
                      2:  * VAX processor register numbers
                      3:  */
                      4: 
                      5: #define        KSP     0x0             /* kernel stack pointer */
                      6: #define        ESP     0x1             /* exec stack pointer */
                      7: #define        SSP     0x2             /* supervisor stack pointer */
                      8: #define        USP     0x3             /* user stack pointer */
                      9: #define        ISP     0x4             /* interrupt stack pointer */
                     10: #define        P0BR    0x8             /* p0 base register */
                     11: #define        P0LR    0x9             /* p0 length register */
                     12: #define        P1BR    0xa             /* p1 base register */
                     13: #define        P1LR    0xb             /* p1 length register */
                     14: #define        SBR     0xc             /* system segment base register */
                     15: #define        SLR     0xd             /* system segment length register */
                     16: #define        PCBB    0x10            /* process control block base */
                     17: #define        SCBB    0x11            /* system control block base */
                     18: #define        IPL     0x12            /* interrupt priority level */
                     19: #define        ASTLVL  0x13            /* async. system trap level */
                     20: #define        SIRR    0x14            /* software interrupt request */
                     21: #define        SISR    0x15            /* software interrupt summary */
                     22: #define        ICCS    0x18            /* interval clock control */
                     23: #define        NICR    0x19            /* next interval count */
                     24: #define        ICR     0x1a            /* interval count */
                     25: #define        TODR    0x1b            /* time of year (day) */
                     26: #define        RXCS    0x20            /* console receiver control and status */
                     27: #define        RXDB    0x21            /* console receiver data buffer */
                     28: #define        TXCS    0x22            /* console transmitter control and status */
                     29: #define        TXDB    0x23            /* console transmitter data buffer */
                     30: #define        MAPEN   0x38            /* memory management enable */
                     31: #define        TBIA    0x39            /* translation buffer invalidate all */
                     32: #define        TBIS    0x3a            /* translation buffer invalidate single */
                     33: #define        PMR     0x3d            /* performance monitor enable */
                     34: #define        CPUSID  0x3e            /* system identification */
                     35: 
                     36: #if VAX780
                     37: #define        ACCS    0x28            /* accelerator control and status */
                     38: #define        ACCR    0x29            /* accelerator maintenance */
                     39: #define        WCSA    0x2c            /* WCS address */
                     40: #define        WCSD    0x2d            /* WCS data */
                     41: #define        SBIFS   0x30            /* SBI fault and status */
                     42: #define        SBIS    0x31            /* SBI silo */
                     43: #define        SBISC   0x32            /* SBI silo comparator */
                     44: #define        SBIMT   0x33            /* SBI maintenance */
                     45: #define        SBIER   0x34            /* SBI error register */
                     46: #define        SBITA   0x35            /* SBI timeout address */
                     47: #define        SBIQC   0x36            /* SBI quadword clear */
                     48: #define        MBRK    0x3c            /* micro-program breakpoint */
                     49: #endif
                     50: 
                     51: #if defined(VAX750) || defined(MVAX)
                     52: #define        MCSR    0x17            /* machine check status register */
                     53: #define        CSRS    0x1c            /* console storage receive status register */
                     54: #define        CSRD    0x1d            /* console storage receive data register */
                     55: #define        CSTS    0x1e            /* console storage transmit status register */
                     56: #define        CSTD    0x1f            /* console storage transmit data register */
                     57: #define        TBDR    0x24            /* translation buffer disable register */
                     58: #define        CADR    0x25            /* cache disable register */
                     59: #define        MCESR   0x26            /* machine check error summary register */
                     60: #define        CAER    0x27            /* cache error */
                     61: #define        IUR     0x37            /* init unibus register */
                     62: #define        TB      0x3b            /* translation buffer */
                     63: #endif

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