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1.1 root 1: /*
2: * UDA-50 registers and structures
3: */
4:
5: struct udadevice {
6: short udaip; /* initialization and polling */
7: short udasa; /* status and address */
8: };
9:
10: #define UDA_ERR 0100000 /* error bit */
11: #define UDA_STEP4 0040000 /* step 4 has started */
12: #define UDA_STEP3 0020000 /* step 3 has started */
13: #define UDA_STEP2 0010000 /* step 2 has started */
14: #define UDA_STEP1 0004000 /* step 1 has started */
15: #define UDA_NV 0002000 /* no host settable interrupt vector */
16: #define UDA_QB 0001000 /* controller supports Q22 bus */
17: #define UDA_DI 0000400 /* controller implements diagnostics */
18: #define UDA_IE 0000200 /* interrupt enable */
19: #define UDA_PI 0000001 /* host requests adapter purge interrupts */
20: #define UDA_LF 0000002 /* host requests last fail packet */
21: #define UDA_GO 0000001 /* start operation, after init */
22:
23: /*
24: * UDA Communications Area
25: */
26:
27: struct udaca {
28: short ca_xxx1; /* unused */
29: char ca_xxx2; /* unused */
30: char ca_bdp; /* BDP to purge */
31: short ca_cmdint; /* command queue transition interrupt flag */
32: short ca_rspint; /* response queue transition interrupt flag */
33: long ca_rspdsc[NRSP];/* response descriptors */
34: long ca_cmddsc[NCMD];/* command descriptors */
35: };
36:
37: #define ca_ringbase ca_rspdsc[0]
38:
39: #define UDA_OWN 0x80000000 /* UDA owns this descriptor */
40: #define UDA_INT 0x40000000 /* allow interrupt on ring transition */
41:
42: /*
43: * MSCP packet info (message envelope)
44: */
45: struct mscp_header {
46: short uda_msglen; /* length of MSCP packet */
47: char uda_credits; /* low 4 bits: credits, high 4 bits: msgtype */
48: /* msgtypes: 0-seq, 1-datagra, 2-credits */
49: char uda_vcid; /* virtual circuit id */
50: };
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