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Annotation of researchv9/sys/sun3/memerr.h, revision 1.1.1.1

1.1       root        1: /*      @(#)memerr.h 1.1 86/02/03 SMI      */
                      2: 
                      3: /*
                      4:  * Copyright (c) 1985 by Sun Microsystems, Inc.
                      5:  */
                      6: 
                      7: /*
                      8:  * All Sun-3 implementations have either memory parity error detection
                      9:  * or memory equipped with error correction (ECC). The memory error
                     10:  * register consists of a control and an address register.  If an error
                     11:  * occurs, the control register stores information relevant to the error.
                     12:  * The memory address error register stores the virtual address, the
                     13:  * context number, and the CPU/DVMA bit of the memory cycle at which
                     14:  * the error was detected.  Errors are reported via a non-maskable
                     15:  * level 7 interrupt.  In case of multiple (stacked) memory errors,
                     16:  * the information relation to the first error is latched in the
                     17:  * memory error register.  The interrupt is held pending and the error
                     18:  * information in the memory error register is latched (frozen) until
                     19:  * it is cleared (unfrozen) by a write to bits <31..24> of the memory
                     20:  * error address register.
                     21:  */
                     22: 
                     23: #define        OBIO_MEMREG 0x80000     /* address of memreg in obio space */
                     24: 
                     25: #ifdef LOCORE
                     26: #define        MEMREG 0x0FFE4000       /* virtual address we map memreg to be at */
                     27: #else
                     28: struct memreg {
                     29:        u_char  mr_er;          /* memory error control register */
                     30: #define        mr_per  mr_er           /* parity error register */
                     31: #define        mr_eer  mr_er           /* ECC error register */
                     32:        u_char  mr_undef[3];
                     33:        u_int   mr_dvma : 1;
                     34:        u_int   mr_ctx  : 3;
                     35:        u_int   mr_vaddr:28;
                     36: };
                     37: #define        MEMREG ((struct memreg *)(0x0FFE4000))
                     38: #endif LOCORE
                     39: 
                     40: /*
                     41:  *  Bits for the memory error register when used as parity error register
                     42:  */
                     43: #define PER_INTR       0x80    /* r/o - 1 = parity interrupt pending */
                     44: #define PER_INTENA     0x40    /* r/w - 1 = enable interrupt on parity error */
                     45: #define PER_TEST       0x20    /* r/w - 1 = write inverse parity */
                     46: #define PER_CHECK      0x10    /* r/w - 1 = enable parity checking */
                     47: #define PER_ERR24      0x08    /* r/o - 1 = parity error <24..31> */
                     48: #define PER_ERR16      0x04    /* r/o - 1 = parity error <16..23> */
                     49: #define PER_ERR08      0x02    /* r/o - 1 = parity error <8..15> */
                     50: #define PER_ERR00      0x01    /* r/o - 1 = parity error <0..7> */
                     51: #define        PER_ERR         0x0F    /* r/o - mask for some parity error occuring */
                     52: #define PARERR_BITS    "\20\10INTR\7INTENA\6TEST\5CHECK\4ERR24\3ERR16\2ERR08\1ERR00"
                     53: 
                     54: /*
                     55:  *  Bits for the memory error register when used as ECC error register
                     56:  */
                     57: #define EER_INTR       0x80    /* r/o - ECC memory interrupt pending */
                     58: #define EER_INTENA     0x40    /* r/w - enable interrupts on errors */
                     59: #define EER_BUSHOLD    0x20    /* r/w - hold memory bus mastership */
                     60: #define EER_CE_ENA     0x10    /* r/w - enable CE recording */
                     61: #define        EER_TIMEOUT     0x08    /* r/o - Sirius bus time out */
                     62: #define        EER_WBACKERR    0x04    /* r/o - write back error */
                     63: #define EER_UE         0x02    /* r/o - UE, uncorrectable error  */
                     64: #define EER_CE         0x01    /* r/o - CE, correctable (single bit) error */
                     65: #define        EER_ERR         0x0F    /* r/o - mask for some ECC error occuring */
                     66: #define ECCERR_BITS    "\20\10INTR\7INTENA\6BUSHOLD\5CE_ENA\4TIMEOUT\3WBACKERR\2UE\1CE"
                     67: 
                     68: 
                     69: #define        ER_INTR         0x80    /* mask for ECC/parity interrupt pending */
                     70: #define        ER_INTENA       0x40    /* mask for ECC/parity enable interrupt */

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