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Annotation of researchv9/sys/sun3/zsreg.h, revision 1.1

1.1     ! root        1: /*     @(#)zsreg.h 1.1 86/02/03 SMI    */
        !             2: 
        !             3: /*
        !             4:  * Copyright (c) 1983 by Sun Microsystems, Inc.
        !             5:  */
        !             6: 
        !             7: /*
        !             8:  * Zilog 8530 SCC Serial Communications Controller
        !             9:  *
        !            10:  * This is a dual uart chip with on-chip baud rate generators.
        !            11:  * It is about as brain-damaged as the typical modern uart chip,
        !            12:  * but it does have a lot of features as well as the usual lot of
        !            13:  * brain damage around addressing, write-onlyness, etc.
        !            14:  */
        !            15: 
        !            16: /*
        !            17:  * Uart registers:
        !            18:  *
        !            19:  * There are 16 write registers and 9 read registers in each channel.
        !            20:  * As usual, the two channels are ALMOST orthogonal, not exactly.  Most regs
        !            21:  * can only be written to, or read, but not both.  To access one, you must
        !            22:  * first write to register 0 with the number of the register you
        !            23:  * are interested in, then read/write the actual value, and hope that
        !            24:  * nobody interrupts you in between.
        !            25:  *
        !            26:  * Note that the register&bit assignment is suspiciously like the Intel 8274.
        !            27:  * Do you think they read each others' data sheets?  Can they decode them?
        !            28:  */
        !            29: 
        !            30: /* bits in RR0 */
        !            31: #define        ZSRR0_RX_READY          0x01    /* received character available */
        !            32: #define ZSRR0_TIMER            0x02    /* if R15_TIMER, timer reached 0 */
        !            33: #define        ZSRR0_TX_READY          0x04    /* transmit buffer empty */
        !            34: #define        ZSRR0_CD                0x08    /* CD input (latched if R15_CD) */
        !            35: #define ZSRR0_SYNC             0x10    /* SYNC input (latched if R15_SYNC) */
        !            36: #define        ZSRR0_CTS               0x20    /* CTS input (latched if R15_CTS) */
        !            37: #define ZSRR0_TXUNDER          0x40    /* (SYNC) Xmitter underran */
        !            38: #define        ZSRR0_BREAK             0x80    /* received break detected */
        !            39: 
        !            40: /* bits in RR1 */
        !            41: #define        ZSRR1_ALL_SENT          0x01    /* all chars fully transmitted */
        !            42: #define        ZSRR1_PE                0x10    /* parity error (latched, must reset) */
        !            43: #define        ZSRR1_DO                0x20    /* data overrun (latched, must reset) */
        !            44: #define        ZSRR1_FE                0x40    /* framing/CRC error (not latched) */
        !            45: #define        ZSRR1_RXEOF             0x80    /* end of recv sdlc frame */
        !            46: 
        !            47: /* bits in R/WR2 -- interrupt vector number. */
        !            48: /* NOTE that RR2 in channel A is unmodified, while in channel B it is
        !            49:    modified by the current status of the UARTs.  (This is independent
        !            50:    of the setting of WR9_VIS.)  If no interrupts are pending, the modified
        !            51:    status is Channel B Special Receive.  It can be written from
        !            52:    either channel. */
        !            53: 
        !            54: /* bits in RR3 -- Interrupt Pending flags for both channels (this reg can
        !            55:    only be read in Channel A, tho.  Thanks guys.) */
        !            56: #define ZSRR3_IP_B_STAT                0x01    /* Ext/status int pending, chan B */
        !            57: #define ZSRR3_IP_B_TX          0x02    /* Transmit int pending, chan B */
        !            58: #define ZSRR3_IP_B_RX          0x04    /* Receive int pending, chan B */
        !            59: #define ZSRR3_IP_A_STAT                0x08    /* Ditto for channel A */
        !            60: #define ZSRR3_IP_A_TX          0x10
        !            61: #define ZSRR3_IP_A_RX          0x20
        !            62: 
        !            63: /* bits in RR8 -- this is the same as reading the Data port */
        !            64: 
        !            65: /* bits in RR10 -- DPLL and SDLC Loop Mode status -- not entered*/
        !            66: 
        !            67: /* bits in R/WR12 -- lower byte of time constant for baud rate generator */
        !            68: /*
        !            69:  * The following macro can be used to generate the baud rate generator's
        !            70:  * time constants.  The parameters are the input clock to the BRG (eg,
        !            71:  * 5000000 for 5MHz) and the desired baud rate.  This macro assumes that
        !            72:  * the clock needed is 16x the desired baud rate.
        !            73:  */
        !            74: #define ZSTimeConst(InputClock, BaudRate) (( InputClock / (2*BaudRate*16)) - 2)
        !            75: 
        !            76: /* bits in R/WR13 -- upper byte of time constant for baud rate generator */
        !            77: 
        !            78: /* bits in R/WR15 -- interrupt enables for status conditions */
        !            79: #define ZSR15_TIMER            0x02    /* ie if baud rate generator = 0 */
        !            80: #define ZSR15_CD               0x08    /* ie transition on CD (car. det.) */
        !            81: #define ZSR15_SYNC             0x10    /* ie transition on SYNC (gen purp) */
        !            82: #define ZSR15_CTS              0x20    /* ie transition on CTS (clr to send) */
        !            83: #define ZSR15_TX_UNDER         0x40    /* (SYNC) ie transmit underrun */
        !            84: #define ZSR15_BREAK            0x80    /* ie on start, and end, of break */
        !            85: 
        !            86: /* Write register 0 -- common commands and Register Pointers */
        !            87: #define ZSWR0_REG              0x0F    /* mask: next reg to read/write */
        !            88: #define        ZSWR0_RESET_STATUS      0x10    /* reset status bit latches */
        !            89: #define ZSWR0_FIRST_RX         0x20    /* in WR1_RX_FIRST_IE, enab next int */
        !            90: #define        ZSWR0_RESET_TXINT       0x28    /* reset transmitter interrupt */
        !            91: #define        ZSWR0_RESET_ERRORS      0x30    /* reset read character errors */
        !            92: #define        ZSWR0_CLR_INTR          0x38    /* Reset Interrupt In Service */
        !            93: #define ZSWR0_RESET_RXCRC       0x40    /*  Reset Rx CRC generator.     */
        !            94: #define ZSWR0_RESET_TXCRC       0x80    /*  Reset Tx CRC generator.     */
        !            95: #define ZSWR0_RESET_EOM         0xC0    /*  Reset Tx underrun / EOM.    */
        !            96: 
        !            97: /* bits in WR1 */
        !            98: #define        ZSWR1_SIE               0x01    /* status change master int enable */
        !            99:                                        /* Also see R15 for individual enabs */
        !           100: #define        ZSWR1_TIE               0x02    /* transmitter interrupt enable */
        !           101: #define        ZSWR1_PARITY_SPECIAL    0x04    /* parity err causes special rx int */
        !           102: #define ZSWR1_RX_FIRST_IE      0x08    /* r.i.e. on 1st char of msg */
        !           103: #define        ZSWR1_RIE               0x10    /* receiver interrupt enable */
        !           104: /* There are other Receive interrupt options defined, see data sheet. */
        !           105: 
        !           106: /* bits in WR2 are defined above as R/WR2. */
        !           107: 
        !           108: /* bits in WR3 */
        !           109: #define        ZSWR3_RX_ENABLE         0x01    /* receiver enable */
        !           110: #define        ZSWR3_RXCRC_ENABLE      0x08    /* receiver CRC enable */
        !           111: #define        ZSWR3_HUNT              0x10    /* enter hunt mode */
        !           112: #define        ZSWR3_AUTO_CD_CTS       0x20    /* auto-enable CD&CTS rcv&xmit ctl */
        !           113: #define ZSWR3_RX_5             0x00    /* receive 5-bit characters */
        !           114: #define        ZSWR3_RX_6              0x80    /* receive 6 bit characters */
        !           115: #define        ZSWR3_RX_7              0x40    /* receive 7 bit characters */
        !           116: #define        ZSWR3_RX_8              0xC0    /* receive 8 bit characters */
        !           117: 
        !           118: /* bits in WR4 */
        !           119: #define        ZSWR4_PARITY_ENABLE     0x01    /* Gen/check parity bit */
        !           120: #define        ZSWR4_PARITY_EVEN       0x02    /* Gen/check even parity */
        !           121: #define        ZSWR4_1_STOP            0x04    /* 1 stop bit */
        !           122: #define        ZSWR4_1_5_STOP          0x08    /* 1.5 stop bits */
        !           123: #define        ZSWR4_2_STOP            0x0C    /* 2 stop bits */
        !           124: #define        ZSWR4_SDLC              0x20    /* SDLC mode */
        !           125: #define ZSWR4_X1_CLK           0x00    /* clock is 1x */
        !           126: #define        ZSWR4_X16_CLK           0x40    /* clock is 16x */
        !           127: #define ZSWR4_X32_CLK          0x80    /* clock is 32x */
        !           128: #define ZSWR4_X64_CLK          0xC0    /* clock is 64x */
        !           129: 
        !           130: /* bits in WR5 */
        !           131: #define        ZSWR5_TXCRC_ENABLE      0x01    /* transmitter CRC enable */
        !           132: #define        ZSWR5_RTS               0x02    /* RTS output */
        !           133: #define        ZSWR5_TX_ENABLE         0x08    /* transmitter enable */
        !           134: #define        ZSWR5_BREAK             0x10    /* send break continuously */
        !           135: #define        ZSWR5_TX_5              0x00    /* transmit 5 bit chars or less */
        !           136: #define        ZSWR5_TX_6              0x40    /* transmit 6 bit characters */
        !           137: #define        ZSWR5_TX_7              0x20    /* transmit 7 bit characters */
        !           138: #define        ZSWR5_TX_8              0x60    /* transmit 8 bit characters */
        !           139: #define        ZSWR5_DTR               0x80    /* DTR output */
        !           140: 
        !           141: /* bits in WR6 -- Sync characters or SDLC address field. */
        !           142: 
        !           143: /* bits in WR7 -- Sync character or SDLC flag */
        !           144: 
        !           145: /* bits in WR8 -- transmit buffer.  Same as writing to data port. */
        !           146: 
        !           147: /* bits in WR9 -- Master interrupt control and reset.  Accessible thru
        !           148:    either channel, there's only one of them. */
        !           149: #define ZSWR9_VECTOR_INCL_STAT 0x01    /* Include status bits in int vector */
        !           150: #define ZSWR9_NO_VECTOR                0x02    /* Do not respond to int ack cycles */
        !           151: #define ZSWR9_DIS_LOWER_CHAIN  0x04    /* Disable ints lower in daisy chain */
        !           152: #define ZSWR9_MASTER_IE                0x08    /* Master interrupt enable */
        !           153: #define ZSWR9_STAT_HIGH                0x10    /* Modify ivec bits 6-4, not 1-3 */
        !           154: #define ZSWR9_RESET_CHAN_B     0x40    /* Reset just channel B */
        !           155: #define ZSWR9_RESET_CHAN_A     0x80    /* Reset just channel A */
        !           156: #define ZSWR9_RESET_WORLD      0xC0    /* Force hardware reset */
        !           157: 
        !           158: /* bits in WR10 -- SDLC, NRZI, FM control bits */
        !           159: #define        ZSWR10_UNDERRUN_ABORT   0x04    /* send abort on TX underrun */
        !           160: #define        ZSWR10_PRESET_ONES      0x80    /* preset CRC to ones (SDLC) */
        !           161: 
        !           162: /* bits in WR11 -- clock mode control */
        !           163: #define ZSWR11_TRXC_XTAL       0x00    /* TRxC output = xtal osc */
        !           164: #define ZSWR11_TRXC_XMIT       0x01    /* TRxC output = xmitter clk */
        !           165: #define ZSWR11_TRXC_BAUD       0x02    /* TRxC output = baud rate gen */
        !           166: #define ZSWR11_TRXC_DPLL       0x03    /* TRxC output = Phase Locked Loop */
        !           167: #define ZSWR11_TRXC_OUT_ENA    0x04    /* TRxC output enable (unless input) */
        !           168: #define ZSWR11_TXCLK_RTXC      0x00    /* Tx clock is RTxC pin */
        !           169: #define ZSWR11_TXCLK_TRXC      0x08    /* Tx clock is TRxC pin */
        !           170: #define ZSWR11_TXCLK_BAUD      0x10    /* Tx clock is baud rate gen output */
        !           171: #define ZSWR11_TXCLK_DPLL      0x18    /* Tx clock is Phase Locked Loop o/p */
        !           172: #define ZSWR11_RXCLK_RTXC      0x00    /* Rx clock is RTxC pin */
        !           173: #define ZSWR11_RXCLK_TRXC      0x20    /* Rx clock is TRxC pin */
        !           174: #define ZSWR11_RXCLK_BAUD      0x40    /* Rx clock is baud rate gen output */
        !           175: #define ZSWR11_RXCLK_DPLL      0x60    /* Rx clock is Phase Locked Loop o/p */
        !           176: #define ZSWR11_RTXC_XTAL       0x80    /* RTxC uses crystal, not TTL signal */
        !           177: 
        !           178: /* bits in WR12 -- described above as R/WR12 */
        !           179: 
        !           180: /* bits in WR13 -- described above as R/WR13 */
        !           181: 
        !           182: /* bits in WR14 -- misc control bits, and DPLL control */
        !           183: #define ZSWR14_BAUD_ENA                0x01    /* enables baud rate counter */
        !           184: #define ZSWR14_BAUD_FROM_PCLK  0x02    /* Baud rate gen src = PCLK not RTxC */
        !           185: #define ZSWR14_DTR_IS_REQUEST  0x04    /* Changes DTR line to DMA Request */
        !           186: #define ZSWR14_AUTO_ECHO       0x08    /* Echoes RXD to TXD */
        !           187: #define ZSWR14_LOCAL_LOOPBACK  0x10    /* Echoes TX to RX in chip */
        !           188: #define ZSWR14_DPLL_NOP                0x00    /* These 8 commands are mut. exclu. */
        !           189: #define ZSWR14_DPLL_SEARCH     0x20    /* Enter search mode in DPLL */
        !           190: #define ZSWR14_DPLL_RESET      0x40    /* Reset missing clock in DPLL */
        !           191: #define ZSWR14_DPLL_DISABLE    0x60    /* Disable DPLL */
        !           192: #define ZSWR14_DPLL_SRC_BAUD   0x80    /* Source for DPLL is baud rate gen */
        !           193: #define ZSWR14_DPLL_SRC_RTXC   0xA0    /* Source for DPLL is RTxC pin */
        !           194: #define ZSWR14_DPLL_FM         0xC0    /* DPLL should run in FM mode */
        !           195: #define ZSWR14_DPLL_NRZI       0xE0    /* DPLL should run in NRZI mode */
        !           196: 
        !           197: /* bits in WR15 -- described above as R/WR15 */
        !           198: 
        !           199: /*
        !           200:  * UART register addressing
        !           201:  *
        !           202:  * It would be nice if they used 4 address pins to address 15 registers,
        !           203:  * but they only used 1.  So you have to write to the control port then
        !           204:  * read or write it; the 2nd cycle is done to whatever register number
        !           205:  * you wrote in the first cycle.
        !           206:  *
        !           207:  * The data register can also be accessed as Read/Write register 8.
        !           208:  */
        !           209: #ifndef LOCORE
        !           210: struct zscc_device {
        !           211:        unsigned char   zscc_control;
        !           212:        unsigned char   :8;             /* Filler */
        !           213:        unsigned char   zscc_data;
        !           214:        unsigned char   :8;             /* Filler */
        !           215: };
        !           216: #endif

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