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Annotation of researchv9/sys/sundev/lereg.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * Copyright (c) 1985 by Sun Microsystems, Inc.
        !             3:  */
        !             4: 
        !             5: /*
        !             6:  * AMD 7990 LANCE Ethernet controller registers.
        !             7:  *
        !             8:  * The LANCE chip saves address pins by accessing
        !             9:  * several registers with one address pin by first writing the
        !            10:  * register address to an internal address register, then reading
        !            11:  * or writing a data register.  To use this safely, care must be
        !            12:  * taken that the driver isn't reentered between the writing
        !            13:  * of the address register and the access to the data register,
        !            14:  * lest the reentered code try to touch the registers and
        !            15:  * screw up the sequence.
        !            16:  *
        !            17:  * There are 4 registers accessible with this scheme, CSR0, CSR1,
        !            18:  * CSR2, and CSR3.  In normal operation, only CSR0 can be or
        !            19:  * needs to be accessed, so the driver normally leaves a 0 in the
        !            20:  * Register Address Port, allowing CSR0 to be accessed simply by
        !            21:  * accessing the Register Data Port.  During the initialization
        !            22:  * sequence, when the other CSRs need to be accessed, the appropriate
        !            23:  * CSR address is written into the address port, and afterwards
        !            24:  * the 0 is put back in the address port.
        !            25:  */
        !            26: 
        !            27: 
        !            28: /*
        !            29:  * Buffer size is chosen to give room for:
        !            30:  *  -  the Ethernet maximum transmission unit,         1536
        !            31:  *  -  the CRC,                                           4
        !            32:  *  -  and an overrun consisting of the entire
        !            33:  *     fifo contents,                                    48
        !            34:  */
        !            35: #define MAXBUF 1588
        !            36: 
        !            37: struct le_device {
        !            38:        u_short le_rdp;                 /* Register Data Port */
        !            39:        u_short         : 14;           /* Reserved */
        !            40:        u_short le_rap  : 2;            /* Register Address Port */
        !            41: };
        !            42: #define le_csr le_rdp
        !            43: 
        !            44: #define        LE_CSR0         0
        !            45: #define        LE_CSR1         1
        !            46: #define        LE_CSR2         2
        !            47: #define        LE_CSR3         3
        !            48: 
        !            49: /*
        !            50:  * Control and status bits for CSR0.
        !            51:  * These behave somewhat strangely, but the net effect is that
        !            52:  * bit masks may be written to the register which affect only
        !            53:  * those functions for which there is a one bit in the mask.
        !            54:  * The exception is the interrupt enable, which must be explicitly
        !            55:  * set to the correct value in each mask that is used.
        !            56:  *
        !            57:  * RO - Read Only, writing has no effect
        !            58:  * RC - Read, Clear.  Writing 1 clears, writing 0 has no effect
        !            59:  * RW - Read, Write.
        !            60:  * W1 - Write with 1 only.  Writing 1 sets, writing 0 has no effect.
        !            61:  *        Reading gives unpredictable data but doesn't hurt anything.
        !            62:  * RW1 - Read, Write with 1 only.  Writing 1 sets, writing 0 has no effect.
        !            63:  */
        !            64: 
        !            65: #define        LE_ERR          0x8000          /* RO BABL | CERR | MISS | MERR */
        !            66: #define        LE_BABL         0x4000          /* RC transmitted too many bits */
        !            67: #define        LE_CERR         0x2000          /* RC No Heartbeat */
        !            68: #define        LE_MISS         0x1000          /* RC Missed an incoming packet */
        !            69: #define        LE_MERR         0x0800          /* RC Memory Error; no acknowledge */
        !            70: #define        LE_RINT         0x0400          /* RC Received packet Interrupt */
        !            71: #define        LE_TINT         0x0200          /* RC Transmitted packet Interrupt */
        !            72: #define        LE_IDON         0x0100          /* RC Initialization Done */
        !            73: #define        LE_INTR         0x0080          /* RO BABL|MISS|MERR|RINT|TINT|IDON */
        !            74: #define        LE_INEA         0x0040          /* RW Interrupt Enable */
        !            75: #define        LE_RXON         0x0020          /* RO Receiver On */
        !            76: #define        LE_TXON         0x0010          /* RO Transmitter On */
        !            77: #define        LE_TDMD         0x0008          /* W1 Transmit Demand (send it now) */
        !            78: #define        LE_STOP         0x0004          /* RW1 Stop */
        !            79: #define        LE_STRT         0x0002          /* RW1 Start */
        !            80: #define        LE_INIT         0x0001          /* RW1 Initialize */
        !            81: 
        !            82: /*
        !            83:  * CSR1  is   the low 16 bits of the address of the initialization block
        !            84:  * CSR2  is   the high 8 bits of the address of the initialization block
        !            85:  *           the high 8 bits of the register must be 0
        !            86:  * CSR3 mode bits:
        !            87:  *
        !            88:  */
        !            89: #define        LE_BSWP         0x4     /* Byte Swap (on for 68000 byte order) */
        !            90: #define        LE_ACON         0x2     /* ALE Control (on for active low ALE) */
        !            91: #define        LE_BCON         0x1     /* Byte Control (see the manual) */
        !            92: 
        !            93: /* The address contained in this structure must be longword aligned */
        !            94: struct le_drp {                        /* Descriptor Ring Pointer */
        !            95:        u_short drp_laddr;      /* Low 16 bits of ring address */
        !            96:        u_char  drp_len : 3;    /* Binary exponent of no. of ring entries */
        !            97:        u_char          : 5;    /* Reserved */
        !            98:        u_char  drp_haddr;      /* High 16 bits of ring address */
        !            99: };
        !           100: 
        !           101: /*
        !           102:  * Initialization Block.  This structure is constructed in memory,
        !           103:  * and it's address is written into the chip during initialization.
        !           104:  * The chip then fetches it's initialization info from the structure.
        !           105:  */
        !           106: struct le_init_block {
        !           107:        /* In the normal mode, these 16 bits are all 0 */
        !           108:        u_short ib_prom : 1;    /* Promiscuous Mode */
        !           109:        u_short                 : 7;    /* Reserved */
        !           110:        u_short ib_intl : 1;    /* Internal Loopback */
        !           111:        u_short ib_drty : 1;    /* Disable Retry */
        !           112:        u_short ib_coll : 1;    /* Force Collision */
        !           113:        u_short ib_dtcr : 1;    /* Disable Transmit CRC */
        !           114:        u_short ib_loop : 1;    /* Loopback */
        !           115:        u_short ib_dtx  : 1;    /* Disable Transmitter */
        !           116:        u_short ib_drx  : 1;    /* Disable Receiver */
        !           117: 
        !           118:        /*
        !           119:         * The bytes must be swapped within the word, so that, for example,
        !           120:         * the address 8:0:20:1:25:5a is written in the order
        !           121:         *             0 8 1 20 5a 25
        !           122:         */
        !           123:        u_char  ib_padr[6];
        !           124: 
        !           125:        u_char  ib_ladrf[8];
        !           126: 
        !           127:        struct  le_drp ib_rdrp; /* Receive Descriptor Ring Pointer */
        !           128:        struct  le_drp ib_tdrp; /* Transmit Descriptor Ring Pointer */
        !           129: };
        !           130: 
        !           131: struct le_md {                 /* Message Descriptor */
        !           132:        u_short lmd_ladr;       /* Low Order 16 Address Bits */
        !           133:        u_char  lmd_flags;
        !           134:        u_char  lmd_hadr: 8;    /* High Order 8 Address Bits */
        !           135:        u_short lmd_bcnt;       /* Buffer Byte Count (maximum length) */
        !           136:        u_short lmd_mcnt;       /* Message Byte Count (actual length) */
        !           137: };
        !           138: #define lmd_flags3 lmd_mcnt    /* for Transmit message descriptor */
        !           139: 
        !           140: /* Bits common to both rmds and tmds */
        !           141: #define        LMD_OWN         0x80    /* Chip owns the descriptor */
        !           142: #define        LMD_ERR         0x40    /* Error occurred */
        !           143: #define        LMD_STP         0x02    /* Start of Packet */
        !           144: #define        LMD_ENP         0x01    /* End of Packet */
        !           145: 
        !           146: /* Bits in rmd flags */
        !           147: #define        RMD_FRAM        0x20    /* Framing error */
        !           148: #define        RMD_OFLO        0x10    /* Internal Silo Overflowed. Valid if !ENP */
        !           149: #define        RMD_CRC         0x08    /* CRC Error */
        !           150: #define        RMD_BUFF        0x04    /* Didn't have a buffer for the packet */
        !           151: /* bits in tmd flags */
        !           152: #define        TMD_MORE        0x10    /* More than one retry was needed */
        !           153: #define        TMD_ONE         0x08    /* Exactly One Retry, valid only if !LCOL */
        !           154: #define        TMD_DEF         0x04    /* Deferred (net was initially busy) */
        !           155: 
        !           156: /* Bits for lmd_errflags */
        !           157: #define        TMD_BUFF 0x8000         /* Buffer Error (imples underflow too) */
        !           158: #define        TMD_UFLO 0x4000         /* Underflow Error */
        !           159: #define        TMD_LCOL 0x1000         /* Late Collision */
        !           160: #define        TMD_LCAR 0x0800         /* Loss of Carrier */
        !           161: #define        TMD_RTRY 0x0400         /* More than 16 Retry's */
        !           162: #define        TMD_TDR  0x003f         /* Time Domain Reflectometry counter mask */

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