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Annotation of researchv9/sys/sundev/sireg.h, revision 1.1

1.1     ! root        1: /*     @(#)sireg.h 1.1 86/02/03 SMI    */
        !             2: 
        !             3: /*
        !             4:  * Copyright (c) 1983 by Sun Microsystems, Inc.
        !             5:  */
        !             6: 
        !             7: /*
        !             8:  * Register definitions for the Sun3/50 onboard and Sun3 32-bit VME version 
        !             9:  * of the SCSI control logic interface. Both of these interfaces use the
        !            10:  * NCR 5380 SBC (SCSI Bus Controller). The main difference between these
        !            11:  * two interfaces is the dma interface. The Sun3/50 onboard version uses
        !            12:  * the AMD 9516 UDC (Universal DMA Controller).
        !            13:  * Since the NCR 5380 SBC chip is used, both interfaces support the SCSI
        !            14:  * disconnect/reconnect capability thus implying support for the scsi
        !            15:  * arbitration phase.
        !            16:  */
        !            17: 
        !            18: /*
        !            19:  * NCR 5380 SBC (SCSI Bus Controller) Registers.
        !            20:  */
        !            21: 
        !            22: /* read of sbc registers yields the following: */
        !            23: struct sbc_read_reg {
        !            24:        u_char          cdr;    /* current data register */
        !            25:        u_char          icr;    /* initiator command register */
        !            26:        u_char          mr;     /* mode register */
        !            27:        u_char          tcr;    /* target command register */
        !            28:        u_char          cbsr;   /* current bus status register */
        !            29:        u_char          bsr;    /* bus and status register */
        !            30:        u_char          idr;    /* input data register */
        !            31:        u_char          clr;    /* read to clear parity error, */
        !            32:                                /* interrupt request, and busy */
        !            33:                                /* failure bits in the bsr */
        !            34: };
        !            35: 
        !            36: /* write of sbc registers yields the following: */
        !            37: struct sbc_write_reg {
        !            38:        u_char          odr;    /* output data register */
        !            39:        u_char          icr;    /* initiator command register */
        !            40:        u_char          mr;     /* mode register */
        !            41:        u_char          tcr;    /* target command register */
        !            42:        u_char          ser;    /* select/reselect enable register */
        !            43:        u_char          send;   /* start dma for target/initiator send xfer */
        !            44:        u_char          trcv;   /* start dma for target receive transfer */
        !            45:        u_char          ircv;   /* start dma for initiator receive transfer */
        !            46: };
        !            47: 
        !            48: /* bits in the sbc initiator command register */
        !            49: #define        SBC_ICR_RST     0x80    /* (r/w) assert reset */
        !            50: #define SBC_ICR_AIP    0x40    /* (r)   arbitration in progress */
        !            51: #define SBC_ICR_TEST   0x40    /* (w)   test mode, disables output */
        !            52: #define SBC_ICR_LA     0x20    /* (r)   lost arbitration */
        !            53: #define SBC_ICR_DE     0x20    /* (w)   differential enable */
        !            54: #define SBC_ICR_ACK    0x10    /* (r/w) assert acknowledge */
        !            55: #define SBC_ICR_BUSY   0x08    /* (r/w) assert busy */
        !            56: #define SBC_ICR_SEL    0x04    /* (r/w) assert select */
        !            57: #define SBC_ICR_ATN    0x02    /* (r/w) assert attention */
        !            58: #define SBC_ICR_DATA   0x01    /* (r/w) assert data bus */
        !            59: 
        !            60: /* bits in the sbc mode register (same on read or write) */
        !            61: #define SBC_MR_BDMA    0x80    /* block mode dma */
        !            62: #define SBC_MR_TRG     0x40    /* target mode */
        !            63: #define SBC_MR_EPC     0x20    /* enable parity check */
        !            64: #define SBC_MR_EPI     0x10    /* enable parity interrupt */
        !            65: #define SBC_MR_EEI     0x08    /* enable eop interrupt */
        !            66: #define SBC_MR_MBSY    0x04    /* monitor busy */
        !            67: #define SBC_MR_DMA     0x02    /* dma mode */
        !            68: #define SBC_MR_ARB     0x01    /* arbitration mode */
        !            69: 
        !            70: /* bits in the sbc target command register */
        !            71: #define SBC_TCR_REQ    0x08    /* assert request */
        !            72: #define SBC_TCR_MSG    0x04    /* assert message */
        !            73: #define SBC_TCR_CD     0x02    /* assert command/data */
        !            74: #define SBC_TCR_IO     0x01    /* assert input/output */
        !            75: 
        !            76: /* settings of tcr to reflect different information transfer phases */
        !            77: #define TCR_COMMAND    (SBC_TCR_CD)
        !            78: #define TCR_MSG_OUT    (SBC_TCR_MSG | SBC_TCR_CD)
        !            79: #define TCR_DATA_OUT   0
        !            80: #define TCR_STATUS     (SBC_TCR_CD | SBC_TCR_IO)
        !            81: #define TCR_MSG_IN     (SBC_TCR_MSG | SBC_TCR_CD | SBC_TCR_IO)
        !            82: #define TCR_DATA_IN    (SBC_TCR_IO)
        !            83: #define TCR_UNSPECIFIED        (SBC_TCR_MSG)
        !            84: 
        !            85: /* bits in the sbc current bus status register */
        !            86: #define SBC_CBSR_RST   0x80    /* reset */
        !            87: #define SBC_CBSR_BSY   0x40    /* busy */
        !            88: #define SBC_CBSR_REQ   0x20    /* request */
        !            89: #define SBC_CBSR_MSG   0x10    /* message */
        !            90: #define SBC_CBSR_CD    0x08    /* command/data */
        !            91: #define SBC_CBSR_IO    0x04    /* input/output */
        !            92: #define SBC_CBSR_SEL   0x02    /* select */
        !            93: #define SBC_CBSR_DBP   0x01    /* data bus parity */
        !            94: 
        !            95: /* scsi bus signals reflecting different information transfer phases */
        !            96: #define CBSR_PHASE_BITS        (SBC_CBSR_CD | SBC_CBSR_MSG | SBC_CBSR_IO)
        !            97: #define PHASE_COMMAND  (SBC_CBSR_CD)
        !            98: #define PHASE_MSG_OUT  (SBC_CBSR_MSG | SBC_CBSR_CD)
        !            99: #define PHASE_DATA_OUT 0
        !           100: #define PHASE_STATUS   (SBC_CBSR_CD | SBC_CBSR_IO)
        !           101: #define PHASE_MSG_IN   (SBC_CBSR_MSG | SBC_CBSR_CD | SBC_CBSR_IO)
        !           102: #define PHASE_DATA_IN  (SBC_CBSR_IO)
        !           103: 
        !           104: /* bits in the sbc bus and status register */
        !           105: #define SBC_BSR_EDMA   0x80    /* end of dma */
        !           106: #define SBC_BSR_RDMA   0x40    /* dma request */
        !           107: #define SBC_BSR_PERR   0x20    /* parity error */
        !           108: #define SBC_BSR_INTR   0x10    /* interrupt request */
        !           109: #define SBC_BSR_PMTCH  0x08    /* phase match */
        !           110: #define SBC_BSR_BERR   0x04    /* busy error */
        !           111: #define SBC_BSR_ATN    0x02    /* attention */
        !           112: #define SBC_BSR_ACK    0x01    /* acknowledge */
        !           113: 
        !           114: /*
        !           115:  * AMD 9516 UDC (Universal DMA Controller) Registers.
        !           116:  * Sun3/50 only.
        !           117:  */
        !           118: 
        !           119: /* addresses of the udc registers accessed directly by driver */
        !           120: #define UDC_ADR_MODE           0x38    /* master mode register */
        !           121: #define UDC_ADR_COMMAND                0x2e    /* command register (write only) */
        !           122: #define UDC_ADR_STATUS         0x2e    /* status register (read only) */
        !           123: #define UDC_ADR_CAR_HIGH       0x26    /* chain addr reg, high word */
        !           124: #define UDC_ADR_CAR_LOW                0x22    /* chain addr reg, low word */
        !           125: #define UDC_ADR_CARA_HIGH      0x1a    /* cur addr reg A, high word */
        !           126: #define UDC_ADR_CARA_LOW       0x0a    /* cur addr reg A, low word */
        !           127: #define UDC_ADR_CARB_HIGH      0x12    /* cur addr reg B, high word */
        !           128: #define UDC_ADR_CARB_LOW       0x02    /* cur addr reg B, low word */
        !           129: #define UDC_ADR_CMR_HIGH       0x56    /* channel mode reg, high word */
        !           130: #define UDC_ADR_CMR_LOW                0x52    /* channel mode reg, low word */
        !           131: #define UDC_ADR_COUNT          0x32    /* number of words to transfer */
        !           132: 
        !           133: /* 
        !           134:  * For a dma transfer, the appropriate udc registers are loaded from a 
        !           135:  * table in memory pointed to by the chain address register.
        !           136:  */
        !           137: struct udc_table {
        !           138:        u_short                 rsel;   /* tells udc which regs to load */
        !           139:        u_short                 haddr;  /* high word of main mem dma address */
        !           140:        u_short                 laddr;  /* low word of main mem dma address */
        !           141:        u_short                 count;  /* num words to transfer */
        !           142:        u_short                 hcmr;   /* high word of channel mode reg */
        !           143:        u_short                 lcmr;   /* low word of channel mode reg */
        !           144: };
        !           145: 
        !           146: /* indicates which udc registers are to be set based on info in above table */
        !           147: #define UDC_RSEL_RECV          0x0182
        !           148: #define UDC_RSEL_SEND          0x0282
        !           149: 
        !           150: /* setting of chain mode reg: selects how the dma op is to be executed */
        !           151: #define UDC_CMR_HIGH           0x0040  /* high word of channel mode reg */
        !           152: #define UDC_CMR_LSEND          0x00c2  /* low word of cmr when send */
        !           153: #define UDC_CMR_LRECV          0x00d2  /* low word of cmr when receiving */
        !           154: 
        !           155: /* setting for the master mode register */
        !           156: #define UDC_MODE               0xd     /* enables udc chip */
        !           157: 
        !           158: /* setting for the low byte in the high word of an address */
        !           159: #define UDC_ADDR_INFO          0x40    /* inc addr after each word is dma'd */
        !           160: 
        !           161: /* udc commands */
        !           162: #define UDC_CMD_STRT_CHN       0xa0    /* start chaining */
        !           163: #define UDC_CMD_CIE            0x32    /* channel 1 interrupt enable */
        !           164: #define UDC_CMD_RESET          0x00    /* reset udc, same as hdw reset */
        !           165: 
        !           166: /* bits in the udc status register */
        !           167: #define UDC_SR_CIE             0x8000  /* channel interrupt enable */
        !           168: #define UDC_SR_IP              0x2000  /* interrupt pending */
        !           169: #define UDC_SR_CA              0x1000  /* channel abort */
        !           170: #define UDC_SR_NAC             0x0800  /* no auto reload or chaining*/
        !           171: #define UDC_SR_WFB             0x0400  /* waiting for bus */
        !           172: #define UDC_SR_SIP             0x0200  /* second interrupt pending */
        !           173: #define UDC_SR_HM              0x0040  /* hardware mask */
        !           174: #define UDC_SR_HRQ             0x0020  /* hardware request */
        !           175: #define UDC_SR_MCH             0x0010  /* match on upper comparator byte */
        !           176: #define UDC_SR_MCL             0x0008  /* match on lower comparator byte */
        !           177: #define UDC_SR_MC              0x0004  /* match condition ended dma */
        !           178: #define UDC_SR_EOP             0x0002  /* eop condition ended dma */
        !           179: #define UDC_SR_TC              0x0001  /* termination of count ended dma */
        !           180: 
        !           181: /*
        !           182:  * Misc defines 
        !           183:  */
        !           184: 
        !           185: /* arbitraty retry count */
        !           186: #define SI_NUM_RETRIES         2
        !           187: 
        !           188: /* scsi timer values, all in microseconds */
        !           189: #define SI_ARBITRATION_DELAY   3
        !           190: #define SI_BUS_CLEAR_DELAY     1
        !           191: #define SI_BUS_SETTLE_DELAY    1
        !           192: #define SI_UDC_WAIT            1
        !           193: #define        SI_WAIT_COUNT           250000
        !           194: 
        !           195: /* directions for dma transfers */
        !           196: #define SI_RECV_DATA           0
        !           197: #define SI_SEND_DATA           1
        !           198: #define SI_NO_DATA             2
        !           199: 
        !           200: /* initiator's scsi device id */
        !           201: #define        SI_HOST_ID              0x80
        !           202: 
        !           203: /* possible values for the address modifier, sun3 vme version only */
        !           204: #define VME_SUPV_DATA_24       0x3d00
        !           205: 
        !           206: /* must massage dvma addresses for Sun3/50 hardware */
        !           207: #define DVMA_OFFSET    (int)(DVMA - (char *)KERNELBASE)
        !           208: 
        !           209: /* 
        !           210:  * Register layout for the SCSI control logic interface.
        !           211:  * Some of these registers apply to only one interface and some
        !           212:  * apply to both. The registers which apply to the Sun3/50 onboard 
        !           213:  * version only are udc_rdata and udc_raddr. The registers which
        !           214:  * apply to the Sun3 vme version only are dma_addr, dma_count, bpr,
        !           215:  * iv_am, and bcrh. Thus, the sbc registers, fifo_data, bcr, and csr 
        !           216:  * apply to both interfaces.
        !           217:  * One other feature of the vme interface: a write to the dma count 
        !           218:  * register also causes a write to the fifo byte count register and
        !           219:  * vis versa.
        !           220:  */
        !           221: struct scsi_si_reg {
        !           222:        union {
        !           223:                struct sbc_read_reg     read;   /* scsi bus ctlr, read reg */
        !           224:                struct sbc_write_reg    write;  /* scsi bus ctlr, write reg */
        !           225:        } sbc;
        !           226: #define sbc_rreg sbc.read
        !           227: #define sbc_wreg sbc.write
        !           228:        u_int                   dma_addr;       /* dma address register */
        !           229:        u_int                   dma_count;      /* dma count register */
        !           230:        u_short                 udc_rdata;      /* univ dma ctlr, reg data */
        !           231:        u_short                 udc_raddr;      /* univ dma ctlr, reg addr */
        !           232:        u_short                 fifo_data;      /* fifo data register */
        !           233:                                                /* holds extra byte on odd */
        !           234:                                                /* byte dma read */
        !           235:        u_short                 bcr;            /* fifo byte count reg */
        !           236:        u_short                 csr;            /* control/status register */
        !           237:        u_int                   bpr;            /* byte pack register */
        !           238:        u_short                 iv_am;          /* bits 0-7: addr modifier */
        !           239:                                                /* bits 8-13: intr vector */
        !           240:                                                /* bits 14-15: unused */
        !           241:        u_short                 bcrh;           /* high portion of bcr */
        !           242: };
        !           243: 
        !           244: /*
        !           245:  * Status Register.
        !           246:  * Note:
        !           247:  *     (r)     indicates bit is read only.
        !           248:  *     (rw)    indicates bit is read or write.
        !           249:  *     (v)     vme host adaptor interface only.
        !           250:  *     (o)     sun3/50 onboard host adaptor interface only.
        !           251:  *     (b)     both vme and sun3/50 host adaptor interfaces.
        !           252:  */
        !           253: #define SI_CSR_DMA_ACTIVE      0x8000  /* (r,o) dma transfer active */
        !           254: #define SI_CSR_DMA_CONFLICT    0x4000  /* (r,b) reg accessed while dmaing */
        !           255: #define SI_CSR_DMA_BUS_ERR     0x2000  /* (r,b) bus error during dma */
        !           256: #define SI_CSR_UNUSED          0x1000  /* (r,b) always read as zero */
        !           257: #define SI_CSR_FIFO_FULL       0x0800  /* (r,b) fifo full */
        !           258: #define SI_CSR_FIFO_EMPTY      0x0400  /* (r,b) fifo empty */
        !           259: #define SI_CSR_SBC_IP          0x0200  /* (r,b) sbc interrupt pending */
        !           260: #define SI_CSR_DMA_IP          0x0100  /* (r,b) dma interrupt pending */
        !           261: #define SI_CSR_LOB             0x00c0  /* (r,v) number of leftover bytes */
        !           262: #define SI_CSR_LOB_THREE       0x00c0  /* (r,v) three leftover bytes */
        !           263: #define SI_CSR_LOB_TWO         0x0080  /* (r,v) two leftover bytes */
        !           264: #define SI_CSR_LOB_ONE         0x0040  /* (r,v) one leftover byte */
        !           265: #define SI_CSR_BPCON           0x0020  /* (rw,v) byte packing control */
        !           266:                                        /* dma is in 0=longwords, 1=words */
        !           267: #define SI_CSR_DMA_EN          0x0010  /* (rw,v) dma enable */
        !           268: #define SI_CSR_SEND            0x0008  /* (rw,b) dma dir, 1=to device */
        !           269: #define SI_CSR_INTR_EN         0x0004  /* (rw,b) interrupts enable */
        !           270: #define SI_CSR_FIFO_RES                0x0002  /* (rw,b) inits fifo, 0=reset */
        !           271: #define SI_CSR_SCSI_RES                0x0001  /* (rw,b) reset sbc and udc, 0=reset */

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