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1.1 root 1: /* uartdefs.h */
2:
3: /* 8250 Universal Asynchronous Receiver/Transmitter definitions */
4:
5: /* $Id: uartdefs.h,v 1.5 2006/06/20 22:25:37 rswindell Exp $ */
6:
7: /****************************************************************************
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10: * *
11: * Copyright 2006 Rob Swindell - http://www.synchro.net/copyright.html *
12: * *
13: * This program is free software; you can redistribute it and/or *
14: * modify it under the terms of the GNU General Public License *
15: * as published by the Free Software Foundation; either version 2 *
16: * of the License, or (at your option) any later version. *
17: * See the GNU General Public License for more details: gpl.txt or *
18: * http://www.fsf.org/copyleft/gpl.html *
19: * *
20: * Anonymous FTP access to the most recent released source is available at *
21: * ftp://vert.synchro.net, ftp://cvs.synchro.net and ftp://ftp.synchro.net *
22: * *
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27: * cvs -d :pserver:[email protected]:/cvsroot/sbbs checkout src *
28: * *
29: * For Synchronet coding style and modification guidelines, see *
30: * http://www.synchro.net/source.html *
31: * *
32: * You are encouraged to submit any modifications (preferably in Unix diff *
33: * format) via e-mail to [email protected] *
34: * *
35: * Note: If this box doesn't appear square, then you need to fix your tabs. *
36: ****************************************************************************/
37:
38: #ifndef _UARTDEFS_H
39: #define _UARTDEFS_H
40:
41: /* UART Registers */
42: #define UART_BASE 0 /* tx/rx data */
43: #define UART_IER 1 /* interrupt enable */
44: #define UART_IIR 2 /* interrupt identification */
45: #define UART_FCR 2 /* FIFO control */
46: #define UART_LCR 3 /* line control */
47: #define UART_MCR 4 /* modem control */
48: #define UART_LSR 5 /* line status */
49: #define UART_MSR 6 /* modem status */
50: #define UART_SCRATCH 7 /* scratch */
51: #define UART_IO_RANGE UART_SCRATCH
52:
53: const char* uart_reg_desc[] = { "base", "IER", "IIR", "LCR", "MCR", "LSR", "MSR", "scratch" };
54:
55: #define UART_IER_MODEM_STATUS (1<<3)
56: #define UART_IER_LINE_STATUS (1<<2)
57: #define UART_IER_TX_EMPTY (1<<1)
58: #define UART_IER_RX_DATA (1<<0)
59:
60: #define UART_IIR_MODEM_STATUS 0x00
61: #define UART_IIR_NONE 0x01 /* Bit 0=0, Interrupt Pending */
62: #define UART_IIR_TX_EMPTY 0x02 /* THRE (Transmit Holding Register Empty) */
63: #define UART_IIR_RX_DATA 0x04
64: #define UART_IIR_LINE_STATUS 0x06
65:
66: #define UART_LSR_FIFO_ERROR (1<<7)
67: #define UART_LSR_EMPTY_DATA (1<<6)
68: #define UART_LSR_EMPTY_XMIT (1<<5)
69: #define UART_LSR_BREAK (1<<4)
70: #define UART_LSR_FRAME_ERROR (1<<3)
71: #define UART_LSR_PARITY_ERROR (1<<2)
72: #define UART_LSR_OVERRUN_ERROR (1<<1)
73: #define UART_LSR_DATA_READY (1<<0)
74:
75: #define UART_MSR_DCD (1<<7)
76: #define UART_MSR_RING (1<<6)
77: #define UART_MSR_DSR (1<<5)
78: #define UART_MSR_CTS (1<<4)
79: #define UART_MSR_DCD_CHANGE (1<<3)
80: #define UART_MSR_RING_CHANGE (1<<2)
81: #define UART_MSR_DSR_CHANGE (1<<1)
82: #define UART_MSR_CTS_CHANGE (1<<0)
83:
84: #define UART_LCR_DLAB (1<<7)
85: #define UART_LCR_BREAK (1<<6)
86: #define UART_LCR_8_DATA_BITS 0x03 /* 8 data bits */
87:
88: #define UART_MCR_DTR (1<<0)
89: #define UART_MCR_RTS (1<<1)
90: #define UART_MCR_AUX1 (1<<2)
91: #define UART_MCR_AUX2 (1<<3)
92: #define UART_MCR_LOOPBACK (1<<4)
93:
94: /* I/O Ports */
95: #define UART_COM1_IO_BASE 0x3f8
96: #define UART_COM2_IO_BASE 0x2f8
97: #define UART_COM3_IO_BASE 0x3e8
98: #define UART_COM4_IO_BASE 0x2e8
99:
100: /* IRQs */
101: #define UART_COM1_IRQ 4
102: #define UART_COM2_IRQ 3
103: #define UART_COM3_IRQ 4
104: #define UART_COM4_IRQ 3
105:
106: #endif /* Don't add anything after this line */
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