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1.1 root 1: /* automatically generated by bus-device-auto.sh, do not edit! */ 1.1.1.2 ! root 2: _TME_RCSID("$Id: bus-device-auto.sh,v 1.2 2006/09/30 12:43:35 fredette Exp $"); 1.1 root 3: 4: /* this indexes an initiator bus router array for a device with a port size 5: of 8 * (2 ^ siz_lg2) bits: */ 6: #define TME_BUS_ROUTER_INIT_INDEX(siz_lg2, cycle_size, address) \ 7: ((( \ 8: /* by the maximum cycle size: */ \ 9: ((cycle_size) - 1) \ 10: \ 11: /* by the address alignment: */ \ 12: << siz_lg2) \ 13: + ((address) & ((1 << (siz_lg2)) - 1))) \ 14: \ 15: /* factor in the size of the generic bus router array: */ \ 16: * TME_BUS_ROUTER_SIZE(siz_lg2)) 17: 18: /* this gives the number of entries that must be in a generic bus 19: router array for a device with a bus size of 8 * (2 ^ siz_lg2) 20: bits: */ 21: #define TME_BUS_ROUTER_INIT_SIZE(siz_lg2) \ 22: TME_BUS_ROUTER_INIT_INDEX(siz_lg2, (1 << (siz_lg2)) + 1, 0) 23: 24: 25: /* the 16-bit big-endian bus master bus router: */ 26: const tme_bus_lane_t tme_bus_device_router_16eb[TME_BUS_ROUTER_INIT_SIZE(TME_BUS16_LOG2)] = { 27: 28: /* initiator maximum cycle size: 8 bits 29: initiator address offset: 0 bits 30: responder bus port size: 8 bits 31: responder port least lane: D7-D0: */ 32: /* D7-D0 */ TME_BUS_LANE_UNDEF, 33: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 34: 35: /* initiator maximum cycle size: 8 bits 36: initiator address offset: 0 bits 37: responder bus port size: 8 bits 38: responder port least lane: D15-D8: */ 39: /* D7-D0 */ TME_BUS_LANE_UNDEF, 40: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 41: 42: /* initiator maximum cycle size: 8 bits 43: initiator address offset: 0 bits 44: responder bus port size: 16 bits 45: responder port least lane: D7-D0: */ 46: /* D7-D0 */ TME_BUS_LANE_UNDEF, 47: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 48: 49: /* initiator maximum cycle size: 8 bits 50: initiator address offset: 0 bits 51: responder bus port size: 16 bits 52: responder port least lane: D15-D8 53: (responder port not correctly positioned for this initiator): */ 54: /* D7-D0 */ TME_BUS_LANE_UNDEF, 55: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 56: 57: /* initiator maximum cycle size: 8 bits 58: initiator address offset: 8 bits 59: responder bus port size: 8 bits 60: responder port least lane: D7-D0: */ 61: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 62: /* D15-D8 */ TME_BUS_LANE_UNDEF, 63: 64: /* initiator maximum cycle size: 8 bits 65: initiator address offset: 8 bits 66: responder bus port size: 8 bits 67: responder port least lane: D15-D8: */ 68: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 69: /* D15-D8 */ TME_BUS_LANE_UNDEF, 70: 71: /* initiator maximum cycle size: 8 bits 72: initiator address offset: 8 bits 73: responder bus port size: 16 bits 74: responder port least lane: D7-D0: */ 75: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 76: /* D15-D8 */ TME_BUS_LANE_UNDEF, 77: 78: /* initiator maximum cycle size: 8 bits 79: initiator address offset: 8 bits 80: responder bus port size: 16 bits 81: responder port least lane: D15-D8 82: (responder port not correctly positioned for this initiator): */ 83: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 84: /* D15-D8 */ TME_BUS_LANE_UNDEF, 85: 86: /* initiator maximum cycle size: 16 bits 87: initiator address offset: 0 bits 88: responder bus port size: 8 bits 89: responder port least lane: D7-D0: */ 90: /* D7-D0 */ TME_BUS_LANE_ROUTE(1), 91: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 92: 93: /* initiator maximum cycle size: 16 bits 94: initiator address offset: 0 bits 95: responder bus port size: 8 bits 96: responder port least lane: D15-D8: */ 97: /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 98: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 99: 100: /* initiator maximum cycle size: 16 bits 101: initiator address offset: 0 bits 102: responder bus port size: 16 bits 103: responder port least lane: D7-D0: */ 104: /* D7-D0 */ TME_BUS_LANE_ROUTE(1), 105: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 106: 107: /* initiator maximum cycle size: 16 bits 108: initiator address offset: 0 bits 109: responder bus port size: 16 bits 110: responder port least lane: D15-D8 111: (responder port not correctly positioned for this initiator): */ 112: /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 113: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 114: 115: /* initiator maximum cycle size: 16 bits 116: initiator address offset: 8 bits 117: (a 16-bit initiator cannot request 16 bits at an 8-bit offset - this is an array placeholder) 118: responder bus port size: 8 bits 119: responder port least lane: D7-D0: */ 120: /* D7-D0 */ TME_BUS_LANE_ABORT, 121: /* D15-D8 */ TME_BUS_LANE_ABORT, 122: 123: /* initiator maximum cycle size: 16 bits 124: initiator address offset: 8 bits 125: (a 16-bit initiator cannot request 16 bits at an 8-bit offset - this is an array placeholder) 126: responder bus port size: 8 bits 127: responder port least lane: D15-D8: */ 128: /* D7-D0 */ TME_BUS_LANE_ABORT, 129: /* D15-D8 */ TME_BUS_LANE_ABORT, 130: 131: /* initiator maximum cycle size: 16 bits 132: initiator address offset: 8 bits 133: (a 16-bit initiator cannot request 16 bits at an 8-bit offset - this is an array placeholder) 134: responder bus port size: 16 bits 135: responder port least lane: D7-D0: */ 136: /* D7-D0 */ TME_BUS_LANE_ABORT, 137: /* D15-D8 */ TME_BUS_LANE_ABORT, 138: 139: /* initiator maximum cycle size: 16 bits 140: initiator address offset: 8 bits 141: (a 16-bit initiator cannot request 16 bits at an 8-bit offset - this is an array placeholder) 142: responder bus port size: 16 bits 143: responder port least lane: D15-D8 144: (responder port not correctly positioned for this initiator): */ 145: /* D7-D0 */ TME_BUS_LANE_ABORT, 146: /* D15-D8 */ TME_BUS_LANE_ABORT, 147: }; 148: 149: /* the 16-bit little-endian bus master bus router: */ 150: const tme_bus_lane_t tme_bus_device_router_16el[TME_BUS_ROUTER_INIT_SIZE(TME_BUS16_LOG2)] = { 151: 152: /* initiator maximum cycle size: 8 bits 153: initiator address offset: 0 bits 154: responder bus port size: 8 bits 155: responder port least lane: D7-D0: */ 156: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 157: /* D15-D8 */ TME_BUS_LANE_UNDEF, 158: 159: /* initiator maximum cycle size: 8 bits 160: initiator address offset: 0 bits 161: responder bus port size: 8 bits 162: responder port least lane: D15-D8: */ 163: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 164: /* D15-D8 */ TME_BUS_LANE_UNDEF, 165: 166: /* initiator maximum cycle size: 8 bits 167: initiator address offset: 0 bits 168: responder bus port size: 16 bits 169: responder port least lane: D7-D0: */ 170: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 171: /* D15-D8 */ TME_BUS_LANE_UNDEF, 172: 173: /* initiator maximum cycle size: 8 bits 174: initiator address offset: 0 bits 175: responder bus port size: 16 bits 176: responder port least lane: D15-D8 177: (responder port not correctly positioned for this initiator): */ 178: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 179: /* D15-D8 */ TME_BUS_LANE_UNDEF, 180: 181: /* initiator maximum cycle size: 8 bits 182: initiator address offset: 8 bits 183: responder bus port size: 8 bits 184: responder port least lane: D7-D0: */ 185: /* D7-D0 */ TME_BUS_LANE_UNDEF, 186: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 187: 188: /* initiator maximum cycle size: 8 bits 189: initiator address offset: 8 bits 190: responder bus port size: 8 bits 191: responder port least lane: D15-D8: */ 192: /* D7-D0 */ TME_BUS_LANE_UNDEF, 193: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 194: 195: /* initiator maximum cycle size: 8 bits 196: initiator address offset: 8 bits 197: responder bus port size: 16 bits 198: responder port least lane: D7-D0: */ 199: /* D7-D0 */ TME_BUS_LANE_UNDEF, 200: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 201: 202: /* initiator maximum cycle size: 8 bits 203: initiator address offset: 8 bits 204: responder bus port size: 16 bits 205: responder port least lane: D15-D8 206: (responder port not correctly positioned for this initiator): */ 207: /* D7-D0 */ TME_BUS_LANE_UNDEF, 208: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 209: 210: /* initiator maximum cycle size: 16 bits 211: initiator address offset: 0 bits 212: responder bus port size: 8 bits 213: responder port least lane: D7-D0: */ 214: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 215: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 216: 217: /* initiator maximum cycle size: 16 bits 218: initiator address offset: 0 bits 219: responder bus port size: 8 bits 220: responder port least lane: D15-D8: */ 221: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 222: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 223: 224: /* initiator maximum cycle size: 16 bits 225: initiator address offset: 0 bits 226: responder bus port size: 16 bits 227: responder port least lane: D7-D0: */ 228: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 229: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 230: 231: /* initiator maximum cycle size: 16 bits 232: initiator address offset: 0 bits 233: responder bus port size: 16 bits 234: responder port least lane: D15-D8 235: (responder port not correctly positioned for this initiator): */ 236: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 237: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 238: 239: /* initiator maximum cycle size: 16 bits 240: initiator address offset: 8 bits 241: (a 16-bit initiator cannot request 16 bits at an 8-bit offset - this is an array placeholder) 242: responder bus port size: 8 bits 243: responder port least lane: D7-D0: */ 244: /* D7-D0 */ TME_BUS_LANE_ABORT, 245: /* D15-D8 */ TME_BUS_LANE_ABORT, 246: 247: /* initiator maximum cycle size: 16 bits 248: initiator address offset: 8 bits 249: (a 16-bit initiator cannot request 16 bits at an 8-bit offset - this is an array placeholder) 250: responder bus port size: 8 bits 251: responder port least lane: D15-D8: */ 252: /* D7-D0 */ TME_BUS_LANE_ABORT, 253: /* D15-D8 */ TME_BUS_LANE_ABORT, 254: 255: /* initiator maximum cycle size: 16 bits 256: initiator address offset: 8 bits 257: (a 16-bit initiator cannot request 16 bits at an 8-bit offset - this is an array placeholder) 258: responder bus port size: 16 bits 259: responder port least lane: D7-D0: */ 260: /* D7-D0 */ TME_BUS_LANE_ABORT, 261: /* D15-D8 */ TME_BUS_LANE_ABORT, 262: 263: /* initiator maximum cycle size: 16 bits 264: initiator address offset: 8 bits 265: (a 16-bit initiator cannot request 16 bits at an 8-bit offset - this is an array placeholder) 266: responder bus port size: 16 bits 267: responder port least lane: D15-D8 268: (responder port not correctly positioned for this initiator): */ 269: /* D7-D0 */ TME_BUS_LANE_ABORT, 270: /* D15-D8 */ TME_BUS_LANE_ABORT, 271: }; 272: 273: /* the 16-bit bus master DMA read function: */ 274: int 275: tme_bus_device_dma_read_16(struct tme_bus_device *bus_device, 276: tme_bus_addr_t address_init, 277: tme_bus_addr_t size, 278: tme_uint8_t *buffer, 279: unsigned int locks) 280: { 281: struct tme_bus_tlb *tlb, tlb_local; 282: struct tme_bus_connection *conn_bus; 283: tme_bus_addr_t count_minus_one, count; 284: struct tme_bus_cycle cycle; 285: tme_bus_addr_t address_resp; 286: int shift; 287: int err; 288: 289: /* assume no error: */ 290: err = TME_OK; 291: 292: /* loop while we have more bytes to read: */ 293: for (; err == TME_OK && size > 0; ) { 294: 295: /* hash this address into a TLB entry: */ 296: tlb = (*bus_device->tme_bus_device_tlb_hash) 297: (bus_device, 298: address_init, 299: TME_BUS_CYCLE_READ); 300: 1.1.1.2 ! root 301: /* busy this TLB entry: */ ! 302: tme_bus_tlb_busy(tlb); ! 303: ! 304: /* if this TLB entry is invalid, doesn't cover this address, or if it doesn't 1.1 root 305: allow reading, reload it: */ 1.1.1.2 ! root 306: if (tme_bus_tlb_is_invalid(tlb) ! 307: || address_init < tlb->tme_bus_tlb_addr_first ! 308: || address_init > tlb->tme_bus_tlb_addr_last 1.1 root 309: || (tlb->tme_bus_tlb_emulator_off_read == TME_EMULATOR_OFF_UNDEF 310: && !(tlb->tme_bus_tlb_cycles_ok & TME_BUS_CYCLE_READ))) { 311: 1.1.1.2 ! root 312: /* unbusy this TLB entry for filling: */ ! 313: tme_bus_tlb_unbusy_fill(tlb); ! 314: 1.1 root 315: /* reserve this TLB entry: */ 1.1.1.2 ! root 316: tlb_local.tme_bus_tlb_global = tlb; 1.1 root 317: tlb = &tlb_local; 318: 319: /* get our bus connection: */ 1.1.1.2 ! root 320: conn_bus = tme_memory_atomic_pointer_read(struct tme_bus_connection *, ! 321: bus_device->tme_bus_device_connection, ! 322: &bus_device->tme_bus_device_connection_rwlock); 1.1 root 323: 324: /* unlock the device: */ 325: (*bus_device->tme_bus_device_unlock)(bus_device, locks); 326: 327: /* reload the TLB entry: */ 328: err = (*conn_bus->tme_bus_tlb_fill) 329: (conn_bus, 330: tlb, 331: address_init, 332: TME_BUS_CYCLE_READ); 333: 334: /* lock the device: */ 335: (*bus_device->tme_bus_device_lock)(bus_device, locks); 336: 337: /* return if we couldn't fill the TLB entry: */ 338: if (err != TME_OK) { 339: return (err); 340: } 341: 342: /* store the TLB entry: */ 343: tme_bus_tlb_back(tlb); 1.1.1.2 ! root 344: ! 345: /* loop to check the newly filled TLB entry: */ ! 346: continue; 1.1 root 347: } 348: 349: /* if this TLB entry allows fast reading: */ 350: if (tlb->tme_bus_tlb_emulator_off_read != TME_EMULATOR_OFF_UNDEF) { 351: 352: /* see how many bytes we can fast read from this TLB entry, 353: starting at this address: */ 1.1.1.2 ! root 354: count_minus_one = (tlb->tme_bus_tlb_addr_last - address_init); 1.1 root 355: 356: /* read that many bytes or size bytes, whichever is smaller: */ 357: count_minus_one = TME_MIN(count_minus_one, 358: (size - 1)); 359: count = count_minus_one + 1; 360: assert (count != 0); 361: 1.1.1.2 ! root 362: /* do the bus read: */ ! 363: tme_memory_bus_read_buffer((tlb->tme_bus_tlb_emulator_off_read + address_init), buffer, count, tlb->tme_bus_tlb_rwlock, sizeof(tme_uint8_t), sizeof(tme_uint16_t)); ! 364: ! 365: /* unbusy this TLB entry: */ ! 366: tme_bus_tlb_unbusy(tlb); 1.1 root 367: } 368: 369: /* otherwise, we have to do a slow read: */ 370: else { 371: 372: /* get the size of this bus cycle: */ 373: count = (1 << TME_BUS16_LOG2); 374: count -= (address_init & (count - 1)); 375: count = TME_MIN(count, size); 376: 377: /* fill the cycle structure: */ 378: cycle.tme_bus_cycle_type = TME_BUS_CYCLE_READ; 379: cycle.tme_bus_cycle_size = count; 380: cycle.tme_bus_cycle_buffer = (tme_uint8_t *) buffer; /* XXX this breaks const */ 381: cycle.tme_bus_cycle_buffer_increment = 1; 382: cycle.tme_bus_cycle_lane_routing 383: = (bus_device->tme_bus_device_router 384: + TME_BUS_ROUTER_INIT_INDEX(TME_BUS16_LOG2, count, address_init)); 385: 386: /* XXX this should come from a socket configuration: */ 387: cycle.tme_bus_cycle_port = TME_BUS_CYCLE_PORT(0, TME_BUS16_LOG2); 388: 389: /* form the physical address for the bus cycle handler: */ 390: address_resp = tlb->tme_bus_tlb_addr_offset + address_init; 391: shift = tlb->tme_bus_tlb_addr_shift; 392: if (shift < 0) { 393: address_resp <<= (0 - shift); 394: } 395: else if (shift > 0) { 396: address_resp >>= shift; 397: } 398: cycle.tme_bus_cycle_address = address_resp; 399: 1.1.1.2 ! root 400: /* unbusy this TLB entry: */ ! 401: tme_bus_tlb_unbusy(tlb); ! 402: 1.1 root 403: /* unlock the device: */ 404: (*bus_device->tme_bus_device_unlock)(bus_device, locks); 405: 406: /* run the bus cycle: */ 407: err = (*tlb->tme_bus_tlb_cycle) 408: (tlb->tme_bus_tlb_cycle_private, &cycle); 409: 1.1.1.2 ! root 410: /* if the TLB entry was invalidated before the read: */ ! 411: if (err == EBADF ! 412: && tme_bus_tlb_is_invalid(tlb)) { ! 413: count = 0; 1.1 root 414: } 415: 416: /* otherwise, any other error might be a bus error: */ 417: else if (err != TME_OK) { 418: err = tme_bus_tlb_fault(tlb, &cycle, err); 419: assert (err != TME_OK); 420: } 421: 422: /* lock the device: */ 423: (*bus_device->tme_bus_device_lock)(bus_device, locks); 424: } 425: 426: /* update the address, buffer, and size and continue: */ 427: address_init += count; 428: buffer += count; 429: size -= count; 430: } 431: 432: return (err); 433: } 434: 435: /* the 16-bit bus master DMA write function: */ 436: int 437: tme_bus_device_dma_write_16(struct tme_bus_device *bus_device, 438: tme_bus_addr_t address_init, 439: tme_bus_addr_t size, 440: const tme_uint8_t *buffer, 441: unsigned int locks) 442: { 443: struct tme_bus_tlb *tlb, tlb_local; 444: struct tme_bus_connection *conn_bus; 445: tme_bus_addr_t count_minus_one, count; 446: struct tme_bus_cycle cycle; 447: tme_bus_addr_t address_resp; 448: int shift; 449: int err; 450: 451: /* assume no error: */ 452: err = TME_OK; 453: 454: /* loop while we have more bytes to write: */ 455: for (; err == TME_OK && size > 0; ) { 456: 457: /* hash this address into a TLB entry: */ 458: tlb = (*bus_device->tme_bus_device_tlb_hash) 459: (bus_device, 460: address_init, 461: TME_BUS_CYCLE_WRITE); 462: 1.1.1.2 ! root 463: /* busy this TLB entry: */ ! 464: tme_bus_tlb_busy(tlb); ! 465: ! 466: /* if this TLB entry is invalid, doesn't cover this address, or if it doesn't 1.1 root 467: allow writing, reload it: */ 1.1.1.2 ! root 468: if (tme_bus_tlb_is_invalid(tlb) ! 469: || address_init < tlb->tme_bus_tlb_addr_first ! 470: || address_init > tlb->tme_bus_tlb_addr_last 1.1 root 471: || (tlb->tme_bus_tlb_emulator_off_write == TME_EMULATOR_OFF_UNDEF 472: && !(tlb->tme_bus_tlb_cycles_ok & TME_BUS_CYCLE_WRITE))) { 473: 1.1.1.2 ! root 474: /* unbusy this TLB entry for filling: */ ! 475: tme_bus_tlb_unbusy_fill(tlb); ! 476: 1.1 root 477: /* reserve this TLB entry: */ 1.1.1.2 ! root 478: tlb_local.tme_bus_tlb_global = tlb; 1.1 root 479: tlb = &tlb_local; 480: 481: /* get our bus connection: */ 1.1.1.2 ! root 482: conn_bus = tme_memory_atomic_pointer_read(struct tme_bus_connection *, ! 483: bus_device->tme_bus_device_connection, ! 484: &bus_device->tme_bus_device_connection_rwlock); 1.1 root 485: 486: /* unlock the device: */ 487: (*bus_device->tme_bus_device_unlock)(bus_device, locks); 488: 489: /* reload the TLB entry: */ 490: err = (*conn_bus->tme_bus_tlb_fill) 491: (conn_bus, 492: tlb, 493: address_init, 494: TME_BUS_CYCLE_WRITE); 495: 496: /* lock the device: */ 497: (*bus_device->tme_bus_device_lock)(bus_device, locks); 498: 499: /* return if we couldn't fill the TLB entry: */ 500: if (err != TME_OK) { 501: return (err); 502: } 503: 504: /* store the TLB entry: */ 505: tme_bus_tlb_back(tlb); 1.1.1.2 ! root 506: ! 507: /* loop to check the newly filled TLB entry: */ ! 508: continue; 1.1 root 509: } 510: 511: /* if this TLB entry allows fast writing: */ 512: if (tlb->tme_bus_tlb_emulator_off_write != TME_EMULATOR_OFF_UNDEF) { 513: 514: /* see how many bytes we can fast write to this TLB entry, 515: starting at this address: */ 1.1.1.2 ! root 516: count_minus_one = (tlb->tme_bus_tlb_addr_last - address_init); 1.1 root 517: 518: /* write that many bytes or size bytes, whichever is smaller: */ 519: count_minus_one = TME_MIN(count_minus_one, 520: (size - 1)); 521: count = count_minus_one + 1; 522: assert (count != 0); 523: 1.1.1.2 ! root 524: /* do the bus write: */ ! 525: tme_memory_bus_write_buffer((tlb->tme_bus_tlb_emulator_off_write + address_init), buffer, count, tlb->tme_bus_tlb_rwlock, sizeof(tme_uint8_t), sizeof(tme_uint16_t)); ! 526: ! 527: /* unbusy this TLB entry: */ ! 528: tme_bus_tlb_unbusy(tlb); 1.1 root 529: } 530: 531: /* otherwise, we have to do a slow write: */ 532: else { 533: 534: /* get the size of this bus cycle: */ 535: count = (1 << TME_BUS16_LOG2); 536: count -= (address_init & (count - 1)); 537: count = TME_MIN(count, size); 538: 539: /* fill the cycle structure: */ 540: cycle.tme_bus_cycle_type = TME_BUS_CYCLE_WRITE; 541: cycle.tme_bus_cycle_size = count; 542: cycle.tme_bus_cycle_buffer = (tme_uint8_t *) buffer; /* XXX this breaks const */ 543: cycle.tme_bus_cycle_buffer_increment = 1; 544: cycle.tme_bus_cycle_lane_routing 545: = (bus_device->tme_bus_device_router 546: + TME_BUS_ROUTER_INIT_INDEX(TME_BUS16_LOG2, count, address_init)); 547: 548: /* XXX this should come from a socket configuration: */ 549: cycle.tme_bus_cycle_port = TME_BUS_CYCLE_PORT(0, TME_BUS16_LOG2); 550: 551: /* form the physical address for the bus cycle handler: */ 552: address_resp = tlb->tme_bus_tlb_addr_offset + address_init; 553: shift = tlb->tme_bus_tlb_addr_shift; 554: if (shift < 0) { 555: address_resp <<= (0 - shift); 556: } 557: else if (shift > 0) { 558: address_resp >>= shift; 559: } 560: cycle.tme_bus_cycle_address = address_resp; 561: 1.1.1.2 ! root 562: /* unbusy this TLB entry: */ ! 563: tme_bus_tlb_unbusy(tlb); ! 564: 1.1 root 565: /* unlock the device: */ 566: (*bus_device->tme_bus_device_unlock)(bus_device, locks); 567: 568: /* run the bus cycle: */ 569: err = (*tlb->tme_bus_tlb_cycle) 570: (tlb->tme_bus_tlb_cycle_private, &cycle); 571: 1.1.1.2 ! root 572: /* if the TLB entry was invalidated before the write: */ ! 573: if (err == EBADF ! 574: && tme_bus_tlb_is_invalid(tlb)) { ! 575: count = 0; 1.1 root 576: } 577: 578: /* otherwise, any other error might be a bus error: */ 579: else if (err != TME_OK) { 580: err = tme_bus_tlb_fault(tlb, &cycle, err); 581: assert (err != TME_OK); 582: } 583: 584: /* lock the device: */ 585: (*bus_device->tme_bus_device_lock)(bus_device, locks); 586: } 587: 588: /* update the address, buffer, and size and continue: */ 589: address_init += count; 590: buffer += count; 591: size -= count; 592: } 593: 594: return (err); 595: } 596: 597: /* the 32-bit big-endian bus master bus router: */ 598: const tme_bus_lane_t tme_bus_device_router_32eb[TME_BUS_ROUTER_INIT_SIZE(TME_BUS32_LOG2)] = { 599: 600: /* initiator maximum cycle size: 8 bits 601: initiator address offset: 0 bits 602: responder bus port size: 8 bits 603: responder port least lane: D7-D0: */ 604: /* D7-D0 */ TME_BUS_LANE_UNDEF, 605: /* D15-D8 */ TME_BUS_LANE_UNDEF, 606: /* D23-D16 */ TME_BUS_LANE_UNDEF, 607: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 608: 609: /* initiator maximum cycle size: 8 bits 610: initiator address offset: 0 bits 611: responder bus port size: 8 bits 612: responder port least lane: D15-D8: */ 613: /* D7-D0 */ TME_BUS_LANE_UNDEF, 614: /* D15-D8 */ TME_BUS_LANE_UNDEF, 615: /* D23-D16 */ TME_BUS_LANE_UNDEF, 616: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 617: 618: /* initiator maximum cycle size: 8 bits 619: initiator address offset: 0 bits 620: responder bus port size: 8 bits 621: responder port least lane: D23-D16: */ 622: /* D7-D0 */ TME_BUS_LANE_UNDEF, 623: /* D15-D8 */ TME_BUS_LANE_UNDEF, 624: /* D23-D16 */ TME_BUS_LANE_UNDEF, 625: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 626: 627: /* initiator maximum cycle size: 8 bits 628: initiator address offset: 0 bits 629: responder bus port size: 8 bits 630: responder port least lane: D31-D24: */ 631: /* D7-D0 */ TME_BUS_LANE_UNDEF, 632: /* D15-D8 */ TME_BUS_LANE_UNDEF, 633: /* D23-D16 */ TME_BUS_LANE_UNDEF, 634: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 635: 636: /* initiator maximum cycle size: 8 bits 637: initiator address offset: 0 bits 638: responder bus port size: 16 bits 639: responder port least lane: D7-D0: */ 640: /* D7-D0 */ TME_BUS_LANE_UNDEF, 641: /* D15-D8 */ TME_BUS_LANE_UNDEF, 642: /* D23-D16 */ TME_BUS_LANE_UNDEF, 643: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 644: 645: /* initiator maximum cycle size: 8 bits 646: initiator address offset: 0 bits 647: responder bus port size: 16 bits 648: responder port least lane: D15-D8: */ 649: /* D7-D0 */ TME_BUS_LANE_UNDEF, 650: /* D15-D8 */ TME_BUS_LANE_UNDEF, 651: /* D23-D16 */ TME_BUS_LANE_UNDEF, 652: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 653: 654: /* initiator maximum cycle size: 8 bits 655: initiator address offset: 0 bits 656: responder bus port size: 16 bits 657: responder port least lane: D23-D16: */ 658: /* D7-D0 */ TME_BUS_LANE_UNDEF, 659: /* D15-D8 */ TME_BUS_LANE_UNDEF, 660: /* D23-D16 */ TME_BUS_LANE_UNDEF, 661: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 662: 663: /* initiator maximum cycle size: 8 bits 664: initiator address offset: 0 bits 665: responder bus port size: 16 bits 666: responder port least lane: D31-D24 667: (responder port not correctly positioned for this initiator): */ 668: /* D7-D0 */ TME_BUS_LANE_UNDEF, 669: /* D15-D8 */ TME_BUS_LANE_UNDEF, 670: /* D23-D16 */ TME_BUS_LANE_UNDEF, 671: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 672: 673: /* initiator maximum cycle size: 8 bits 674: initiator address offset: 0 bits 675: responder bus port size: 32 bits 676: responder port least lane: D7-D0: */ 677: /* D7-D0 */ TME_BUS_LANE_UNDEF, 678: /* D15-D8 */ TME_BUS_LANE_UNDEF, 679: /* D23-D16 */ TME_BUS_LANE_UNDEF, 680: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 681: 682: /* initiator maximum cycle size: 8 bits 683: initiator address offset: 0 bits 684: responder bus port size: 32 bits 685: responder port least lane: D15-D8 686: (responder port not correctly positioned for this initiator): */ 687: /* D7-D0 */ TME_BUS_LANE_UNDEF, 688: /* D15-D8 */ TME_BUS_LANE_UNDEF, 689: /* D23-D16 */ TME_BUS_LANE_UNDEF, 690: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 691: 692: /* initiator maximum cycle size: 8 bits 693: initiator address offset: 0 bits 694: responder bus port size: 32 bits 695: responder port least lane: D23-D16 696: (responder port not correctly positioned for this initiator): */ 697: /* D7-D0 */ TME_BUS_LANE_UNDEF, 698: /* D15-D8 */ TME_BUS_LANE_UNDEF, 699: /* D23-D16 */ TME_BUS_LANE_UNDEF, 700: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 701: 702: /* initiator maximum cycle size: 8 bits 703: initiator address offset: 0 bits 704: responder bus port size: 32 bits 705: responder port least lane: D31-D24 706: (responder port not correctly positioned for this initiator): */ 707: /* D7-D0 */ TME_BUS_LANE_UNDEF, 708: /* D15-D8 */ TME_BUS_LANE_UNDEF, 709: /* D23-D16 */ TME_BUS_LANE_UNDEF, 710: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 711: 712: /* initiator maximum cycle size: 8 bits 713: initiator address offset: 8 bits 714: responder bus port size: 8 bits 715: responder port least lane: D7-D0: */ 716: /* D7-D0 */ TME_BUS_LANE_UNDEF, 717: /* D15-D8 */ TME_BUS_LANE_UNDEF, 718: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 719: /* D31-D24 */ TME_BUS_LANE_UNDEF, 720: 721: /* initiator maximum cycle size: 8 bits 722: initiator address offset: 8 bits 723: responder bus port size: 8 bits 724: responder port least lane: D15-D8: */ 725: /* D7-D0 */ TME_BUS_LANE_UNDEF, 726: /* D15-D8 */ TME_BUS_LANE_UNDEF, 727: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 728: /* D31-D24 */ TME_BUS_LANE_UNDEF, 729: 730: /* initiator maximum cycle size: 8 bits 731: initiator address offset: 8 bits 732: responder bus port size: 8 bits 733: responder port least lane: D23-D16: */ 734: /* D7-D0 */ TME_BUS_LANE_UNDEF, 735: /* D15-D8 */ TME_BUS_LANE_UNDEF, 736: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 737: /* D31-D24 */ TME_BUS_LANE_UNDEF, 738: 739: /* initiator maximum cycle size: 8 bits 740: initiator address offset: 8 bits 741: responder bus port size: 8 bits 742: responder port least lane: D31-D24: */ 743: /* D7-D0 */ TME_BUS_LANE_UNDEF, 744: /* D15-D8 */ TME_BUS_LANE_UNDEF, 745: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 746: /* D31-D24 */ TME_BUS_LANE_UNDEF, 747: 748: /* initiator maximum cycle size: 8 bits 749: initiator address offset: 8 bits 750: responder bus port size: 16 bits 751: responder port least lane: D7-D0: */ 752: /* D7-D0 */ TME_BUS_LANE_UNDEF, 753: /* D15-D8 */ TME_BUS_LANE_UNDEF, 754: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 755: /* D31-D24 */ TME_BUS_LANE_UNDEF, 756: 757: /* initiator maximum cycle size: 8 bits 758: initiator address offset: 8 bits 759: responder bus port size: 16 bits 760: responder port least lane: D15-D8: */ 761: /* D7-D0 */ TME_BUS_LANE_UNDEF, 762: /* D15-D8 */ TME_BUS_LANE_UNDEF, 763: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 764: /* D31-D24 */ TME_BUS_LANE_UNDEF, 765: 766: /* initiator maximum cycle size: 8 bits 767: initiator address offset: 8 bits 768: responder bus port size: 16 bits 769: responder port least lane: D23-D16: */ 770: /* D7-D0 */ TME_BUS_LANE_UNDEF, 771: /* D15-D8 */ TME_BUS_LANE_UNDEF, 772: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 773: /* D31-D24 */ TME_BUS_LANE_UNDEF, 774: 775: /* initiator maximum cycle size: 8 bits 776: initiator address offset: 8 bits 777: responder bus port size: 16 bits 778: responder port least lane: D31-D24 779: (responder port not correctly positioned for this initiator): */ 780: /* D7-D0 */ TME_BUS_LANE_UNDEF, 781: /* D15-D8 */ TME_BUS_LANE_UNDEF, 782: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 783: /* D31-D24 */ TME_BUS_LANE_UNDEF, 784: 785: /* initiator maximum cycle size: 8 bits 786: initiator address offset: 8 bits 787: responder bus port size: 32 bits 788: responder port least lane: D7-D0: */ 789: /* D7-D0 */ TME_BUS_LANE_UNDEF, 790: /* D15-D8 */ TME_BUS_LANE_UNDEF, 791: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 792: /* D31-D24 */ TME_BUS_LANE_UNDEF, 793: 794: /* initiator maximum cycle size: 8 bits 795: initiator address offset: 8 bits 796: responder bus port size: 32 bits 797: responder port least lane: D15-D8 798: (responder port not correctly positioned for this initiator): */ 799: /* D7-D0 */ TME_BUS_LANE_UNDEF, 800: /* D15-D8 */ TME_BUS_LANE_UNDEF, 801: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 802: /* D31-D24 */ TME_BUS_LANE_UNDEF, 803: 804: /* initiator maximum cycle size: 8 bits 805: initiator address offset: 8 bits 806: responder bus port size: 32 bits 807: responder port least lane: D23-D16 808: (responder port not correctly positioned for this initiator): */ 809: /* D7-D0 */ TME_BUS_LANE_UNDEF, 810: /* D15-D8 */ TME_BUS_LANE_UNDEF, 811: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 812: /* D31-D24 */ TME_BUS_LANE_UNDEF, 813: 814: /* initiator maximum cycle size: 8 bits 815: initiator address offset: 8 bits 816: responder bus port size: 32 bits 817: responder port least lane: D31-D24 818: (responder port not correctly positioned for this initiator): */ 819: /* D7-D0 */ TME_BUS_LANE_UNDEF, 820: /* D15-D8 */ TME_BUS_LANE_UNDEF, 821: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 822: /* D31-D24 */ TME_BUS_LANE_UNDEF, 823: 824: /* initiator maximum cycle size: 8 bits 825: initiator address offset: 16 bits 826: responder bus port size: 8 bits 827: responder port least lane: D7-D0: */ 828: /* D7-D0 */ TME_BUS_LANE_UNDEF, 829: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 830: /* D23-D16 */ TME_BUS_LANE_UNDEF, 831: /* D31-D24 */ TME_BUS_LANE_UNDEF, 832: 833: /* initiator maximum cycle size: 8 bits 834: initiator address offset: 16 bits 835: responder bus port size: 8 bits 836: responder port least lane: D15-D8: */ 837: /* D7-D0 */ TME_BUS_LANE_UNDEF, 838: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 839: /* D23-D16 */ TME_BUS_LANE_UNDEF, 840: /* D31-D24 */ TME_BUS_LANE_UNDEF, 841: 842: /* initiator maximum cycle size: 8 bits 843: initiator address offset: 16 bits 844: responder bus port size: 8 bits 845: responder port least lane: D23-D16: */ 846: /* D7-D0 */ TME_BUS_LANE_UNDEF, 847: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 848: /* D23-D16 */ TME_BUS_LANE_UNDEF, 849: /* D31-D24 */ TME_BUS_LANE_UNDEF, 850: 851: /* initiator maximum cycle size: 8 bits 852: initiator address offset: 16 bits 853: responder bus port size: 8 bits 854: responder port least lane: D31-D24: */ 855: /* D7-D0 */ TME_BUS_LANE_UNDEF, 856: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 857: /* D23-D16 */ TME_BUS_LANE_UNDEF, 858: /* D31-D24 */ TME_BUS_LANE_UNDEF, 859: 860: /* initiator maximum cycle size: 8 bits 861: initiator address offset: 16 bits 862: responder bus port size: 16 bits 863: responder port least lane: D7-D0: */ 864: /* D7-D0 */ TME_BUS_LANE_UNDEF, 865: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 866: /* D23-D16 */ TME_BUS_LANE_UNDEF, 867: /* D31-D24 */ TME_BUS_LANE_UNDEF, 868: 869: /* initiator maximum cycle size: 8 bits 870: initiator address offset: 16 bits 871: responder bus port size: 16 bits 872: responder port least lane: D15-D8: */ 873: /* D7-D0 */ TME_BUS_LANE_UNDEF, 874: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 875: /* D23-D16 */ TME_BUS_LANE_UNDEF, 876: /* D31-D24 */ TME_BUS_LANE_UNDEF, 877: 878: /* initiator maximum cycle size: 8 bits 879: initiator address offset: 16 bits 880: responder bus port size: 16 bits 881: responder port least lane: D23-D16: */ 882: /* D7-D0 */ TME_BUS_LANE_UNDEF, 883: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 884: /* D23-D16 */ TME_BUS_LANE_UNDEF, 885: /* D31-D24 */ TME_BUS_LANE_UNDEF, 886: 887: /* initiator maximum cycle size: 8 bits 888: initiator address offset: 16 bits 889: responder bus port size: 16 bits 890: responder port least lane: D31-D24 891: (responder port not correctly positioned for this initiator): */ 892: /* D7-D0 */ TME_BUS_LANE_UNDEF, 893: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 894: /* D23-D16 */ TME_BUS_LANE_UNDEF, 895: /* D31-D24 */ TME_BUS_LANE_UNDEF, 896: 897: /* initiator maximum cycle size: 8 bits 898: initiator address offset: 16 bits 899: responder bus port size: 32 bits 900: responder port least lane: D7-D0: */ 901: /* D7-D0 */ TME_BUS_LANE_UNDEF, 902: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 903: /* D23-D16 */ TME_BUS_LANE_UNDEF, 904: /* D31-D24 */ TME_BUS_LANE_UNDEF, 905: 906: /* initiator maximum cycle size: 8 bits 907: initiator address offset: 16 bits 908: responder bus port size: 32 bits 909: responder port least lane: D15-D8 910: (responder port not correctly positioned for this initiator): */ 911: /* D7-D0 */ TME_BUS_LANE_UNDEF, 912: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 913: /* D23-D16 */ TME_BUS_LANE_UNDEF, 914: /* D31-D24 */ TME_BUS_LANE_UNDEF, 915: 916: /* initiator maximum cycle size: 8 bits 917: initiator address offset: 16 bits 918: responder bus port size: 32 bits 919: responder port least lane: D23-D16 920: (responder port not correctly positioned for this initiator): */ 921: /* D7-D0 */ TME_BUS_LANE_UNDEF, 922: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 923: /* D23-D16 */ TME_BUS_LANE_UNDEF, 924: /* D31-D24 */ TME_BUS_LANE_UNDEF, 925: 926: /* initiator maximum cycle size: 8 bits 927: initiator address offset: 16 bits 928: responder bus port size: 32 bits 929: responder port least lane: D31-D24 930: (responder port not correctly positioned for this initiator): */ 931: /* D7-D0 */ TME_BUS_LANE_UNDEF, 932: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 933: /* D23-D16 */ TME_BUS_LANE_UNDEF, 934: /* D31-D24 */ TME_BUS_LANE_UNDEF, 935: 936: /* initiator maximum cycle size: 8 bits 937: initiator address offset: 24 bits 938: responder bus port size: 8 bits 939: responder port least lane: D7-D0: */ 940: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 941: /* D15-D8 */ TME_BUS_LANE_UNDEF, 942: /* D23-D16 */ TME_BUS_LANE_UNDEF, 943: /* D31-D24 */ TME_BUS_LANE_UNDEF, 944: 945: /* initiator maximum cycle size: 8 bits 946: initiator address offset: 24 bits 947: responder bus port size: 8 bits 948: responder port least lane: D15-D8: */ 949: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 950: /* D15-D8 */ TME_BUS_LANE_UNDEF, 951: /* D23-D16 */ TME_BUS_LANE_UNDEF, 952: /* D31-D24 */ TME_BUS_LANE_UNDEF, 953: 954: /* initiator maximum cycle size: 8 bits 955: initiator address offset: 24 bits 956: responder bus port size: 8 bits 957: responder port least lane: D23-D16: */ 958: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 959: /* D15-D8 */ TME_BUS_LANE_UNDEF, 960: /* D23-D16 */ TME_BUS_LANE_UNDEF, 961: /* D31-D24 */ TME_BUS_LANE_UNDEF, 962: 963: /* initiator maximum cycle size: 8 bits 964: initiator address offset: 24 bits 965: responder bus port size: 8 bits 966: responder port least lane: D31-D24: */ 967: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 968: /* D15-D8 */ TME_BUS_LANE_UNDEF, 969: /* D23-D16 */ TME_BUS_LANE_UNDEF, 970: /* D31-D24 */ TME_BUS_LANE_UNDEF, 971: 972: /* initiator maximum cycle size: 8 bits 973: initiator address offset: 24 bits 974: responder bus port size: 16 bits 975: responder port least lane: D7-D0: */ 976: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 977: /* D15-D8 */ TME_BUS_LANE_UNDEF, 978: /* D23-D16 */ TME_BUS_LANE_UNDEF, 979: /* D31-D24 */ TME_BUS_LANE_UNDEF, 980: 981: /* initiator maximum cycle size: 8 bits 982: initiator address offset: 24 bits 983: responder bus port size: 16 bits 984: responder port least lane: D15-D8: */ 985: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 986: /* D15-D8 */ TME_BUS_LANE_UNDEF, 987: /* D23-D16 */ TME_BUS_LANE_UNDEF, 988: /* D31-D24 */ TME_BUS_LANE_UNDEF, 989: 990: /* initiator maximum cycle size: 8 bits 991: initiator address offset: 24 bits 992: responder bus port size: 16 bits 993: responder port least lane: D23-D16: */ 994: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 995: /* D15-D8 */ TME_BUS_LANE_UNDEF, 996: /* D23-D16 */ TME_BUS_LANE_UNDEF, 997: /* D31-D24 */ TME_BUS_LANE_UNDEF, 998: 999: /* initiator maximum cycle size: 8 bits 1000: initiator address offset: 24 bits 1001: responder bus port size: 16 bits 1002: responder port least lane: D31-D24 1003: (responder port not correctly positioned for this initiator): */ 1004: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1005: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1006: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1007: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1008: 1009: /* initiator maximum cycle size: 8 bits 1010: initiator address offset: 24 bits 1011: responder bus port size: 32 bits 1012: responder port least lane: D7-D0: */ 1013: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 1014: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1015: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1016: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1017: 1018: /* initiator maximum cycle size: 8 bits 1019: initiator address offset: 24 bits 1020: responder bus port size: 32 bits 1021: responder port least lane: D15-D8 1022: (responder port not correctly positioned for this initiator): */ 1023: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1024: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1025: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1026: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1027: 1028: /* initiator maximum cycle size: 8 bits 1029: initiator address offset: 24 bits 1030: responder bus port size: 32 bits 1031: responder port least lane: D23-D16 1032: (responder port not correctly positioned for this initiator): */ 1033: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1034: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1035: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1036: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1037: 1038: /* initiator maximum cycle size: 8 bits 1039: initiator address offset: 24 bits 1040: responder bus port size: 32 bits 1041: responder port least lane: D31-D24 1042: (responder port not correctly positioned for this initiator): */ 1043: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1044: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1045: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1046: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1047: 1048: /* initiator maximum cycle size: 16 bits 1049: initiator address offset: 0 bits 1050: responder bus port size: 8 bits 1051: responder port least lane: D7-D0: */ 1052: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1053: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1054: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1055: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1056: 1057: /* initiator maximum cycle size: 16 bits 1058: initiator address offset: 0 bits 1059: responder bus port size: 8 bits 1060: responder port least lane: D15-D8: */ 1061: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1062: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1063: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1064: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1065: 1066: /* initiator maximum cycle size: 16 bits 1067: initiator address offset: 0 bits 1068: responder bus port size: 8 bits 1069: responder port least lane: D23-D16: */ 1070: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1071: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1072: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 1073: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1074: 1075: /* initiator maximum cycle size: 16 bits 1076: initiator address offset: 0 bits 1077: responder bus port size: 8 bits 1078: responder port least lane: D31-D24: */ 1079: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1080: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1081: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1082: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 1083: 1084: /* initiator maximum cycle size: 16 bits 1085: initiator address offset: 0 bits 1086: responder bus port size: 16 bits 1087: responder port least lane: D7-D0: */ 1088: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1089: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1090: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1091: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1092: 1093: /* initiator maximum cycle size: 16 bits 1094: initiator address offset: 0 bits 1095: responder bus port size: 16 bits 1096: responder port least lane: D15-D8: */ 1097: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1098: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1099: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 1100: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1101: 1102: /* initiator maximum cycle size: 16 bits 1103: initiator address offset: 0 bits 1104: responder bus port size: 16 bits 1105: responder port least lane: D23-D16: */ 1106: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1107: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1108: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 1109: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 1110: 1111: /* initiator maximum cycle size: 16 bits 1112: initiator address offset: 0 bits 1113: responder bus port size: 16 bits 1114: responder port least lane: D31-D24 1115: (responder port not correctly positioned for this initiator): */ 1116: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1117: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1118: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1119: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 1120: 1121: /* initiator maximum cycle size: 16 bits 1122: initiator address offset: 0 bits 1123: responder bus port size: 32 bits 1124: responder port least lane: D7-D0: */ 1125: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1126: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1127: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 1128: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 1129: 1130: /* initiator maximum cycle size: 16 bits 1131: initiator address offset: 0 bits 1132: responder bus port size: 32 bits 1133: responder port least lane: D15-D8 1134: (responder port not correctly positioned for this initiator): */ 1135: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1136: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1137: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 1138: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 1139: 1140: /* initiator maximum cycle size: 16 bits 1141: initiator address offset: 0 bits 1142: responder bus port size: 32 bits 1143: responder port least lane: D23-D16 1144: (responder port not correctly positioned for this initiator): */ 1145: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1146: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1147: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 1148: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 1149: 1150: /* initiator maximum cycle size: 16 bits 1151: initiator address offset: 0 bits 1152: responder bus port size: 32 bits 1153: responder port least lane: D31-D24 1154: (responder port not correctly positioned for this initiator): */ 1155: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1156: /* D15-D8 */ TME_BUS_LANE_UNDEF, 1157: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1158: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 1159: 1160: /* initiator maximum cycle size: 16 bits 1161: initiator address offset: 8 bits 1162: responder bus port size: 8 bits 1163: responder port least lane: D7-D0: */ 1164: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1165: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1166: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1167: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1168: 1169: /* initiator maximum cycle size: 16 bits 1170: initiator address offset: 8 bits 1171: responder bus port size: 8 bits 1172: responder port least lane: D15-D8: */ 1173: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1174: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 1175: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1176: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1177: 1178: /* initiator maximum cycle size: 16 bits 1179: initiator address offset: 8 bits 1180: responder bus port size: 8 bits 1181: responder port least lane: D23-D16: */ 1182: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1183: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1184: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 1185: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1186: 1187: /* initiator maximum cycle size: 16 bits 1188: initiator address offset: 8 bits 1189: responder bus port size: 8 bits 1190: responder port least lane: D31-D24: */ 1191: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1192: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1193: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1194: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1195: 1196: /* initiator maximum cycle size: 16 bits 1197: initiator address offset: 8 bits 1198: responder bus port size: 16 bits 1199: responder port least lane: D7-D0: */ 1200: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1201: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 1202: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1203: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1204: 1205: /* initiator maximum cycle size: 16 bits 1206: initiator address offset: 8 bits 1207: responder bus port size: 16 bits 1208: responder port least lane: D15-D8: */ 1209: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1210: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 1211: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 1212: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1213: 1214: /* initiator maximum cycle size: 16 bits 1215: initiator address offset: 8 bits 1216: responder bus port size: 16 bits 1217: responder port least lane: D23-D16: */ 1218: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1219: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1220: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 1221: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1222: 1223: /* initiator maximum cycle size: 16 bits 1224: initiator address offset: 8 bits 1225: responder bus port size: 16 bits 1226: responder port least lane: D31-D24 1227: (responder port not correctly positioned for this initiator): */ 1228: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1229: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1230: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1231: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1232: 1233: /* initiator maximum cycle size: 16 bits 1234: initiator address offset: 8 bits 1235: responder bus port size: 32 bits 1236: responder port least lane: D7-D0: */ 1237: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1238: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 1239: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 1240: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1241: 1242: /* initiator maximum cycle size: 16 bits 1243: initiator address offset: 8 bits 1244: responder bus port size: 32 bits 1245: responder port least lane: D15-D8 1246: (responder port not correctly positioned for this initiator): */ 1247: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1248: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 1249: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 1250: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1251: 1252: /* initiator maximum cycle size: 16 bits 1253: initiator address offset: 8 bits 1254: responder bus port size: 32 bits 1255: responder port least lane: D23-D16 1256: (responder port not correctly positioned for this initiator): */ 1257: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1258: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1259: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 1260: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1261: 1262: /* initiator maximum cycle size: 16 bits 1263: initiator address offset: 8 bits 1264: responder bus port size: 32 bits 1265: responder port least lane: D31-D24 1266: (responder port not correctly positioned for this initiator): */ 1267: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1268: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1269: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1270: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1271: 1272: /* initiator maximum cycle size: 16 bits 1273: initiator address offset: 16 bits 1274: responder bus port size: 8 bits 1275: responder port least lane: D7-D0: */ 1276: /* D7-D0 */ TME_BUS_LANE_ROUTE(1), 1277: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1278: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1279: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1280: 1281: /* initiator maximum cycle size: 16 bits 1282: initiator address offset: 16 bits 1283: responder bus port size: 8 bits 1284: responder port least lane: D15-D8: */ 1285: /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1286: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 1287: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1288: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1289: 1290: /* initiator maximum cycle size: 16 bits 1291: initiator address offset: 16 bits 1292: responder bus port size: 8 bits 1293: responder port least lane: D23-D16: */ 1294: /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1295: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1296: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1297: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1298: 1299: /* initiator maximum cycle size: 16 bits 1300: initiator address offset: 16 bits 1301: responder bus port size: 8 bits 1302: responder port least lane: D31-D24: */ 1303: /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1304: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1305: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1306: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1307: 1308: /* initiator maximum cycle size: 16 bits 1309: initiator address offset: 16 bits 1310: responder bus port size: 16 bits 1311: responder port least lane: D7-D0: */ 1312: /* D7-D0 */ TME_BUS_LANE_ROUTE(1), 1313: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 1314: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1315: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1316: 1317: /* initiator maximum cycle size: 16 bits 1318: initiator address offset: 16 bits 1319: responder bus port size: 16 bits 1320: responder port least lane: D15-D8: */ 1321: /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1322: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 1323: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1324: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1325: 1326: /* initiator maximum cycle size: 16 bits 1327: initiator address offset: 16 bits 1328: responder bus port size: 16 bits 1329: responder port least lane: D23-D16: */ 1330: /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1331: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1332: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1333: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1334: 1335: /* initiator maximum cycle size: 16 bits 1336: initiator address offset: 16 bits 1337: responder bus port size: 16 bits 1338: responder port least lane: D31-D24 1339: (responder port not correctly positioned for this initiator): */ 1340: /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1341: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1342: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1343: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1344: 1345: /* initiator maximum cycle size: 16 bits 1346: initiator address offset: 16 bits 1347: responder bus port size: 32 bits 1348: responder port least lane: D7-D0: */ 1349: /* D7-D0 */ TME_BUS_LANE_ROUTE(1), 1350: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 1351: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1352: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1353: 1354: /* initiator maximum cycle size: 16 bits 1355: initiator address offset: 16 bits 1356: responder bus port size: 32 bits 1357: responder port least lane: D15-D8 1358: (responder port not correctly positioned for this initiator): */ 1359: /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1360: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 1361: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1362: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1363: 1364: /* initiator maximum cycle size: 16 bits 1365: initiator address offset: 16 bits 1366: responder bus port size: 32 bits 1367: responder port least lane: D23-D16 1368: (responder port not correctly positioned for this initiator): */ 1369: /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1370: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1371: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1372: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1373: 1374: /* initiator maximum cycle size: 16 bits 1375: initiator address offset: 16 bits 1376: responder bus port size: 32 bits 1377: responder port least lane: D31-D24 1378: (responder port not correctly positioned for this initiator): */ 1379: /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1380: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1381: /* D23-D16 */ TME_BUS_LANE_UNDEF, 1382: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1383: 1384: /* initiator maximum cycle size: 16 bits 1385: initiator address offset: 24 bits 1386: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 1387: responder bus port size: 8 bits 1388: responder port least lane: D7-D0: */ 1389: /* D7-D0 */ TME_BUS_LANE_ABORT, 1390: /* D15-D8 */ TME_BUS_LANE_ABORT, 1391: /* D23-D16 */ TME_BUS_LANE_ABORT, 1392: /* D31-D24 */ TME_BUS_LANE_ABORT, 1393: 1394: /* initiator maximum cycle size: 16 bits 1395: initiator address offset: 24 bits 1396: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 1397: responder bus port size: 8 bits 1398: responder port least lane: D15-D8: */ 1399: /* D7-D0 */ TME_BUS_LANE_ABORT, 1400: /* D15-D8 */ TME_BUS_LANE_ABORT, 1401: /* D23-D16 */ TME_BUS_LANE_ABORT, 1402: /* D31-D24 */ TME_BUS_LANE_ABORT, 1403: 1404: /* initiator maximum cycle size: 16 bits 1405: initiator address offset: 24 bits 1406: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 1407: responder bus port size: 8 bits 1408: responder port least lane: D23-D16: */ 1409: /* D7-D0 */ TME_BUS_LANE_ABORT, 1410: /* D15-D8 */ TME_BUS_LANE_ABORT, 1411: /* D23-D16 */ TME_BUS_LANE_ABORT, 1412: /* D31-D24 */ TME_BUS_LANE_ABORT, 1413: 1414: /* initiator maximum cycle size: 16 bits 1415: initiator address offset: 24 bits 1416: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 1417: responder bus port size: 8 bits 1418: responder port least lane: D31-D24: */ 1419: /* D7-D0 */ TME_BUS_LANE_ABORT, 1420: /* D15-D8 */ TME_BUS_LANE_ABORT, 1421: /* D23-D16 */ TME_BUS_LANE_ABORT, 1422: /* D31-D24 */ TME_BUS_LANE_ABORT, 1423: 1424: /* initiator maximum cycle size: 16 bits 1425: initiator address offset: 24 bits 1426: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 1427: responder bus port size: 16 bits 1428: responder port least lane: D7-D0: */ 1429: /* D7-D0 */ TME_BUS_LANE_ABORT, 1430: /* D15-D8 */ TME_BUS_LANE_ABORT, 1431: /* D23-D16 */ TME_BUS_LANE_ABORT, 1432: /* D31-D24 */ TME_BUS_LANE_ABORT, 1433: 1434: /* initiator maximum cycle size: 16 bits 1435: initiator address offset: 24 bits 1436: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 1437: responder bus port size: 16 bits 1438: responder port least lane: D15-D8: */ 1439: /* D7-D0 */ TME_BUS_LANE_ABORT, 1440: /* D15-D8 */ TME_BUS_LANE_ABORT, 1441: /* D23-D16 */ TME_BUS_LANE_ABORT, 1442: /* D31-D24 */ TME_BUS_LANE_ABORT, 1443: 1444: /* initiator maximum cycle size: 16 bits 1445: initiator address offset: 24 bits 1446: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 1447: responder bus port size: 16 bits 1448: responder port least lane: D23-D16: */ 1449: /* D7-D0 */ TME_BUS_LANE_ABORT, 1450: /* D15-D8 */ TME_BUS_LANE_ABORT, 1451: /* D23-D16 */ TME_BUS_LANE_ABORT, 1452: /* D31-D24 */ TME_BUS_LANE_ABORT, 1453: 1454: /* initiator maximum cycle size: 16 bits 1455: initiator address offset: 24 bits 1456: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 1457: responder bus port size: 16 bits 1458: responder port least lane: D31-D24 1459: (responder port not correctly positioned for this initiator): */ 1460: /* D7-D0 */ TME_BUS_LANE_ABORT, 1461: /* D15-D8 */ TME_BUS_LANE_ABORT, 1462: /* D23-D16 */ TME_BUS_LANE_ABORT, 1463: /* D31-D24 */ TME_BUS_LANE_ABORT, 1464: 1465: /* initiator maximum cycle size: 16 bits 1466: initiator address offset: 24 bits 1467: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 1468: responder bus port size: 32 bits 1469: responder port least lane: D7-D0: */ 1470: /* D7-D0 */ TME_BUS_LANE_ABORT, 1471: /* D15-D8 */ TME_BUS_LANE_ABORT, 1472: /* D23-D16 */ TME_BUS_LANE_ABORT, 1473: /* D31-D24 */ TME_BUS_LANE_ABORT, 1474: 1475: /* initiator maximum cycle size: 16 bits 1476: initiator address offset: 24 bits 1477: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 1478: responder bus port size: 32 bits 1479: responder port least lane: D15-D8 1480: (responder port not correctly positioned for this initiator): */ 1481: /* D7-D0 */ TME_BUS_LANE_ABORT, 1482: /* D15-D8 */ TME_BUS_LANE_ABORT, 1483: /* D23-D16 */ TME_BUS_LANE_ABORT, 1484: /* D31-D24 */ TME_BUS_LANE_ABORT, 1485: 1486: /* initiator maximum cycle size: 16 bits 1487: initiator address offset: 24 bits 1488: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 1489: responder bus port size: 32 bits 1490: responder port least lane: D23-D16 1491: (responder port not correctly positioned for this initiator): */ 1492: /* D7-D0 */ TME_BUS_LANE_ABORT, 1493: /* D15-D8 */ TME_BUS_LANE_ABORT, 1494: /* D23-D16 */ TME_BUS_LANE_ABORT, 1495: /* D31-D24 */ TME_BUS_LANE_ABORT, 1496: 1497: /* initiator maximum cycle size: 16 bits 1498: initiator address offset: 24 bits 1499: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 1500: responder bus port size: 32 bits 1501: responder port least lane: D31-D24 1502: (responder port not correctly positioned for this initiator): */ 1503: /* D7-D0 */ TME_BUS_LANE_ABORT, 1504: /* D15-D8 */ TME_BUS_LANE_ABORT, 1505: /* D23-D16 */ TME_BUS_LANE_ABORT, 1506: /* D31-D24 */ TME_BUS_LANE_ABORT, 1507: 1508: /* initiator maximum cycle size: 24 bits 1509: initiator address offset: 0 bits 1510: responder bus port size: 8 bits 1511: responder port least lane: D7-D0: */ 1512: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1513: /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1514: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1515: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1516: 1517: /* initiator maximum cycle size: 24 bits 1518: initiator address offset: 0 bits 1519: responder bus port size: 8 bits 1520: responder port least lane: D15-D8: */ 1521: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1522: /* D15-D8 */ TME_BUS_LANE_ROUTE(2), 1523: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1524: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1525: 1526: /* initiator maximum cycle size: 24 bits 1527: initiator address offset: 0 bits 1528: responder bus port size: 8 bits 1529: responder port least lane: D23-D16: */ 1530: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1531: /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1532: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 1533: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1534: 1535: /* initiator maximum cycle size: 24 bits 1536: initiator address offset: 0 bits 1537: responder bus port size: 8 bits 1538: responder port least lane: D31-D24: */ 1539: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1540: /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1541: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1542: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 1543: 1544: /* initiator maximum cycle size: 24 bits 1545: initiator address offset: 0 bits 1546: responder bus port size: 16 bits 1547: responder port least lane: D7-D0: */ 1548: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1549: /* D15-D8 */ TME_BUS_LANE_ROUTE(2), 1550: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1551: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1552: 1553: /* initiator maximum cycle size: 24 bits 1554: initiator address offset: 0 bits 1555: responder bus port size: 16 bits 1556: responder port least lane: D15-D8: */ 1557: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1558: /* D15-D8 */ TME_BUS_LANE_ROUTE(2), 1559: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 1560: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1561: 1562: /* initiator maximum cycle size: 24 bits 1563: initiator address offset: 0 bits 1564: responder bus port size: 16 bits 1565: responder port least lane: D23-D16: */ 1566: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1567: /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1568: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 1569: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 1570: 1571: /* initiator maximum cycle size: 24 bits 1572: initiator address offset: 0 bits 1573: responder bus port size: 16 bits 1574: responder port least lane: D31-D24 1575: (responder port not correctly positioned for this initiator): */ 1576: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1577: /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1578: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1579: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 1580: 1581: /* initiator maximum cycle size: 24 bits 1582: initiator address offset: 0 bits 1583: responder bus port size: 32 bits 1584: responder port least lane: D7-D0: */ 1585: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1586: /* D15-D8 */ TME_BUS_LANE_ROUTE(2), 1587: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 1588: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 1589: 1590: /* initiator maximum cycle size: 24 bits 1591: initiator address offset: 0 bits 1592: responder bus port size: 32 bits 1593: responder port least lane: D15-D8 1594: (responder port not correctly positioned for this initiator): */ 1595: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1596: /* D15-D8 */ TME_BUS_LANE_ROUTE(2), 1597: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 1598: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 1599: 1600: /* initiator maximum cycle size: 24 bits 1601: initiator address offset: 0 bits 1602: responder bus port size: 32 bits 1603: responder port least lane: D23-D16 1604: (responder port not correctly positioned for this initiator): */ 1605: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1606: /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1607: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 1608: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 1609: 1610: /* initiator maximum cycle size: 24 bits 1611: initiator address offset: 0 bits 1612: responder bus port size: 32 bits 1613: responder port least lane: D31-D24 1614: (responder port not correctly positioned for this initiator): */ 1615: /* D7-D0 */ TME_BUS_LANE_UNDEF, 1616: /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1617: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1618: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 1619: 1620: /* initiator maximum cycle size: 24 bits 1621: initiator address offset: 8 bits 1622: responder bus port size: 8 bits 1623: responder port least lane: D7-D0: */ 1624: /* D7-D0 */ TME_BUS_LANE_ROUTE(2), 1625: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1626: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1627: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1628: 1629: /* initiator maximum cycle size: 24 bits 1630: initiator address offset: 8 bits 1631: responder bus port size: 8 bits 1632: responder port least lane: D15-D8: */ 1633: /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1634: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 1635: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1636: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1637: 1638: /* initiator maximum cycle size: 24 bits 1639: initiator address offset: 8 bits 1640: responder bus port size: 8 bits 1641: responder port least lane: D23-D16: */ 1642: /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1643: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1644: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 1645: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1646: 1647: /* initiator maximum cycle size: 24 bits 1648: initiator address offset: 8 bits 1649: responder bus port size: 8 bits 1650: responder port least lane: D31-D24: */ 1651: /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1652: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1653: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1654: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1655: 1656: /* initiator maximum cycle size: 24 bits 1657: initiator address offset: 8 bits 1658: responder bus port size: 16 bits 1659: responder port least lane: D7-D0: */ 1660: /* D7-D0 */ TME_BUS_LANE_ROUTE(2), 1661: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 1662: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1663: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1664: 1665: /* initiator maximum cycle size: 24 bits 1666: initiator address offset: 8 bits 1667: responder bus port size: 16 bits 1668: responder port least lane: D15-D8: */ 1669: /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1670: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 1671: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 1672: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1673: 1674: /* initiator maximum cycle size: 24 bits 1675: initiator address offset: 8 bits 1676: responder bus port size: 16 bits 1677: responder port least lane: D23-D16: */ 1678: /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1679: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1680: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 1681: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1682: 1683: /* initiator maximum cycle size: 24 bits 1684: initiator address offset: 8 bits 1685: responder bus port size: 16 bits 1686: responder port least lane: D31-D24 1687: (responder port not correctly positioned for this initiator): */ 1688: /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1689: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1690: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1691: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1692: 1693: /* initiator maximum cycle size: 24 bits 1694: initiator address offset: 8 bits 1695: responder bus port size: 32 bits 1696: responder port least lane: D7-D0: */ 1697: /* D7-D0 */ TME_BUS_LANE_ROUTE(2), 1698: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 1699: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 1700: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1701: 1702: /* initiator maximum cycle size: 24 bits 1703: initiator address offset: 8 bits 1704: responder bus port size: 32 bits 1705: responder port least lane: D15-D8 1706: (responder port not correctly positioned for this initiator): */ 1707: /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1708: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 1709: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 1710: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1711: 1712: /* initiator maximum cycle size: 24 bits 1713: initiator address offset: 8 bits 1714: responder bus port size: 32 bits 1715: responder port least lane: D23-D16 1716: (responder port not correctly positioned for this initiator): */ 1717: /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1718: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1719: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 1720: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1721: 1722: /* initiator maximum cycle size: 24 bits 1723: initiator address offset: 8 bits 1724: responder bus port size: 32 bits 1725: responder port least lane: D31-D24 1726: (responder port not correctly positioned for this initiator): */ 1727: /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1728: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1729: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1730: /* D31-D24 */ TME_BUS_LANE_UNDEF, 1731: 1732: /* initiator maximum cycle size: 24 bits 1733: initiator address offset: 16 bits 1734: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 1735: responder bus port size: 8 bits 1736: responder port least lane: D7-D0: */ 1737: /* D7-D0 */ TME_BUS_LANE_ABORT, 1738: /* D15-D8 */ TME_BUS_LANE_ABORT, 1739: /* D23-D16 */ TME_BUS_LANE_ABORT, 1740: /* D31-D24 */ TME_BUS_LANE_ABORT, 1741: 1742: /* initiator maximum cycle size: 24 bits 1743: initiator address offset: 16 bits 1744: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 1745: responder bus port size: 8 bits 1746: responder port least lane: D15-D8: */ 1747: /* D7-D0 */ TME_BUS_LANE_ABORT, 1748: /* D15-D8 */ TME_BUS_LANE_ABORT, 1749: /* D23-D16 */ TME_BUS_LANE_ABORT, 1750: /* D31-D24 */ TME_BUS_LANE_ABORT, 1751: 1752: /* initiator maximum cycle size: 24 bits 1753: initiator address offset: 16 bits 1754: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 1755: responder bus port size: 8 bits 1756: responder port least lane: D23-D16: */ 1757: /* D7-D0 */ TME_BUS_LANE_ABORT, 1758: /* D15-D8 */ TME_BUS_LANE_ABORT, 1759: /* D23-D16 */ TME_BUS_LANE_ABORT, 1760: /* D31-D24 */ TME_BUS_LANE_ABORT, 1761: 1762: /* initiator maximum cycle size: 24 bits 1763: initiator address offset: 16 bits 1764: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 1765: responder bus port size: 8 bits 1766: responder port least lane: D31-D24: */ 1767: /* D7-D0 */ TME_BUS_LANE_ABORT, 1768: /* D15-D8 */ TME_BUS_LANE_ABORT, 1769: /* D23-D16 */ TME_BUS_LANE_ABORT, 1770: /* D31-D24 */ TME_BUS_LANE_ABORT, 1771: 1772: /* initiator maximum cycle size: 24 bits 1773: initiator address offset: 16 bits 1774: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 1775: responder bus port size: 16 bits 1776: responder port least lane: D7-D0: */ 1777: /* D7-D0 */ TME_BUS_LANE_ABORT, 1778: /* D15-D8 */ TME_BUS_LANE_ABORT, 1779: /* D23-D16 */ TME_BUS_LANE_ABORT, 1780: /* D31-D24 */ TME_BUS_LANE_ABORT, 1781: 1782: /* initiator maximum cycle size: 24 bits 1783: initiator address offset: 16 bits 1784: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 1785: responder bus port size: 16 bits 1786: responder port least lane: D15-D8: */ 1787: /* D7-D0 */ TME_BUS_LANE_ABORT, 1788: /* D15-D8 */ TME_BUS_LANE_ABORT, 1789: /* D23-D16 */ TME_BUS_LANE_ABORT, 1790: /* D31-D24 */ TME_BUS_LANE_ABORT, 1791: 1792: /* initiator maximum cycle size: 24 bits 1793: initiator address offset: 16 bits 1794: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 1795: responder bus port size: 16 bits 1796: responder port least lane: D23-D16: */ 1797: /* D7-D0 */ TME_BUS_LANE_ABORT, 1798: /* D15-D8 */ TME_BUS_LANE_ABORT, 1799: /* D23-D16 */ TME_BUS_LANE_ABORT, 1800: /* D31-D24 */ TME_BUS_LANE_ABORT, 1801: 1802: /* initiator maximum cycle size: 24 bits 1803: initiator address offset: 16 bits 1804: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 1805: responder bus port size: 16 bits 1806: responder port least lane: D31-D24 1807: (responder port not correctly positioned for this initiator): */ 1808: /* D7-D0 */ TME_BUS_LANE_ABORT, 1809: /* D15-D8 */ TME_BUS_LANE_ABORT, 1810: /* D23-D16 */ TME_BUS_LANE_ABORT, 1811: /* D31-D24 */ TME_BUS_LANE_ABORT, 1812: 1813: /* initiator maximum cycle size: 24 bits 1814: initiator address offset: 16 bits 1815: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 1816: responder bus port size: 32 bits 1817: responder port least lane: D7-D0: */ 1818: /* D7-D0 */ TME_BUS_LANE_ABORT, 1819: /* D15-D8 */ TME_BUS_LANE_ABORT, 1820: /* D23-D16 */ TME_BUS_LANE_ABORT, 1821: /* D31-D24 */ TME_BUS_LANE_ABORT, 1822: 1823: /* initiator maximum cycle size: 24 bits 1824: initiator address offset: 16 bits 1825: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 1826: responder bus port size: 32 bits 1827: responder port least lane: D15-D8 1828: (responder port not correctly positioned for this initiator): */ 1829: /* D7-D0 */ TME_BUS_LANE_ABORT, 1830: /* D15-D8 */ TME_BUS_LANE_ABORT, 1831: /* D23-D16 */ TME_BUS_LANE_ABORT, 1832: /* D31-D24 */ TME_BUS_LANE_ABORT, 1833: 1834: /* initiator maximum cycle size: 24 bits 1835: initiator address offset: 16 bits 1836: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 1837: responder bus port size: 32 bits 1838: responder port least lane: D23-D16 1839: (responder port not correctly positioned for this initiator): */ 1840: /* D7-D0 */ TME_BUS_LANE_ABORT, 1841: /* D15-D8 */ TME_BUS_LANE_ABORT, 1842: /* D23-D16 */ TME_BUS_LANE_ABORT, 1843: /* D31-D24 */ TME_BUS_LANE_ABORT, 1844: 1845: /* initiator maximum cycle size: 24 bits 1846: initiator address offset: 16 bits 1847: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 1848: responder bus port size: 32 bits 1849: responder port least lane: D31-D24 1850: (responder port not correctly positioned for this initiator): */ 1851: /* D7-D0 */ TME_BUS_LANE_ABORT, 1852: /* D15-D8 */ TME_BUS_LANE_ABORT, 1853: /* D23-D16 */ TME_BUS_LANE_ABORT, 1854: /* D31-D24 */ TME_BUS_LANE_ABORT, 1855: 1856: /* initiator maximum cycle size: 24 bits 1857: initiator address offset: 24 bits 1858: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 1859: responder bus port size: 8 bits 1860: responder port least lane: D7-D0: */ 1861: /* D7-D0 */ TME_BUS_LANE_ABORT, 1862: /* D15-D8 */ TME_BUS_LANE_ABORT, 1863: /* D23-D16 */ TME_BUS_LANE_ABORT, 1864: /* D31-D24 */ TME_BUS_LANE_ABORT, 1865: 1866: /* initiator maximum cycle size: 24 bits 1867: initiator address offset: 24 bits 1868: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 1869: responder bus port size: 8 bits 1870: responder port least lane: D15-D8: */ 1871: /* D7-D0 */ TME_BUS_LANE_ABORT, 1872: /* D15-D8 */ TME_BUS_LANE_ABORT, 1873: /* D23-D16 */ TME_BUS_LANE_ABORT, 1874: /* D31-D24 */ TME_BUS_LANE_ABORT, 1875: 1876: /* initiator maximum cycle size: 24 bits 1877: initiator address offset: 24 bits 1878: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 1879: responder bus port size: 8 bits 1880: responder port least lane: D23-D16: */ 1881: /* D7-D0 */ TME_BUS_LANE_ABORT, 1882: /* D15-D8 */ TME_BUS_LANE_ABORT, 1883: /* D23-D16 */ TME_BUS_LANE_ABORT, 1884: /* D31-D24 */ TME_BUS_LANE_ABORT, 1885: 1886: /* initiator maximum cycle size: 24 bits 1887: initiator address offset: 24 bits 1888: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 1889: responder bus port size: 8 bits 1890: responder port least lane: D31-D24: */ 1891: /* D7-D0 */ TME_BUS_LANE_ABORT, 1892: /* D15-D8 */ TME_BUS_LANE_ABORT, 1893: /* D23-D16 */ TME_BUS_LANE_ABORT, 1894: /* D31-D24 */ TME_BUS_LANE_ABORT, 1895: 1896: /* initiator maximum cycle size: 24 bits 1897: initiator address offset: 24 bits 1898: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 1899: responder bus port size: 16 bits 1900: responder port least lane: D7-D0: */ 1901: /* D7-D0 */ TME_BUS_LANE_ABORT, 1902: /* D15-D8 */ TME_BUS_LANE_ABORT, 1903: /* D23-D16 */ TME_BUS_LANE_ABORT, 1904: /* D31-D24 */ TME_BUS_LANE_ABORT, 1905: 1906: /* initiator maximum cycle size: 24 bits 1907: initiator address offset: 24 bits 1908: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 1909: responder bus port size: 16 bits 1910: responder port least lane: D15-D8: */ 1911: /* D7-D0 */ TME_BUS_LANE_ABORT, 1912: /* D15-D8 */ TME_BUS_LANE_ABORT, 1913: /* D23-D16 */ TME_BUS_LANE_ABORT, 1914: /* D31-D24 */ TME_BUS_LANE_ABORT, 1915: 1916: /* initiator maximum cycle size: 24 bits 1917: initiator address offset: 24 bits 1918: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 1919: responder bus port size: 16 bits 1920: responder port least lane: D23-D16: */ 1921: /* D7-D0 */ TME_BUS_LANE_ABORT, 1922: /* D15-D8 */ TME_BUS_LANE_ABORT, 1923: /* D23-D16 */ TME_BUS_LANE_ABORT, 1924: /* D31-D24 */ TME_BUS_LANE_ABORT, 1925: 1926: /* initiator maximum cycle size: 24 bits 1927: initiator address offset: 24 bits 1928: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 1929: responder bus port size: 16 bits 1930: responder port least lane: D31-D24 1931: (responder port not correctly positioned for this initiator): */ 1932: /* D7-D0 */ TME_BUS_LANE_ABORT, 1933: /* D15-D8 */ TME_BUS_LANE_ABORT, 1934: /* D23-D16 */ TME_BUS_LANE_ABORT, 1935: /* D31-D24 */ TME_BUS_LANE_ABORT, 1936: 1937: /* initiator maximum cycle size: 24 bits 1938: initiator address offset: 24 bits 1939: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 1940: responder bus port size: 32 bits 1941: responder port least lane: D7-D0: */ 1942: /* D7-D0 */ TME_BUS_LANE_ABORT, 1943: /* D15-D8 */ TME_BUS_LANE_ABORT, 1944: /* D23-D16 */ TME_BUS_LANE_ABORT, 1945: /* D31-D24 */ TME_BUS_LANE_ABORT, 1946: 1947: /* initiator maximum cycle size: 24 bits 1948: initiator address offset: 24 bits 1949: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 1950: responder bus port size: 32 bits 1951: responder port least lane: D15-D8 1952: (responder port not correctly positioned for this initiator): */ 1953: /* D7-D0 */ TME_BUS_LANE_ABORT, 1954: /* D15-D8 */ TME_BUS_LANE_ABORT, 1955: /* D23-D16 */ TME_BUS_LANE_ABORT, 1956: /* D31-D24 */ TME_BUS_LANE_ABORT, 1957: 1958: /* initiator maximum cycle size: 24 bits 1959: initiator address offset: 24 bits 1960: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 1961: responder bus port size: 32 bits 1962: responder port least lane: D23-D16 1963: (responder port not correctly positioned for this initiator): */ 1964: /* D7-D0 */ TME_BUS_LANE_ABORT, 1965: /* D15-D8 */ TME_BUS_LANE_ABORT, 1966: /* D23-D16 */ TME_BUS_LANE_ABORT, 1967: /* D31-D24 */ TME_BUS_LANE_ABORT, 1968: 1969: /* initiator maximum cycle size: 24 bits 1970: initiator address offset: 24 bits 1971: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 1972: responder bus port size: 32 bits 1973: responder port least lane: D31-D24 1974: (responder port not correctly positioned for this initiator): */ 1975: /* D7-D0 */ TME_BUS_LANE_ABORT, 1976: /* D15-D8 */ TME_BUS_LANE_ABORT, 1977: /* D23-D16 */ TME_BUS_LANE_ABORT, 1978: /* D31-D24 */ TME_BUS_LANE_ABORT, 1979: 1980: /* initiator maximum cycle size: 32 bits 1981: initiator address offset: 0 bits 1982: responder bus port size: 8 bits 1983: responder port least lane: D7-D0: */ 1984: /* D7-D0 */ TME_BUS_LANE_ROUTE(3), 1985: /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 1986: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1987: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1988: 1989: /* initiator maximum cycle size: 32 bits 1990: initiator address offset: 0 bits 1991: responder bus port size: 8 bits 1992: responder port least lane: D15-D8: */ 1993: /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN, 1994: /* D15-D8 */ TME_BUS_LANE_ROUTE(2), 1995: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 1996: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 1997: 1998: /* initiator maximum cycle size: 32 bits 1999: initiator address offset: 0 bits 2000: responder bus port size: 8 bits 2001: responder port least lane: D23-D16: */ 2002: /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN, 2003: /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 2004: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 2005: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2006: 2007: /* initiator maximum cycle size: 32 bits 2008: initiator address offset: 0 bits 2009: responder bus port size: 8 bits 2010: responder port least lane: D31-D24: */ 2011: /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN, 2012: /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 2013: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 2014: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 2015: 2016: /* initiator maximum cycle size: 32 bits 2017: initiator address offset: 0 bits 2018: responder bus port size: 16 bits 2019: responder port least lane: D7-D0: */ 2020: /* D7-D0 */ TME_BUS_LANE_ROUTE(3), 2021: /* D15-D8 */ TME_BUS_LANE_ROUTE(2), 2022: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 2023: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2024: 2025: /* initiator maximum cycle size: 32 bits 2026: initiator address offset: 0 bits 2027: responder bus port size: 16 bits 2028: responder port least lane: D15-D8: */ 2029: /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN, 2030: /* D15-D8 */ TME_BUS_LANE_ROUTE(2), 2031: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 2032: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2033: 2034: /* initiator maximum cycle size: 32 bits 2035: initiator address offset: 0 bits 2036: responder bus port size: 16 bits 2037: responder port least lane: D23-D16: */ 2038: /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN, 2039: /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 2040: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 2041: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 2042: 2043: /* initiator maximum cycle size: 32 bits 2044: initiator address offset: 0 bits 2045: responder bus port size: 16 bits 2046: responder port least lane: D31-D24 2047: (responder port not correctly positioned for this initiator): */ 2048: /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN, 2049: /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 2050: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 2051: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 2052: 2053: /* initiator maximum cycle size: 32 bits 2054: initiator address offset: 0 bits 2055: responder bus port size: 32 bits 2056: responder port least lane: D7-D0: */ 2057: /* D7-D0 */ TME_BUS_LANE_ROUTE(3), 2058: /* D15-D8 */ TME_BUS_LANE_ROUTE(2), 2059: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 2060: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 2061: 2062: /* initiator maximum cycle size: 32 bits 2063: initiator address offset: 0 bits 2064: responder bus port size: 32 bits 2065: responder port least lane: D15-D8 2066: (responder port not correctly positioned for this initiator): */ 2067: /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN, 2068: /* D15-D8 */ TME_BUS_LANE_ROUTE(2), 2069: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 2070: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 2071: 2072: /* initiator maximum cycle size: 32 bits 2073: initiator address offset: 0 bits 2074: responder bus port size: 32 bits 2075: responder port least lane: D23-D16 2076: (responder port not correctly positioned for this initiator): */ 2077: /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN, 2078: /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 2079: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 2080: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 2081: 2082: /* initiator maximum cycle size: 32 bits 2083: initiator address offset: 0 bits 2084: responder bus port size: 32 bits 2085: responder port least lane: D31-D24 2086: (responder port not correctly positioned for this initiator): */ 2087: /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN, 2088: /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 2089: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 2090: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 2091: 2092: /* initiator maximum cycle size: 32 bits 2093: initiator address offset: 8 bits 2094: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 2095: responder bus port size: 8 bits 2096: responder port least lane: D7-D0: */ 2097: /* D7-D0 */ TME_BUS_LANE_ABORT, 2098: /* D15-D8 */ TME_BUS_LANE_ABORT, 2099: /* D23-D16 */ TME_BUS_LANE_ABORT, 2100: /* D31-D24 */ TME_BUS_LANE_ABORT, 2101: 2102: /* initiator maximum cycle size: 32 bits 2103: initiator address offset: 8 bits 2104: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 2105: responder bus port size: 8 bits 2106: responder port least lane: D15-D8: */ 2107: /* D7-D0 */ TME_BUS_LANE_ABORT, 2108: /* D15-D8 */ TME_BUS_LANE_ABORT, 2109: /* D23-D16 */ TME_BUS_LANE_ABORT, 2110: /* D31-D24 */ TME_BUS_LANE_ABORT, 2111: 2112: /* initiator maximum cycle size: 32 bits 2113: initiator address offset: 8 bits 2114: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 2115: responder bus port size: 8 bits 2116: responder port least lane: D23-D16: */ 2117: /* D7-D0 */ TME_BUS_LANE_ABORT, 2118: /* D15-D8 */ TME_BUS_LANE_ABORT, 2119: /* D23-D16 */ TME_BUS_LANE_ABORT, 2120: /* D31-D24 */ TME_BUS_LANE_ABORT, 2121: 2122: /* initiator maximum cycle size: 32 bits 2123: initiator address offset: 8 bits 2124: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 2125: responder bus port size: 8 bits 2126: responder port least lane: D31-D24: */ 2127: /* D7-D0 */ TME_BUS_LANE_ABORT, 2128: /* D15-D8 */ TME_BUS_LANE_ABORT, 2129: /* D23-D16 */ TME_BUS_LANE_ABORT, 2130: /* D31-D24 */ TME_BUS_LANE_ABORT, 2131: 2132: /* initiator maximum cycle size: 32 bits 2133: initiator address offset: 8 bits 2134: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 2135: responder bus port size: 16 bits 2136: responder port least lane: D7-D0: */ 2137: /* D7-D0 */ TME_BUS_LANE_ABORT, 2138: /* D15-D8 */ TME_BUS_LANE_ABORT, 2139: /* D23-D16 */ TME_BUS_LANE_ABORT, 2140: /* D31-D24 */ TME_BUS_LANE_ABORT, 2141: 2142: /* initiator maximum cycle size: 32 bits 2143: initiator address offset: 8 bits 2144: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 2145: responder bus port size: 16 bits 2146: responder port least lane: D15-D8: */ 2147: /* D7-D0 */ TME_BUS_LANE_ABORT, 2148: /* D15-D8 */ TME_BUS_LANE_ABORT, 2149: /* D23-D16 */ TME_BUS_LANE_ABORT, 2150: /* D31-D24 */ TME_BUS_LANE_ABORT, 2151: 2152: /* initiator maximum cycle size: 32 bits 2153: initiator address offset: 8 bits 2154: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 2155: responder bus port size: 16 bits 2156: responder port least lane: D23-D16: */ 2157: /* D7-D0 */ TME_BUS_LANE_ABORT, 2158: /* D15-D8 */ TME_BUS_LANE_ABORT, 2159: /* D23-D16 */ TME_BUS_LANE_ABORT, 2160: /* D31-D24 */ TME_BUS_LANE_ABORT, 2161: 2162: /* initiator maximum cycle size: 32 bits 2163: initiator address offset: 8 bits 2164: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 2165: responder bus port size: 16 bits 2166: responder port least lane: D31-D24 2167: (responder port not correctly positioned for this initiator): */ 2168: /* D7-D0 */ TME_BUS_LANE_ABORT, 2169: /* D15-D8 */ TME_BUS_LANE_ABORT, 2170: /* D23-D16 */ TME_BUS_LANE_ABORT, 2171: /* D31-D24 */ TME_BUS_LANE_ABORT, 2172: 2173: /* initiator maximum cycle size: 32 bits 2174: initiator address offset: 8 bits 2175: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 2176: responder bus port size: 32 bits 2177: responder port least lane: D7-D0: */ 2178: /* D7-D0 */ TME_BUS_LANE_ABORT, 2179: /* D15-D8 */ TME_BUS_LANE_ABORT, 2180: /* D23-D16 */ TME_BUS_LANE_ABORT, 2181: /* D31-D24 */ TME_BUS_LANE_ABORT, 2182: 2183: /* initiator maximum cycle size: 32 bits 2184: initiator address offset: 8 bits 2185: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 2186: responder bus port size: 32 bits 2187: responder port least lane: D15-D8 2188: (responder port not correctly positioned for this initiator): */ 2189: /* D7-D0 */ TME_BUS_LANE_ABORT, 2190: /* D15-D8 */ TME_BUS_LANE_ABORT, 2191: /* D23-D16 */ TME_BUS_LANE_ABORT, 2192: /* D31-D24 */ TME_BUS_LANE_ABORT, 2193: 2194: /* initiator maximum cycle size: 32 bits 2195: initiator address offset: 8 bits 2196: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 2197: responder bus port size: 32 bits 2198: responder port least lane: D23-D16 2199: (responder port not correctly positioned for this initiator): */ 2200: /* D7-D0 */ TME_BUS_LANE_ABORT, 2201: /* D15-D8 */ TME_BUS_LANE_ABORT, 2202: /* D23-D16 */ TME_BUS_LANE_ABORT, 2203: /* D31-D24 */ TME_BUS_LANE_ABORT, 2204: 2205: /* initiator maximum cycle size: 32 bits 2206: initiator address offset: 8 bits 2207: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 2208: responder bus port size: 32 bits 2209: responder port least lane: D31-D24 2210: (responder port not correctly positioned for this initiator): */ 2211: /* D7-D0 */ TME_BUS_LANE_ABORT, 2212: /* D15-D8 */ TME_BUS_LANE_ABORT, 2213: /* D23-D16 */ TME_BUS_LANE_ABORT, 2214: /* D31-D24 */ TME_BUS_LANE_ABORT, 2215: 2216: /* initiator maximum cycle size: 32 bits 2217: initiator address offset: 16 bits 2218: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 2219: responder bus port size: 8 bits 2220: responder port least lane: D7-D0: */ 2221: /* D7-D0 */ TME_BUS_LANE_ABORT, 2222: /* D15-D8 */ TME_BUS_LANE_ABORT, 2223: /* D23-D16 */ TME_BUS_LANE_ABORT, 2224: /* D31-D24 */ TME_BUS_LANE_ABORT, 2225: 2226: /* initiator maximum cycle size: 32 bits 2227: initiator address offset: 16 bits 2228: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 2229: responder bus port size: 8 bits 2230: responder port least lane: D15-D8: */ 2231: /* D7-D0 */ TME_BUS_LANE_ABORT, 2232: /* D15-D8 */ TME_BUS_LANE_ABORT, 2233: /* D23-D16 */ TME_BUS_LANE_ABORT, 2234: /* D31-D24 */ TME_BUS_LANE_ABORT, 2235: 2236: /* initiator maximum cycle size: 32 bits 2237: initiator address offset: 16 bits 2238: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 2239: responder bus port size: 8 bits 2240: responder port least lane: D23-D16: */ 2241: /* D7-D0 */ TME_BUS_LANE_ABORT, 2242: /* D15-D8 */ TME_BUS_LANE_ABORT, 2243: /* D23-D16 */ TME_BUS_LANE_ABORT, 2244: /* D31-D24 */ TME_BUS_LANE_ABORT, 2245: 2246: /* initiator maximum cycle size: 32 bits 2247: initiator address offset: 16 bits 2248: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 2249: responder bus port size: 8 bits 2250: responder port least lane: D31-D24: */ 2251: /* D7-D0 */ TME_BUS_LANE_ABORT, 2252: /* D15-D8 */ TME_BUS_LANE_ABORT, 2253: /* D23-D16 */ TME_BUS_LANE_ABORT, 2254: /* D31-D24 */ TME_BUS_LANE_ABORT, 2255: 2256: /* initiator maximum cycle size: 32 bits 2257: initiator address offset: 16 bits 2258: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 2259: responder bus port size: 16 bits 2260: responder port least lane: D7-D0: */ 2261: /* D7-D0 */ TME_BUS_LANE_ABORT, 2262: /* D15-D8 */ TME_BUS_LANE_ABORT, 2263: /* D23-D16 */ TME_BUS_LANE_ABORT, 2264: /* D31-D24 */ TME_BUS_LANE_ABORT, 2265: 2266: /* initiator maximum cycle size: 32 bits 2267: initiator address offset: 16 bits 2268: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 2269: responder bus port size: 16 bits 2270: responder port least lane: D15-D8: */ 2271: /* D7-D0 */ TME_BUS_LANE_ABORT, 2272: /* D15-D8 */ TME_BUS_LANE_ABORT, 2273: /* D23-D16 */ TME_BUS_LANE_ABORT, 2274: /* D31-D24 */ TME_BUS_LANE_ABORT, 2275: 2276: /* initiator maximum cycle size: 32 bits 2277: initiator address offset: 16 bits 2278: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 2279: responder bus port size: 16 bits 2280: responder port least lane: D23-D16: */ 2281: /* D7-D0 */ TME_BUS_LANE_ABORT, 2282: /* D15-D8 */ TME_BUS_LANE_ABORT, 2283: /* D23-D16 */ TME_BUS_LANE_ABORT, 2284: /* D31-D24 */ TME_BUS_LANE_ABORT, 2285: 2286: /* initiator maximum cycle size: 32 bits 2287: initiator address offset: 16 bits 2288: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 2289: responder bus port size: 16 bits 2290: responder port least lane: D31-D24 2291: (responder port not correctly positioned for this initiator): */ 2292: /* D7-D0 */ TME_BUS_LANE_ABORT, 2293: /* D15-D8 */ TME_BUS_LANE_ABORT, 2294: /* D23-D16 */ TME_BUS_LANE_ABORT, 2295: /* D31-D24 */ TME_BUS_LANE_ABORT, 2296: 2297: /* initiator maximum cycle size: 32 bits 2298: initiator address offset: 16 bits 2299: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 2300: responder bus port size: 32 bits 2301: responder port least lane: D7-D0: */ 2302: /* D7-D0 */ TME_BUS_LANE_ABORT, 2303: /* D15-D8 */ TME_BUS_LANE_ABORT, 2304: /* D23-D16 */ TME_BUS_LANE_ABORT, 2305: /* D31-D24 */ TME_BUS_LANE_ABORT, 2306: 2307: /* initiator maximum cycle size: 32 bits 2308: initiator address offset: 16 bits 2309: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 2310: responder bus port size: 32 bits 2311: responder port least lane: D15-D8 2312: (responder port not correctly positioned for this initiator): */ 2313: /* D7-D0 */ TME_BUS_LANE_ABORT, 2314: /* D15-D8 */ TME_BUS_LANE_ABORT, 2315: /* D23-D16 */ TME_BUS_LANE_ABORT, 2316: /* D31-D24 */ TME_BUS_LANE_ABORT, 2317: 2318: /* initiator maximum cycle size: 32 bits 2319: initiator address offset: 16 bits 2320: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 2321: responder bus port size: 32 bits 2322: responder port least lane: D23-D16 2323: (responder port not correctly positioned for this initiator): */ 2324: /* D7-D0 */ TME_BUS_LANE_ABORT, 2325: /* D15-D8 */ TME_BUS_LANE_ABORT, 2326: /* D23-D16 */ TME_BUS_LANE_ABORT, 2327: /* D31-D24 */ TME_BUS_LANE_ABORT, 2328: 2329: /* initiator maximum cycle size: 32 bits 2330: initiator address offset: 16 bits 2331: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 2332: responder bus port size: 32 bits 2333: responder port least lane: D31-D24 2334: (responder port not correctly positioned for this initiator): */ 2335: /* D7-D0 */ TME_BUS_LANE_ABORT, 2336: /* D15-D8 */ TME_BUS_LANE_ABORT, 2337: /* D23-D16 */ TME_BUS_LANE_ABORT, 2338: /* D31-D24 */ TME_BUS_LANE_ABORT, 2339: 2340: /* initiator maximum cycle size: 32 bits 2341: initiator address offset: 24 bits 2342: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 2343: responder bus port size: 8 bits 2344: responder port least lane: D7-D0: */ 2345: /* D7-D0 */ TME_BUS_LANE_ABORT, 2346: /* D15-D8 */ TME_BUS_LANE_ABORT, 2347: /* D23-D16 */ TME_BUS_LANE_ABORT, 2348: /* D31-D24 */ TME_BUS_LANE_ABORT, 2349: 2350: /* initiator maximum cycle size: 32 bits 2351: initiator address offset: 24 bits 2352: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 2353: responder bus port size: 8 bits 2354: responder port least lane: D15-D8: */ 2355: /* D7-D0 */ TME_BUS_LANE_ABORT, 2356: /* D15-D8 */ TME_BUS_LANE_ABORT, 2357: /* D23-D16 */ TME_BUS_LANE_ABORT, 2358: /* D31-D24 */ TME_BUS_LANE_ABORT, 2359: 2360: /* initiator maximum cycle size: 32 bits 2361: initiator address offset: 24 bits 2362: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 2363: responder bus port size: 8 bits 2364: responder port least lane: D23-D16: */ 2365: /* D7-D0 */ TME_BUS_LANE_ABORT, 2366: /* D15-D8 */ TME_BUS_LANE_ABORT, 2367: /* D23-D16 */ TME_BUS_LANE_ABORT, 2368: /* D31-D24 */ TME_BUS_LANE_ABORT, 2369: 2370: /* initiator maximum cycle size: 32 bits 2371: initiator address offset: 24 bits 2372: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 2373: responder bus port size: 8 bits 2374: responder port least lane: D31-D24: */ 2375: /* D7-D0 */ TME_BUS_LANE_ABORT, 2376: /* D15-D8 */ TME_BUS_LANE_ABORT, 2377: /* D23-D16 */ TME_BUS_LANE_ABORT, 2378: /* D31-D24 */ TME_BUS_LANE_ABORT, 2379: 2380: /* initiator maximum cycle size: 32 bits 2381: initiator address offset: 24 bits 2382: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 2383: responder bus port size: 16 bits 2384: responder port least lane: D7-D0: */ 2385: /* D7-D0 */ TME_BUS_LANE_ABORT, 2386: /* D15-D8 */ TME_BUS_LANE_ABORT, 2387: /* D23-D16 */ TME_BUS_LANE_ABORT, 2388: /* D31-D24 */ TME_BUS_LANE_ABORT, 2389: 2390: /* initiator maximum cycle size: 32 bits 2391: initiator address offset: 24 bits 2392: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 2393: responder bus port size: 16 bits 2394: responder port least lane: D15-D8: */ 2395: /* D7-D0 */ TME_BUS_LANE_ABORT, 2396: /* D15-D8 */ TME_BUS_LANE_ABORT, 2397: /* D23-D16 */ TME_BUS_LANE_ABORT, 2398: /* D31-D24 */ TME_BUS_LANE_ABORT, 2399: 2400: /* initiator maximum cycle size: 32 bits 2401: initiator address offset: 24 bits 2402: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 2403: responder bus port size: 16 bits 2404: responder port least lane: D23-D16: */ 2405: /* D7-D0 */ TME_BUS_LANE_ABORT, 2406: /* D15-D8 */ TME_BUS_LANE_ABORT, 2407: /* D23-D16 */ TME_BUS_LANE_ABORT, 2408: /* D31-D24 */ TME_BUS_LANE_ABORT, 2409: 2410: /* initiator maximum cycle size: 32 bits 2411: initiator address offset: 24 bits 2412: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 2413: responder bus port size: 16 bits 2414: responder port least lane: D31-D24 2415: (responder port not correctly positioned for this initiator): */ 2416: /* D7-D0 */ TME_BUS_LANE_ABORT, 2417: /* D15-D8 */ TME_BUS_LANE_ABORT, 2418: /* D23-D16 */ TME_BUS_LANE_ABORT, 2419: /* D31-D24 */ TME_BUS_LANE_ABORT, 2420: 2421: /* initiator maximum cycle size: 32 bits 2422: initiator address offset: 24 bits 2423: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 2424: responder bus port size: 32 bits 2425: responder port least lane: D7-D0: */ 2426: /* D7-D0 */ TME_BUS_LANE_ABORT, 2427: /* D15-D8 */ TME_BUS_LANE_ABORT, 2428: /* D23-D16 */ TME_BUS_LANE_ABORT, 2429: /* D31-D24 */ TME_BUS_LANE_ABORT, 2430: 2431: /* initiator maximum cycle size: 32 bits 2432: initiator address offset: 24 bits 2433: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 2434: responder bus port size: 32 bits 2435: responder port least lane: D15-D8 2436: (responder port not correctly positioned for this initiator): */ 2437: /* D7-D0 */ TME_BUS_LANE_ABORT, 2438: /* D15-D8 */ TME_BUS_LANE_ABORT, 2439: /* D23-D16 */ TME_BUS_LANE_ABORT, 2440: /* D31-D24 */ TME_BUS_LANE_ABORT, 2441: 2442: /* initiator maximum cycle size: 32 bits 2443: initiator address offset: 24 bits 2444: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 2445: responder bus port size: 32 bits 2446: responder port least lane: D23-D16 2447: (responder port not correctly positioned for this initiator): */ 2448: /* D7-D0 */ TME_BUS_LANE_ABORT, 2449: /* D15-D8 */ TME_BUS_LANE_ABORT, 2450: /* D23-D16 */ TME_BUS_LANE_ABORT, 2451: /* D31-D24 */ TME_BUS_LANE_ABORT, 2452: 2453: /* initiator maximum cycle size: 32 bits 2454: initiator address offset: 24 bits 2455: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 2456: responder bus port size: 32 bits 2457: responder port least lane: D31-D24 2458: (responder port not correctly positioned for this initiator): */ 2459: /* D7-D0 */ TME_BUS_LANE_ABORT, 2460: /* D15-D8 */ TME_BUS_LANE_ABORT, 2461: /* D23-D16 */ TME_BUS_LANE_ABORT, 2462: /* D31-D24 */ TME_BUS_LANE_ABORT, 2463: }; 2464: 2465: /* the 32-bit little-endian bus master bus router: */ 2466: const tme_bus_lane_t tme_bus_device_router_32el[TME_BUS_ROUTER_INIT_SIZE(TME_BUS32_LOG2)] = { 2467: 2468: /* initiator maximum cycle size: 8 bits 2469: initiator address offset: 0 bits 2470: responder bus port size: 8 bits 2471: responder port least lane: D7-D0: */ 2472: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 2473: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2474: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2475: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2476: 2477: /* initiator maximum cycle size: 8 bits 2478: initiator address offset: 0 bits 2479: responder bus port size: 8 bits 2480: responder port least lane: D15-D8: */ 2481: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2482: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2483: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2484: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2485: 2486: /* initiator maximum cycle size: 8 bits 2487: initiator address offset: 0 bits 2488: responder bus port size: 8 bits 2489: responder port least lane: D23-D16: */ 2490: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2491: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2492: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2493: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2494: 2495: /* initiator maximum cycle size: 8 bits 2496: initiator address offset: 0 bits 2497: responder bus port size: 8 bits 2498: responder port least lane: D31-D24: */ 2499: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2500: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2501: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2502: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2503: 2504: /* initiator maximum cycle size: 8 bits 2505: initiator address offset: 0 bits 2506: responder bus port size: 16 bits 2507: responder port least lane: D7-D0: */ 2508: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 2509: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2510: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2511: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2512: 2513: /* initiator maximum cycle size: 8 bits 2514: initiator address offset: 0 bits 2515: responder bus port size: 16 bits 2516: responder port least lane: D15-D8: */ 2517: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2518: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2519: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2520: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2521: 2522: /* initiator maximum cycle size: 8 bits 2523: initiator address offset: 0 bits 2524: responder bus port size: 16 bits 2525: responder port least lane: D23-D16: */ 2526: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2527: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2528: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2529: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2530: 2531: /* initiator maximum cycle size: 8 bits 2532: initiator address offset: 0 bits 2533: responder bus port size: 16 bits 2534: responder port least lane: D31-D24 2535: (responder port not correctly positioned for this initiator): */ 2536: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2537: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2538: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2539: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2540: 2541: /* initiator maximum cycle size: 8 bits 2542: initiator address offset: 0 bits 2543: responder bus port size: 32 bits 2544: responder port least lane: D7-D0: */ 2545: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 2546: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2547: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2548: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2549: 2550: /* initiator maximum cycle size: 8 bits 2551: initiator address offset: 0 bits 2552: responder bus port size: 32 bits 2553: responder port least lane: D15-D8 2554: (responder port not correctly positioned for this initiator): */ 2555: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2556: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2557: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2558: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2559: 2560: /* initiator maximum cycle size: 8 bits 2561: initiator address offset: 0 bits 2562: responder bus port size: 32 bits 2563: responder port least lane: D23-D16 2564: (responder port not correctly positioned for this initiator): */ 2565: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2566: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2567: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2568: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2569: 2570: /* initiator maximum cycle size: 8 bits 2571: initiator address offset: 0 bits 2572: responder bus port size: 32 bits 2573: responder port least lane: D31-D24 2574: (responder port not correctly positioned for this initiator): */ 2575: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2576: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2577: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2578: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2579: 2580: /* initiator maximum cycle size: 8 bits 2581: initiator address offset: 8 bits 2582: responder bus port size: 8 bits 2583: responder port least lane: D7-D0: */ 2584: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2585: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2586: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2587: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2588: 2589: /* initiator maximum cycle size: 8 bits 2590: initiator address offset: 8 bits 2591: responder bus port size: 8 bits 2592: responder port least lane: D15-D8: */ 2593: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2594: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 2595: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2596: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2597: 2598: /* initiator maximum cycle size: 8 bits 2599: initiator address offset: 8 bits 2600: responder bus port size: 8 bits 2601: responder port least lane: D23-D16: */ 2602: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2603: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2604: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2605: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2606: 2607: /* initiator maximum cycle size: 8 bits 2608: initiator address offset: 8 bits 2609: responder bus port size: 8 bits 2610: responder port least lane: D31-D24: */ 2611: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2612: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2613: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2614: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2615: 2616: /* initiator maximum cycle size: 8 bits 2617: initiator address offset: 8 bits 2618: responder bus port size: 16 bits 2619: responder port least lane: D7-D0: */ 2620: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2621: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 2622: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2623: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2624: 2625: /* initiator maximum cycle size: 8 bits 2626: initiator address offset: 8 bits 2627: responder bus port size: 16 bits 2628: responder port least lane: D15-D8: */ 2629: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2630: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 2631: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2632: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2633: 2634: /* initiator maximum cycle size: 8 bits 2635: initiator address offset: 8 bits 2636: responder bus port size: 16 bits 2637: responder port least lane: D23-D16: */ 2638: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2639: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2640: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2641: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2642: 2643: /* initiator maximum cycle size: 8 bits 2644: initiator address offset: 8 bits 2645: responder bus port size: 16 bits 2646: responder port least lane: D31-D24 2647: (responder port not correctly positioned for this initiator): */ 2648: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2649: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2650: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2651: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2652: 2653: /* initiator maximum cycle size: 8 bits 2654: initiator address offset: 8 bits 2655: responder bus port size: 32 bits 2656: responder port least lane: D7-D0: */ 2657: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2658: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 2659: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2660: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2661: 2662: /* initiator maximum cycle size: 8 bits 2663: initiator address offset: 8 bits 2664: responder bus port size: 32 bits 2665: responder port least lane: D15-D8 2666: (responder port not correctly positioned for this initiator): */ 2667: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2668: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 2669: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2670: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2671: 2672: /* initiator maximum cycle size: 8 bits 2673: initiator address offset: 8 bits 2674: responder bus port size: 32 bits 2675: responder port least lane: D23-D16 2676: (responder port not correctly positioned for this initiator): */ 2677: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2678: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2679: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2680: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2681: 2682: /* initiator maximum cycle size: 8 bits 2683: initiator address offset: 8 bits 2684: responder bus port size: 32 bits 2685: responder port least lane: D31-D24 2686: (responder port not correctly positioned for this initiator): */ 2687: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2688: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2689: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2690: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2691: 2692: /* initiator maximum cycle size: 8 bits 2693: initiator address offset: 16 bits 2694: responder bus port size: 8 bits 2695: responder port least lane: D7-D0: */ 2696: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2697: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2698: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2699: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2700: 2701: /* initiator maximum cycle size: 8 bits 2702: initiator address offset: 16 bits 2703: responder bus port size: 8 bits 2704: responder port least lane: D15-D8: */ 2705: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2706: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2707: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2708: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2709: 2710: /* initiator maximum cycle size: 8 bits 2711: initiator address offset: 16 bits 2712: responder bus port size: 8 bits 2713: responder port least lane: D23-D16: */ 2714: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2715: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2716: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 2717: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2718: 2719: /* initiator maximum cycle size: 8 bits 2720: initiator address offset: 16 bits 2721: responder bus port size: 8 bits 2722: responder port least lane: D31-D24: */ 2723: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2724: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2725: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2726: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2727: 2728: /* initiator maximum cycle size: 8 bits 2729: initiator address offset: 16 bits 2730: responder bus port size: 16 bits 2731: responder port least lane: D7-D0: */ 2732: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2733: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2734: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2735: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2736: 2737: /* initiator maximum cycle size: 8 bits 2738: initiator address offset: 16 bits 2739: responder bus port size: 16 bits 2740: responder port least lane: D15-D8: */ 2741: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2742: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2743: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 2744: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2745: 2746: /* initiator maximum cycle size: 8 bits 2747: initiator address offset: 16 bits 2748: responder bus port size: 16 bits 2749: responder port least lane: D23-D16: */ 2750: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2751: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2752: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 2753: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2754: 2755: /* initiator maximum cycle size: 8 bits 2756: initiator address offset: 16 bits 2757: responder bus port size: 16 bits 2758: responder port least lane: D31-D24 2759: (responder port not correctly positioned for this initiator): */ 2760: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2761: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2762: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2763: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2764: 2765: /* initiator maximum cycle size: 8 bits 2766: initiator address offset: 16 bits 2767: responder bus port size: 32 bits 2768: responder port least lane: D7-D0: */ 2769: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2770: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2771: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 2772: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2773: 2774: /* initiator maximum cycle size: 8 bits 2775: initiator address offset: 16 bits 2776: responder bus port size: 32 bits 2777: responder port least lane: D15-D8 2778: (responder port not correctly positioned for this initiator): */ 2779: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2780: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2781: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 2782: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2783: 2784: /* initiator maximum cycle size: 8 bits 2785: initiator address offset: 16 bits 2786: responder bus port size: 32 bits 2787: responder port least lane: D23-D16 2788: (responder port not correctly positioned for this initiator): */ 2789: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2790: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2791: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 2792: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2793: 2794: /* initiator maximum cycle size: 8 bits 2795: initiator address offset: 16 bits 2796: responder bus port size: 32 bits 2797: responder port least lane: D31-D24 2798: (responder port not correctly positioned for this initiator): */ 2799: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2800: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2801: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2802: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2803: 2804: /* initiator maximum cycle size: 8 bits 2805: initiator address offset: 24 bits 2806: responder bus port size: 8 bits 2807: responder port least lane: D7-D0: */ 2808: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2809: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2810: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2811: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2812: 2813: /* initiator maximum cycle size: 8 bits 2814: initiator address offset: 24 bits 2815: responder bus port size: 8 bits 2816: responder port least lane: D15-D8: */ 2817: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2818: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2819: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2820: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2821: 2822: /* initiator maximum cycle size: 8 bits 2823: initiator address offset: 24 bits 2824: responder bus port size: 8 bits 2825: responder port least lane: D23-D16: */ 2826: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2827: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2828: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2829: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2830: 2831: /* initiator maximum cycle size: 8 bits 2832: initiator address offset: 24 bits 2833: responder bus port size: 8 bits 2834: responder port least lane: D31-D24: */ 2835: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2836: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2837: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2838: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 2839: 2840: /* initiator maximum cycle size: 8 bits 2841: initiator address offset: 24 bits 2842: responder bus port size: 16 bits 2843: responder port least lane: D7-D0: */ 2844: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2845: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2846: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2847: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2848: 2849: /* initiator maximum cycle size: 8 bits 2850: initiator address offset: 24 bits 2851: responder bus port size: 16 bits 2852: responder port least lane: D15-D8: */ 2853: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2854: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2855: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2856: /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2857: 2858: /* initiator maximum cycle size: 8 bits 2859: initiator address offset: 24 bits 2860: responder bus port size: 16 bits 2861: responder port least lane: D23-D16: */ 2862: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2863: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2864: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2865: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 2866: 2867: /* initiator maximum cycle size: 8 bits 2868: initiator address offset: 24 bits 2869: responder bus port size: 16 bits 2870: responder port least lane: D31-D24 2871: (responder port not correctly positioned for this initiator): */ 2872: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2873: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2874: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2875: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 2876: 2877: /* initiator maximum cycle size: 8 bits 2878: initiator address offset: 24 bits 2879: responder bus port size: 32 bits 2880: responder port least lane: D7-D0: */ 2881: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2882: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2883: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2884: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 2885: 2886: /* initiator maximum cycle size: 8 bits 2887: initiator address offset: 24 bits 2888: responder bus port size: 32 bits 2889: responder port least lane: D15-D8 2890: (responder port not correctly positioned for this initiator): */ 2891: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2892: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2893: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2894: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 2895: 2896: /* initiator maximum cycle size: 8 bits 2897: initiator address offset: 24 bits 2898: responder bus port size: 32 bits 2899: responder port least lane: D23-D16 2900: (responder port not correctly positioned for this initiator): */ 2901: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2902: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2903: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2904: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 2905: 2906: /* initiator maximum cycle size: 8 bits 2907: initiator address offset: 24 bits 2908: responder bus port size: 32 bits 2909: responder port least lane: D31-D24 2910: (responder port not correctly positioned for this initiator): */ 2911: /* D7-D0 */ TME_BUS_LANE_UNDEF, 2912: /* D15-D8 */ TME_BUS_LANE_UNDEF, 2913: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2914: /* D31-D24 */ TME_BUS_LANE_ROUTE(0), 2915: 2916: /* initiator maximum cycle size: 16 bits 2917: initiator address offset: 0 bits 2918: responder bus port size: 8 bits 2919: responder port least lane: D7-D0: */ 2920: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 2921: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 2922: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2923: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2924: 2925: /* initiator maximum cycle size: 16 bits 2926: initiator address offset: 0 bits 2927: responder bus port size: 8 bits 2928: responder port least lane: D15-D8: */ 2929: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2930: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 2931: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2932: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2933: 2934: /* initiator maximum cycle size: 16 bits 2935: initiator address offset: 0 bits 2936: responder bus port size: 8 bits 2937: responder port least lane: D23-D16: */ 2938: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2939: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 2940: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2941: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2942: 2943: /* initiator maximum cycle size: 16 bits 2944: initiator address offset: 0 bits 2945: responder bus port size: 8 bits 2946: responder port least lane: D31-D24: */ 2947: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2948: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 2949: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2950: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2951: 2952: /* initiator maximum cycle size: 16 bits 2953: initiator address offset: 0 bits 2954: responder bus port size: 16 bits 2955: responder port least lane: D7-D0: */ 2956: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 2957: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 2958: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2959: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2960: 2961: /* initiator maximum cycle size: 16 bits 2962: initiator address offset: 0 bits 2963: responder bus port size: 16 bits 2964: responder port least lane: D15-D8: */ 2965: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2966: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 2967: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2968: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2969: 2970: /* initiator maximum cycle size: 16 bits 2971: initiator address offset: 0 bits 2972: responder bus port size: 16 bits 2973: responder port least lane: D23-D16: */ 2974: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2975: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 2976: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2977: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2978: 2979: /* initiator maximum cycle size: 16 bits 2980: initiator address offset: 0 bits 2981: responder bus port size: 16 bits 2982: responder port least lane: D31-D24 2983: (responder port not correctly positioned for this initiator): */ 2984: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 2985: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 2986: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2987: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2988: 2989: /* initiator maximum cycle size: 16 bits 2990: initiator address offset: 0 bits 2991: responder bus port size: 32 bits 2992: responder port least lane: D7-D0: */ 2993: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 2994: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 2995: /* D23-D16 */ TME_BUS_LANE_UNDEF, 2996: /* D31-D24 */ TME_BUS_LANE_UNDEF, 2997: 2998: /* initiator maximum cycle size: 16 bits 2999: initiator address offset: 0 bits 3000: responder bus port size: 32 bits 3001: responder port least lane: D15-D8 3002: (responder port not correctly positioned for this initiator): */ 3003: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3004: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 3005: /* D23-D16 */ TME_BUS_LANE_UNDEF, 3006: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3007: 3008: /* initiator maximum cycle size: 16 bits 3009: initiator address offset: 0 bits 3010: responder bus port size: 32 bits 3011: responder port least lane: D23-D16 3012: (responder port not correctly positioned for this initiator): */ 3013: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3014: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3015: /* D23-D16 */ TME_BUS_LANE_UNDEF, 3016: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3017: 3018: /* initiator maximum cycle size: 16 bits 3019: initiator address offset: 0 bits 3020: responder bus port size: 32 bits 3021: responder port least lane: D31-D24 3022: (responder port not correctly positioned for this initiator): */ 3023: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3024: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3025: /* D23-D16 */ TME_BUS_LANE_UNDEF, 3026: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3027: 3028: /* initiator maximum cycle size: 16 bits 3029: initiator address offset: 8 bits 3030: responder bus port size: 8 bits 3031: responder port least lane: D7-D0: */ 3032: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3033: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3034: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3035: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3036: 3037: /* initiator maximum cycle size: 16 bits 3038: initiator address offset: 8 bits 3039: responder bus port size: 8 bits 3040: responder port least lane: D15-D8: */ 3041: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3042: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 3043: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3044: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3045: 3046: /* initiator maximum cycle size: 16 bits 3047: initiator address offset: 8 bits 3048: responder bus port size: 8 bits 3049: responder port least lane: D23-D16: */ 3050: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3051: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3052: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 3053: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3054: 3055: /* initiator maximum cycle size: 16 bits 3056: initiator address offset: 8 bits 3057: responder bus port size: 8 bits 3058: responder port least lane: D31-D24: */ 3059: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3060: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3061: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3062: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3063: 3064: /* initiator maximum cycle size: 16 bits 3065: initiator address offset: 8 bits 3066: responder bus port size: 16 bits 3067: responder port least lane: D7-D0: */ 3068: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3069: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 3070: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3071: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3072: 3073: /* initiator maximum cycle size: 16 bits 3074: initiator address offset: 8 bits 3075: responder bus port size: 16 bits 3076: responder port least lane: D15-D8: */ 3077: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3078: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 3079: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 3080: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3081: 3082: /* initiator maximum cycle size: 16 bits 3083: initiator address offset: 8 bits 3084: responder bus port size: 16 bits 3085: responder port least lane: D23-D16: */ 3086: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3087: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3088: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 3089: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3090: 3091: /* initiator maximum cycle size: 16 bits 3092: initiator address offset: 8 bits 3093: responder bus port size: 16 bits 3094: responder port least lane: D31-D24 3095: (responder port not correctly positioned for this initiator): */ 3096: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3097: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3098: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3099: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3100: 3101: /* initiator maximum cycle size: 16 bits 3102: initiator address offset: 8 bits 3103: responder bus port size: 32 bits 3104: responder port least lane: D7-D0: */ 3105: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3106: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 3107: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 3108: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3109: 3110: /* initiator maximum cycle size: 16 bits 3111: initiator address offset: 8 bits 3112: responder bus port size: 32 bits 3113: responder port least lane: D15-D8 3114: (responder port not correctly positioned for this initiator): */ 3115: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3116: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 3117: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 3118: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3119: 3120: /* initiator maximum cycle size: 16 bits 3121: initiator address offset: 8 bits 3122: responder bus port size: 32 bits 3123: responder port least lane: D23-D16 3124: (responder port not correctly positioned for this initiator): */ 3125: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3126: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3127: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 3128: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3129: 3130: /* initiator maximum cycle size: 16 bits 3131: initiator address offset: 8 bits 3132: responder bus port size: 32 bits 3133: responder port least lane: D31-D24 3134: (responder port not correctly positioned for this initiator): */ 3135: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3136: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3137: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3138: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3139: 3140: /* initiator maximum cycle size: 16 bits 3141: initiator address offset: 16 bits 3142: responder bus port size: 8 bits 3143: responder port least lane: D7-D0: */ 3144: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3145: /* D15-D8 */ TME_BUS_LANE_UNDEF, 3146: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3147: /* D31-D24 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3148: 3149: /* initiator maximum cycle size: 16 bits 3150: initiator address offset: 16 bits 3151: responder bus port size: 8 bits 3152: responder port least lane: D15-D8: */ 3153: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3154: /* D15-D8 */ TME_BUS_LANE_UNDEF, 3155: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3156: /* D31-D24 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3157: 3158: /* initiator maximum cycle size: 16 bits 3159: initiator address offset: 16 bits 3160: responder bus port size: 8 bits 3161: responder port least lane: D23-D16: */ 3162: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3163: /* D15-D8 */ TME_BUS_LANE_UNDEF, 3164: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 3165: /* D31-D24 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3166: 3167: /* initiator maximum cycle size: 16 bits 3168: initiator address offset: 16 bits 3169: responder bus port size: 8 bits 3170: responder port least lane: D31-D24: */ 3171: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3172: /* D15-D8 */ TME_BUS_LANE_UNDEF, 3173: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3174: /* D31-D24 */ TME_BUS_LANE_ROUTE(1), 3175: 3176: /* initiator maximum cycle size: 16 bits 3177: initiator address offset: 16 bits 3178: responder bus port size: 16 bits 3179: responder port least lane: D7-D0: */ 3180: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3181: /* D15-D8 */ TME_BUS_LANE_UNDEF, 3182: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3183: /* D31-D24 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3184: 3185: /* initiator maximum cycle size: 16 bits 3186: initiator address offset: 16 bits 3187: responder bus port size: 16 bits 3188: responder port least lane: D15-D8: */ 3189: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3190: /* D15-D8 */ TME_BUS_LANE_UNDEF, 3191: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 3192: /* D31-D24 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3193: 3194: /* initiator maximum cycle size: 16 bits 3195: initiator address offset: 16 bits 3196: responder bus port size: 16 bits 3197: responder port least lane: D23-D16: */ 3198: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3199: /* D15-D8 */ TME_BUS_LANE_UNDEF, 3200: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 3201: /* D31-D24 */ TME_BUS_LANE_ROUTE(1), 3202: 3203: /* initiator maximum cycle size: 16 bits 3204: initiator address offset: 16 bits 3205: responder bus port size: 16 bits 3206: responder port least lane: D31-D24 3207: (responder port not correctly positioned for this initiator): */ 3208: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3209: /* D15-D8 */ TME_BUS_LANE_UNDEF, 3210: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3211: /* D31-D24 */ TME_BUS_LANE_ROUTE(1), 3212: 3213: /* initiator maximum cycle size: 16 bits 3214: initiator address offset: 16 bits 3215: responder bus port size: 32 bits 3216: responder port least lane: D7-D0: */ 3217: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3218: /* D15-D8 */ TME_BUS_LANE_UNDEF, 3219: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 3220: /* D31-D24 */ TME_BUS_LANE_ROUTE(1), 3221: 3222: /* initiator maximum cycle size: 16 bits 3223: initiator address offset: 16 bits 3224: responder bus port size: 32 bits 3225: responder port least lane: D15-D8 3226: (responder port not correctly positioned for this initiator): */ 3227: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3228: /* D15-D8 */ TME_BUS_LANE_UNDEF, 3229: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 3230: /* D31-D24 */ TME_BUS_LANE_ROUTE(1), 3231: 3232: /* initiator maximum cycle size: 16 bits 3233: initiator address offset: 16 bits 3234: responder bus port size: 32 bits 3235: responder port least lane: D23-D16 3236: (responder port not correctly positioned for this initiator): */ 3237: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3238: /* D15-D8 */ TME_BUS_LANE_UNDEF, 3239: /* D23-D16 */ TME_BUS_LANE_ROUTE(0), 3240: /* D31-D24 */ TME_BUS_LANE_ROUTE(1), 3241: 3242: /* initiator maximum cycle size: 16 bits 3243: initiator address offset: 16 bits 3244: responder bus port size: 32 bits 3245: responder port least lane: D31-D24 3246: (responder port not correctly positioned for this initiator): */ 3247: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3248: /* D15-D8 */ TME_BUS_LANE_UNDEF, 3249: /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3250: /* D31-D24 */ TME_BUS_LANE_ROUTE(1), 3251: 3252: /* initiator maximum cycle size: 16 bits 3253: initiator address offset: 24 bits 3254: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 3255: responder bus port size: 8 bits 3256: responder port least lane: D7-D0: */ 3257: /* D7-D0 */ TME_BUS_LANE_ABORT, 3258: /* D15-D8 */ TME_BUS_LANE_ABORT, 3259: /* D23-D16 */ TME_BUS_LANE_ABORT, 3260: /* D31-D24 */ TME_BUS_LANE_ABORT, 3261: 3262: /* initiator maximum cycle size: 16 bits 3263: initiator address offset: 24 bits 3264: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 3265: responder bus port size: 8 bits 3266: responder port least lane: D15-D8: */ 3267: /* D7-D0 */ TME_BUS_LANE_ABORT, 3268: /* D15-D8 */ TME_BUS_LANE_ABORT, 3269: /* D23-D16 */ TME_BUS_LANE_ABORT, 3270: /* D31-D24 */ TME_BUS_LANE_ABORT, 3271: 3272: /* initiator maximum cycle size: 16 bits 3273: initiator address offset: 24 bits 3274: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 3275: responder bus port size: 8 bits 3276: responder port least lane: D23-D16: */ 3277: /* D7-D0 */ TME_BUS_LANE_ABORT, 3278: /* D15-D8 */ TME_BUS_LANE_ABORT, 3279: /* D23-D16 */ TME_BUS_LANE_ABORT, 3280: /* D31-D24 */ TME_BUS_LANE_ABORT, 3281: 3282: /* initiator maximum cycle size: 16 bits 3283: initiator address offset: 24 bits 3284: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 3285: responder bus port size: 8 bits 3286: responder port least lane: D31-D24: */ 3287: /* D7-D0 */ TME_BUS_LANE_ABORT, 3288: /* D15-D8 */ TME_BUS_LANE_ABORT, 3289: /* D23-D16 */ TME_BUS_LANE_ABORT, 3290: /* D31-D24 */ TME_BUS_LANE_ABORT, 3291: 3292: /* initiator maximum cycle size: 16 bits 3293: initiator address offset: 24 bits 3294: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 3295: responder bus port size: 16 bits 3296: responder port least lane: D7-D0: */ 3297: /* D7-D0 */ TME_BUS_LANE_ABORT, 3298: /* D15-D8 */ TME_BUS_LANE_ABORT, 3299: /* D23-D16 */ TME_BUS_LANE_ABORT, 3300: /* D31-D24 */ TME_BUS_LANE_ABORT, 3301: 3302: /* initiator maximum cycle size: 16 bits 3303: initiator address offset: 24 bits 3304: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 3305: responder bus port size: 16 bits 3306: responder port least lane: D15-D8: */ 3307: /* D7-D0 */ TME_BUS_LANE_ABORT, 3308: /* D15-D8 */ TME_BUS_LANE_ABORT, 3309: /* D23-D16 */ TME_BUS_LANE_ABORT, 3310: /* D31-D24 */ TME_BUS_LANE_ABORT, 3311: 3312: /* initiator maximum cycle size: 16 bits 3313: initiator address offset: 24 bits 3314: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 3315: responder bus port size: 16 bits 3316: responder port least lane: D23-D16: */ 3317: /* D7-D0 */ TME_BUS_LANE_ABORT, 3318: /* D15-D8 */ TME_BUS_LANE_ABORT, 3319: /* D23-D16 */ TME_BUS_LANE_ABORT, 3320: /* D31-D24 */ TME_BUS_LANE_ABORT, 3321: 3322: /* initiator maximum cycle size: 16 bits 3323: initiator address offset: 24 bits 3324: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 3325: responder bus port size: 16 bits 3326: responder port least lane: D31-D24 3327: (responder port not correctly positioned for this initiator): */ 3328: /* D7-D0 */ TME_BUS_LANE_ABORT, 3329: /* D15-D8 */ TME_BUS_LANE_ABORT, 3330: /* D23-D16 */ TME_BUS_LANE_ABORT, 3331: /* D31-D24 */ TME_BUS_LANE_ABORT, 3332: 3333: /* initiator maximum cycle size: 16 bits 3334: initiator address offset: 24 bits 3335: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 3336: responder bus port size: 32 bits 3337: responder port least lane: D7-D0: */ 3338: /* D7-D0 */ TME_BUS_LANE_ABORT, 3339: /* D15-D8 */ TME_BUS_LANE_ABORT, 3340: /* D23-D16 */ TME_BUS_LANE_ABORT, 3341: /* D31-D24 */ TME_BUS_LANE_ABORT, 3342: 3343: /* initiator maximum cycle size: 16 bits 3344: initiator address offset: 24 bits 3345: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 3346: responder bus port size: 32 bits 3347: responder port least lane: D15-D8 3348: (responder port not correctly positioned for this initiator): */ 3349: /* D7-D0 */ TME_BUS_LANE_ABORT, 3350: /* D15-D8 */ TME_BUS_LANE_ABORT, 3351: /* D23-D16 */ TME_BUS_LANE_ABORT, 3352: /* D31-D24 */ TME_BUS_LANE_ABORT, 3353: 3354: /* initiator maximum cycle size: 16 bits 3355: initiator address offset: 24 bits 3356: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 3357: responder bus port size: 32 bits 3358: responder port least lane: D23-D16 3359: (responder port not correctly positioned for this initiator): */ 3360: /* D7-D0 */ TME_BUS_LANE_ABORT, 3361: /* D15-D8 */ TME_BUS_LANE_ABORT, 3362: /* D23-D16 */ TME_BUS_LANE_ABORT, 3363: /* D31-D24 */ TME_BUS_LANE_ABORT, 3364: 3365: /* initiator maximum cycle size: 16 bits 3366: initiator address offset: 24 bits 3367: (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder) 3368: responder bus port size: 32 bits 3369: responder port least lane: D31-D24 3370: (responder port not correctly positioned for this initiator): */ 3371: /* D7-D0 */ TME_BUS_LANE_ABORT, 3372: /* D15-D8 */ TME_BUS_LANE_ABORT, 3373: /* D23-D16 */ TME_BUS_LANE_ABORT, 3374: /* D31-D24 */ TME_BUS_LANE_ABORT, 3375: 3376: /* initiator maximum cycle size: 24 bits 3377: initiator address offset: 0 bits 3378: responder bus port size: 8 bits 3379: responder port least lane: D7-D0: */ 3380: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 3381: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3382: /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3383: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3384: 3385: /* initiator maximum cycle size: 24 bits 3386: initiator address offset: 0 bits 3387: responder bus port size: 8 bits 3388: responder port least lane: D15-D8: */ 3389: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3390: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 3391: /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3392: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3393: 3394: /* initiator maximum cycle size: 24 bits 3395: initiator address offset: 0 bits 3396: responder bus port size: 8 bits 3397: responder port least lane: D23-D16: */ 3398: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3399: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3400: /* D23-D16 */ TME_BUS_LANE_ROUTE(2), 3401: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3402: 3403: /* initiator maximum cycle size: 24 bits 3404: initiator address offset: 0 bits 3405: responder bus port size: 8 bits 3406: responder port least lane: D31-D24: */ 3407: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3408: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3409: /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3410: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3411: 3412: /* initiator maximum cycle size: 24 bits 3413: initiator address offset: 0 bits 3414: responder bus port size: 16 bits 3415: responder port least lane: D7-D0: */ 3416: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 3417: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 3418: /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3419: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3420: 3421: /* initiator maximum cycle size: 24 bits 3422: initiator address offset: 0 bits 3423: responder bus port size: 16 bits 3424: responder port least lane: D15-D8: */ 3425: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3426: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 3427: /* D23-D16 */ TME_BUS_LANE_ROUTE(2), 3428: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3429: 3430: /* initiator maximum cycle size: 24 bits 3431: initiator address offset: 0 bits 3432: responder bus port size: 16 bits 3433: responder port least lane: D23-D16: */ 3434: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3435: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3436: /* D23-D16 */ TME_BUS_LANE_ROUTE(2), 3437: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3438: 3439: /* initiator maximum cycle size: 24 bits 3440: initiator address offset: 0 bits 3441: responder bus port size: 16 bits 3442: responder port least lane: D31-D24 3443: (responder port not correctly positioned for this initiator): */ 3444: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3445: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3446: /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3447: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3448: 3449: /* initiator maximum cycle size: 24 bits 3450: initiator address offset: 0 bits 3451: responder bus port size: 32 bits 3452: responder port least lane: D7-D0: */ 3453: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 3454: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 3455: /* D23-D16 */ TME_BUS_LANE_ROUTE(2), 3456: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3457: 3458: /* initiator maximum cycle size: 24 bits 3459: initiator address offset: 0 bits 3460: responder bus port size: 32 bits 3461: responder port least lane: D15-D8 3462: (responder port not correctly positioned for this initiator): */ 3463: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3464: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 3465: /* D23-D16 */ TME_BUS_LANE_ROUTE(2), 3466: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3467: 3468: /* initiator maximum cycle size: 24 bits 3469: initiator address offset: 0 bits 3470: responder bus port size: 32 bits 3471: responder port least lane: D23-D16 3472: (responder port not correctly positioned for this initiator): */ 3473: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3474: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3475: /* D23-D16 */ TME_BUS_LANE_ROUTE(2), 3476: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3477: 3478: /* initiator maximum cycle size: 24 bits 3479: initiator address offset: 0 bits 3480: responder bus port size: 32 bits 3481: responder port least lane: D31-D24 3482: (responder port not correctly positioned for this initiator): */ 3483: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3484: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3485: /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3486: /* D31-D24 */ TME_BUS_LANE_UNDEF, 3487: 3488: /* initiator maximum cycle size: 24 bits 3489: initiator address offset: 8 bits 3490: responder bus port size: 8 bits 3491: responder port least lane: D7-D0: */ 3492: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3493: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3494: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3495: /* D31-D24 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3496: 3497: /* initiator maximum cycle size: 24 bits 3498: initiator address offset: 8 bits 3499: responder bus port size: 8 bits 3500: responder port least lane: D15-D8: */ 3501: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3502: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 3503: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3504: /* D31-D24 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3505: 3506: /* initiator maximum cycle size: 24 bits 3507: initiator address offset: 8 bits 3508: responder bus port size: 8 bits 3509: responder port least lane: D23-D16: */ 3510: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3511: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3512: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 3513: /* D31-D24 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3514: 3515: /* initiator maximum cycle size: 24 bits 3516: initiator address offset: 8 bits 3517: responder bus port size: 8 bits 3518: responder port least lane: D31-D24: */ 3519: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3520: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3521: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3522: /* D31-D24 */ TME_BUS_LANE_ROUTE(2), 3523: 3524: /* initiator maximum cycle size: 24 bits 3525: initiator address offset: 8 bits 3526: responder bus port size: 16 bits 3527: responder port least lane: D7-D0: */ 3528: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3529: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 3530: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3531: /* D31-D24 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3532: 3533: /* initiator maximum cycle size: 24 bits 3534: initiator address offset: 8 bits 3535: responder bus port size: 16 bits 3536: responder port least lane: D15-D8: */ 3537: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3538: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 3539: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 3540: /* D31-D24 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3541: 3542: /* initiator maximum cycle size: 24 bits 3543: initiator address offset: 8 bits 3544: responder bus port size: 16 bits 3545: responder port least lane: D23-D16: */ 3546: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3547: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3548: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 3549: /* D31-D24 */ TME_BUS_LANE_ROUTE(2), 3550: 3551: /* initiator maximum cycle size: 24 bits 3552: initiator address offset: 8 bits 3553: responder bus port size: 16 bits 3554: responder port least lane: D31-D24 3555: (responder port not correctly positioned for this initiator): */ 3556: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3557: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3558: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3559: /* D31-D24 */ TME_BUS_LANE_ROUTE(2), 3560: 3561: /* initiator maximum cycle size: 24 bits 3562: initiator address offset: 8 bits 3563: responder bus port size: 32 bits 3564: responder port least lane: D7-D0: */ 3565: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3566: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 3567: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 3568: /* D31-D24 */ TME_BUS_LANE_ROUTE(2), 3569: 3570: /* initiator maximum cycle size: 24 bits 3571: initiator address offset: 8 bits 3572: responder bus port size: 32 bits 3573: responder port least lane: D15-D8 3574: (responder port not correctly positioned for this initiator): */ 3575: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3576: /* D15-D8 */ TME_BUS_LANE_ROUTE(0), 3577: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 3578: /* D31-D24 */ TME_BUS_LANE_ROUTE(2), 3579: 3580: /* initiator maximum cycle size: 24 bits 3581: initiator address offset: 8 bits 3582: responder bus port size: 32 bits 3583: responder port least lane: D23-D16 3584: (responder port not correctly positioned for this initiator): */ 3585: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3586: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3587: /* D23-D16 */ TME_BUS_LANE_ROUTE(1), 3588: /* D31-D24 */ TME_BUS_LANE_ROUTE(2), 3589: 3590: /* initiator maximum cycle size: 24 bits 3591: initiator address offset: 8 bits 3592: responder bus port size: 32 bits 3593: responder port least lane: D31-D24 3594: (responder port not correctly positioned for this initiator): */ 3595: /* D7-D0 */ TME_BUS_LANE_UNDEF, 3596: /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3597: /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3598: /* D31-D24 */ TME_BUS_LANE_ROUTE(2), 3599: 3600: /* initiator maximum cycle size: 24 bits 3601: initiator address offset: 16 bits 3602: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 3603: responder bus port size: 8 bits 3604: responder port least lane: D7-D0: */ 3605: /* D7-D0 */ TME_BUS_LANE_ABORT, 3606: /* D15-D8 */ TME_BUS_LANE_ABORT, 3607: /* D23-D16 */ TME_BUS_LANE_ABORT, 3608: /* D31-D24 */ TME_BUS_LANE_ABORT, 3609: 3610: /* initiator maximum cycle size: 24 bits 3611: initiator address offset: 16 bits 3612: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 3613: responder bus port size: 8 bits 3614: responder port least lane: D15-D8: */ 3615: /* D7-D0 */ TME_BUS_LANE_ABORT, 3616: /* D15-D8 */ TME_BUS_LANE_ABORT, 3617: /* D23-D16 */ TME_BUS_LANE_ABORT, 3618: /* D31-D24 */ TME_BUS_LANE_ABORT, 3619: 3620: /* initiator maximum cycle size: 24 bits 3621: initiator address offset: 16 bits 3622: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 3623: responder bus port size: 8 bits 3624: responder port least lane: D23-D16: */ 3625: /* D7-D0 */ TME_BUS_LANE_ABORT, 3626: /* D15-D8 */ TME_BUS_LANE_ABORT, 3627: /* D23-D16 */ TME_BUS_LANE_ABORT, 3628: /* D31-D24 */ TME_BUS_LANE_ABORT, 3629: 3630: /* initiator maximum cycle size: 24 bits 3631: initiator address offset: 16 bits 3632: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 3633: responder bus port size: 8 bits 3634: responder port least lane: D31-D24: */ 3635: /* D7-D0 */ TME_BUS_LANE_ABORT, 3636: /* D15-D8 */ TME_BUS_LANE_ABORT, 3637: /* D23-D16 */ TME_BUS_LANE_ABORT, 3638: /* D31-D24 */ TME_BUS_LANE_ABORT, 3639: 3640: /* initiator maximum cycle size: 24 bits 3641: initiator address offset: 16 bits 3642: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 3643: responder bus port size: 16 bits 3644: responder port least lane: D7-D0: */ 3645: /* D7-D0 */ TME_BUS_LANE_ABORT, 3646: /* D15-D8 */ TME_BUS_LANE_ABORT, 3647: /* D23-D16 */ TME_BUS_LANE_ABORT, 3648: /* D31-D24 */ TME_BUS_LANE_ABORT, 3649: 3650: /* initiator maximum cycle size: 24 bits 3651: initiator address offset: 16 bits 3652: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 3653: responder bus port size: 16 bits 3654: responder port least lane: D15-D8: */ 3655: /* D7-D0 */ TME_BUS_LANE_ABORT, 3656: /* D15-D8 */ TME_BUS_LANE_ABORT, 3657: /* D23-D16 */ TME_BUS_LANE_ABORT, 3658: /* D31-D24 */ TME_BUS_LANE_ABORT, 3659: 3660: /* initiator maximum cycle size: 24 bits 3661: initiator address offset: 16 bits 3662: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 3663: responder bus port size: 16 bits 3664: responder port least lane: D23-D16: */ 3665: /* D7-D0 */ TME_BUS_LANE_ABORT, 3666: /* D15-D8 */ TME_BUS_LANE_ABORT, 3667: /* D23-D16 */ TME_BUS_LANE_ABORT, 3668: /* D31-D24 */ TME_BUS_LANE_ABORT, 3669: 3670: /* initiator maximum cycle size: 24 bits 3671: initiator address offset: 16 bits 3672: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 3673: responder bus port size: 16 bits 3674: responder port least lane: D31-D24 3675: (responder port not correctly positioned for this initiator): */ 3676: /* D7-D0 */ TME_BUS_LANE_ABORT, 3677: /* D15-D8 */ TME_BUS_LANE_ABORT, 3678: /* D23-D16 */ TME_BUS_LANE_ABORT, 3679: /* D31-D24 */ TME_BUS_LANE_ABORT, 3680: 3681: /* initiator maximum cycle size: 24 bits 3682: initiator address offset: 16 bits 3683: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 3684: responder bus port size: 32 bits 3685: responder port least lane: D7-D0: */ 3686: /* D7-D0 */ TME_BUS_LANE_ABORT, 3687: /* D15-D8 */ TME_BUS_LANE_ABORT, 3688: /* D23-D16 */ TME_BUS_LANE_ABORT, 3689: /* D31-D24 */ TME_BUS_LANE_ABORT, 3690: 3691: /* initiator maximum cycle size: 24 bits 3692: initiator address offset: 16 bits 3693: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 3694: responder bus port size: 32 bits 3695: responder port least lane: D15-D8 3696: (responder port not correctly positioned for this initiator): */ 3697: /* D7-D0 */ TME_BUS_LANE_ABORT, 3698: /* D15-D8 */ TME_BUS_LANE_ABORT, 3699: /* D23-D16 */ TME_BUS_LANE_ABORT, 3700: /* D31-D24 */ TME_BUS_LANE_ABORT, 3701: 3702: /* initiator maximum cycle size: 24 bits 3703: initiator address offset: 16 bits 3704: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 3705: responder bus port size: 32 bits 3706: responder port least lane: D23-D16 3707: (responder port not correctly positioned for this initiator): */ 3708: /* D7-D0 */ TME_BUS_LANE_ABORT, 3709: /* D15-D8 */ TME_BUS_LANE_ABORT, 3710: /* D23-D16 */ TME_BUS_LANE_ABORT, 3711: /* D31-D24 */ TME_BUS_LANE_ABORT, 3712: 3713: /* initiator maximum cycle size: 24 bits 3714: initiator address offset: 16 bits 3715: (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder) 3716: responder bus port size: 32 bits 3717: responder port least lane: D31-D24 3718: (responder port not correctly positioned for this initiator): */ 3719: /* D7-D0 */ TME_BUS_LANE_ABORT, 3720: /* D15-D8 */ TME_BUS_LANE_ABORT, 3721: /* D23-D16 */ TME_BUS_LANE_ABORT, 3722: /* D31-D24 */ TME_BUS_LANE_ABORT, 3723: 3724: /* initiator maximum cycle size: 24 bits 3725: initiator address offset: 24 bits 3726: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 3727: responder bus port size: 8 bits 3728: responder port least lane: D7-D0: */ 3729: /* D7-D0 */ TME_BUS_LANE_ABORT, 3730: /* D15-D8 */ TME_BUS_LANE_ABORT, 3731: /* D23-D16 */ TME_BUS_LANE_ABORT, 3732: /* D31-D24 */ TME_BUS_LANE_ABORT, 3733: 3734: /* initiator maximum cycle size: 24 bits 3735: initiator address offset: 24 bits 3736: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 3737: responder bus port size: 8 bits 3738: responder port least lane: D15-D8: */ 3739: /* D7-D0 */ TME_BUS_LANE_ABORT, 3740: /* D15-D8 */ TME_BUS_LANE_ABORT, 3741: /* D23-D16 */ TME_BUS_LANE_ABORT, 3742: /* D31-D24 */ TME_BUS_LANE_ABORT, 3743: 3744: /* initiator maximum cycle size: 24 bits 3745: initiator address offset: 24 bits 3746: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 3747: responder bus port size: 8 bits 3748: responder port least lane: D23-D16: */ 3749: /* D7-D0 */ TME_BUS_LANE_ABORT, 3750: /* D15-D8 */ TME_BUS_LANE_ABORT, 3751: /* D23-D16 */ TME_BUS_LANE_ABORT, 3752: /* D31-D24 */ TME_BUS_LANE_ABORT, 3753: 3754: /* initiator maximum cycle size: 24 bits 3755: initiator address offset: 24 bits 3756: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 3757: responder bus port size: 8 bits 3758: responder port least lane: D31-D24: */ 3759: /* D7-D0 */ TME_BUS_LANE_ABORT, 3760: /* D15-D8 */ TME_BUS_LANE_ABORT, 3761: /* D23-D16 */ TME_BUS_LANE_ABORT, 3762: /* D31-D24 */ TME_BUS_LANE_ABORT, 3763: 3764: /* initiator maximum cycle size: 24 bits 3765: initiator address offset: 24 bits 3766: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 3767: responder bus port size: 16 bits 3768: responder port least lane: D7-D0: */ 3769: /* D7-D0 */ TME_BUS_LANE_ABORT, 3770: /* D15-D8 */ TME_BUS_LANE_ABORT, 3771: /* D23-D16 */ TME_BUS_LANE_ABORT, 3772: /* D31-D24 */ TME_BUS_LANE_ABORT, 3773: 3774: /* initiator maximum cycle size: 24 bits 3775: initiator address offset: 24 bits 3776: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 3777: responder bus port size: 16 bits 3778: responder port least lane: D15-D8: */ 3779: /* D7-D0 */ TME_BUS_LANE_ABORT, 3780: /* D15-D8 */ TME_BUS_LANE_ABORT, 3781: /* D23-D16 */ TME_BUS_LANE_ABORT, 3782: /* D31-D24 */ TME_BUS_LANE_ABORT, 3783: 3784: /* initiator maximum cycle size: 24 bits 3785: initiator address offset: 24 bits 3786: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 3787: responder bus port size: 16 bits 3788: responder port least lane: D23-D16: */ 3789: /* D7-D0 */ TME_BUS_LANE_ABORT, 3790: /* D15-D8 */ TME_BUS_LANE_ABORT, 3791: /* D23-D16 */ TME_BUS_LANE_ABORT, 3792: /* D31-D24 */ TME_BUS_LANE_ABORT, 3793: 3794: /* initiator maximum cycle size: 24 bits 3795: initiator address offset: 24 bits 3796: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 3797: responder bus port size: 16 bits 3798: responder port least lane: D31-D24 3799: (responder port not correctly positioned for this initiator): */ 3800: /* D7-D0 */ TME_BUS_LANE_ABORT, 3801: /* D15-D8 */ TME_BUS_LANE_ABORT, 3802: /* D23-D16 */ TME_BUS_LANE_ABORT, 3803: /* D31-D24 */ TME_BUS_LANE_ABORT, 3804: 3805: /* initiator maximum cycle size: 24 bits 3806: initiator address offset: 24 bits 3807: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 3808: responder bus port size: 32 bits 3809: responder port least lane: D7-D0: */ 3810: /* D7-D0 */ TME_BUS_LANE_ABORT, 3811: /* D15-D8 */ TME_BUS_LANE_ABORT, 3812: /* D23-D16 */ TME_BUS_LANE_ABORT, 3813: /* D31-D24 */ TME_BUS_LANE_ABORT, 3814: 3815: /* initiator maximum cycle size: 24 bits 3816: initiator address offset: 24 bits 3817: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 3818: responder bus port size: 32 bits 3819: responder port least lane: D15-D8 3820: (responder port not correctly positioned for this initiator): */ 3821: /* D7-D0 */ TME_BUS_LANE_ABORT, 3822: /* D15-D8 */ TME_BUS_LANE_ABORT, 3823: /* D23-D16 */ TME_BUS_LANE_ABORT, 3824: /* D31-D24 */ TME_BUS_LANE_ABORT, 3825: 3826: /* initiator maximum cycle size: 24 bits 3827: initiator address offset: 24 bits 3828: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 3829: responder bus port size: 32 bits 3830: responder port least lane: D23-D16 3831: (responder port not correctly positioned for this initiator): */ 3832: /* D7-D0 */ TME_BUS_LANE_ABORT, 3833: /* D15-D8 */ TME_BUS_LANE_ABORT, 3834: /* D23-D16 */ TME_BUS_LANE_ABORT, 3835: /* D31-D24 */ TME_BUS_LANE_ABORT, 3836: 3837: /* initiator maximum cycle size: 24 bits 3838: initiator address offset: 24 bits 3839: (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder) 3840: responder bus port size: 32 bits 3841: responder port least lane: D31-D24 3842: (responder port not correctly positioned for this initiator): */ 3843: /* D7-D0 */ TME_BUS_LANE_ABORT, 3844: /* D15-D8 */ TME_BUS_LANE_ABORT, 3845: /* D23-D16 */ TME_BUS_LANE_ABORT, 3846: /* D31-D24 */ TME_BUS_LANE_ABORT, 3847: 3848: /* initiator maximum cycle size: 32 bits 3849: initiator address offset: 0 bits 3850: responder bus port size: 8 bits 3851: responder port least lane: D7-D0: */ 3852: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 3853: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3854: /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3855: /* D31-D24 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN, 3856: 3857: /* initiator maximum cycle size: 32 bits 3858: initiator address offset: 0 bits 3859: responder bus port size: 8 bits 3860: responder port least lane: D15-D8: */ 3861: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3862: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 3863: /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3864: /* D31-D24 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN, 3865: 3866: /* initiator maximum cycle size: 32 bits 3867: initiator address offset: 0 bits 3868: responder bus port size: 8 bits 3869: responder port least lane: D23-D16: */ 3870: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3871: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3872: /* D23-D16 */ TME_BUS_LANE_ROUTE(2), 3873: /* D31-D24 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN, 3874: 3875: /* initiator maximum cycle size: 32 bits 3876: initiator address offset: 0 bits 3877: responder bus port size: 8 bits 3878: responder port least lane: D31-D24: */ 3879: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3880: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3881: /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3882: /* D31-D24 */ TME_BUS_LANE_ROUTE(3), 3883: 3884: /* initiator maximum cycle size: 32 bits 3885: initiator address offset: 0 bits 3886: responder bus port size: 16 bits 3887: responder port least lane: D7-D0: */ 3888: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 3889: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 3890: /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3891: /* D31-D24 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN, 3892: 3893: /* initiator maximum cycle size: 32 bits 3894: initiator address offset: 0 bits 3895: responder bus port size: 16 bits 3896: responder port least lane: D15-D8: */ 3897: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3898: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 3899: /* D23-D16 */ TME_BUS_LANE_ROUTE(2), 3900: /* D31-D24 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN, 3901: 3902: /* initiator maximum cycle size: 32 bits 3903: initiator address offset: 0 bits 3904: responder bus port size: 16 bits 3905: responder port least lane: D23-D16: */ 3906: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3907: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3908: /* D23-D16 */ TME_BUS_LANE_ROUTE(2), 3909: /* D31-D24 */ TME_BUS_LANE_ROUTE(3), 3910: 3911: /* initiator maximum cycle size: 32 bits 3912: initiator address offset: 0 bits 3913: responder bus port size: 16 bits 3914: responder port least lane: D31-D24 3915: (responder port not correctly positioned for this initiator): */ 3916: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3917: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3918: /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3919: /* D31-D24 */ TME_BUS_LANE_ROUTE(3), 3920: 3921: /* initiator maximum cycle size: 32 bits 3922: initiator address offset: 0 bits 3923: responder bus port size: 32 bits 3924: responder port least lane: D7-D0: */ 3925: /* D7-D0 */ TME_BUS_LANE_ROUTE(0), 3926: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 3927: /* D23-D16 */ TME_BUS_LANE_ROUTE(2), 3928: /* D31-D24 */ TME_BUS_LANE_ROUTE(3), 3929: 3930: /* initiator maximum cycle size: 32 bits 3931: initiator address offset: 0 bits 3932: responder bus port size: 32 bits 3933: responder port least lane: D15-D8 3934: (responder port not correctly positioned for this initiator): */ 3935: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3936: /* D15-D8 */ TME_BUS_LANE_ROUTE(1), 3937: /* D23-D16 */ TME_BUS_LANE_ROUTE(2), 3938: /* D31-D24 */ TME_BUS_LANE_ROUTE(3), 3939: 3940: /* initiator maximum cycle size: 32 bits 3941: initiator address offset: 0 bits 3942: responder bus port size: 32 bits 3943: responder port least lane: D23-D16 3944: (responder port not correctly positioned for this initiator): */ 3945: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3946: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3947: /* D23-D16 */ TME_BUS_LANE_ROUTE(2), 3948: /* D31-D24 */ TME_BUS_LANE_ROUTE(3), 3949: 3950: /* initiator maximum cycle size: 32 bits 3951: initiator address offset: 0 bits 3952: responder bus port size: 32 bits 3953: responder port least lane: D31-D24 3954: (responder port not correctly positioned for this initiator): */ 3955: /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN, 3956: /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN, 3957: /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN, 3958: /* D31-D24 */ TME_BUS_LANE_ROUTE(3), 3959: 3960: /* initiator maximum cycle size: 32 bits 3961: initiator address offset: 8 bits 3962: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 3963: responder bus port size: 8 bits 3964: responder port least lane: D7-D0: */ 3965: /* D7-D0 */ TME_BUS_LANE_ABORT, 3966: /* D15-D8 */ TME_BUS_LANE_ABORT, 3967: /* D23-D16 */ TME_BUS_LANE_ABORT, 3968: /* D31-D24 */ TME_BUS_LANE_ABORT, 3969: 3970: /* initiator maximum cycle size: 32 bits 3971: initiator address offset: 8 bits 3972: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 3973: responder bus port size: 8 bits 3974: responder port least lane: D15-D8: */ 3975: /* D7-D0 */ TME_BUS_LANE_ABORT, 3976: /* D15-D8 */ TME_BUS_LANE_ABORT, 3977: /* D23-D16 */ TME_BUS_LANE_ABORT, 3978: /* D31-D24 */ TME_BUS_LANE_ABORT, 3979: 3980: /* initiator maximum cycle size: 32 bits 3981: initiator address offset: 8 bits 3982: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 3983: responder bus port size: 8 bits 3984: responder port least lane: D23-D16: */ 3985: /* D7-D0 */ TME_BUS_LANE_ABORT, 3986: /* D15-D8 */ TME_BUS_LANE_ABORT, 3987: /* D23-D16 */ TME_BUS_LANE_ABORT, 3988: /* D31-D24 */ TME_BUS_LANE_ABORT, 3989: 3990: /* initiator maximum cycle size: 32 bits 3991: initiator address offset: 8 bits 3992: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 3993: responder bus port size: 8 bits 3994: responder port least lane: D31-D24: */ 3995: /* D7-D0 */ TME_BUS_LANE_ABORT, 3996: /* D15-D8 */ TME_BUS_LANE_ABORT, 3997: /* D23-D16 */ TME_BUS_LANE_ABORT, 3998: /* D31-D24 */ TME_BUS_LANE_ABORT, 3999: 4000: /* initiator maximum cycle size: 32 bits 4001: initiator address offset: 8 bits 4002: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 4003: responder bus port size: 16 bits 4004: responder port least lane: D7-D0: */ 4005: /* D7-D0 */ TME_BUS_LANE_ABORT, 4006: /* D15-D8 */ TME_BUS_LANE_ABORT, 4007: /* D23-D16 */ TME_BUS_LANE_ABORT, 4008: /* D31-D24 */ TME_BUS_LANE_ABORT, 4009: 4010: /* initiator maximum cycle size: 32 bits 4011: initiator address offset: 8 bits 4012: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 4013: responder bus port size: 16 bits 4014: responder port least lane: D15-D8: */ 4015: /* D7-D0 */ TME_BUS_LANE_ABORT, 4016: /* D15-D8 */ TME_BUS_LANE_ABORT, 4017: /* D23-D16 */ TME_BUS_LANE_ABORT, 4018: /* D31-D24 */ TME_BUS_LANE_ABORT, 4019: 4020: /* initiator maximum cycle size: 32 bits 4021: initiator address offset: 8 bits 4022: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 4023: responder bus port size: 16 bits 4024: responder port least lane: D23-D16: */ 4025: /* D7-D0 */ TME_BUS_LANE_ABORT, 4026: /* D15-D8 */ TME_BUS_LANE_ABORT, 4027: /* D23-D16 */ TME_BUS_LANE_ABORT, 4028: /* D31-D24 */ TME_BUS_LANE_ABORT, 4029: 4030: /* initiator maximum cycle size: 32 bits 4031: initiator address offset: 8 bits 4032: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 4033: responder bus port size: 16 bits 4034: responder port least lane: D31-D24 4035: (responder port not correctly positioned for this initiator): */ 4036: /* D7-D0 */ TME_BUS_LANE_ABORT, 4037: /* D15-D8 */ TME_BUS_LANE_ABORT, 4038: /* D23-D16 */ TME_BUS_LANE_ABORT, 4039: /* D31-D24 */ TME_BUS_LANE_ABORT, 4040: 4041: /* initiator maximum cycle size: 32 bits 4042: initiator address offset: 8 bits 4043: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 4044: responder bus port size: 32 bits 4045: responder port least lane: D7-D0: */ 4046: /* D7-D0 */ TME_BUS_LANE_ABORT, 4047: /* D15-D8 */ TME_BUS_LANE_ABORT, 4048: /* D23-D16 */ TME_BUS_LANE_ABORT, 4049: /* D31-D24 */ TME_BUS_LANE_ABORT, 4050: 4051: /* initiator maximum cycle size: 32 bits 4052: initiator address offset: 8 bits 4053: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 4054: responder bus port size: 32 bits 4055: responder port least lane: D15-D8 4056: (responder port not correctly positioned for this initiator): */ 4057: /* D7-D0 */ TME_BUS_LANE_ABORT, 4058: /* D15-D8 */ TME_BUS_LANE_ABORT, 4059: /* D23-D16 */ TME_BUS_LANE_ABORT, 4060: /* D31-D24 */ TME_BUS_LANE_ABORT, 4061: 4062: /* initiator maximum cycle size: 32 bits 4063: initiator address offset: 8 bits 4064: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 4065: responder bus port size: 32 bits 4066: responder port least lane: D23-D16 4067: (responder port not correctly positioned for this initiator): */ 4068: /* D7-D0 */ TME_BUS_LANE_ABORT, 4069: /* D15-D8 */ TME_BUS_LANE_ABORT, 4070: /* D23-D16 */ TME_BUS_LANE_ABORT, 4071: /* D31-D24 */ TME_BUS_LANE_ABORT, 4072: 4073: /* initiator maximum cycle size: 32 bits 4074: initiator address offset: 8 bits 4075: (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder) 4076: responder bus port size: 32 bits 4077: responder port least lane: D31-D24 4078: (responder port not correctly positioned for this initiator): */ 4079: /* D7-D0 */ TME_BUS_LANE_ABORT, 4080: /* D15-D8 */ TME_BUS_LANE_ABORT, 4081: /* D23-D16 */ TME_BUS_LANE_ABORT, 4082: /* D31-D24 */ TME_BUS_LANE_ABORT, 4083: 4084: /* initiator maximum cycle size: 32 bits 4085: initiator address offset: 16 bits 4086: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 4087: responder bus port size: 8 bits 4088: responder port least lane: D7-D0: */ 4089: /* D7-D0 */ TME_BUS_LANE_ABORT, 4090: /* D15-D8 */ TME_BUS_LANE_ABORT, 4091: /* D23-D16 */ TME_BUS_LANE_ABORT, 4092: /* D31-D24 */ TME_BUS_LANE_ABORT, 4093: 4094: /* initiator maximum cycle size: 32 bits 4095: initiator address offset: 16 bits 4096: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 4097: responder bus port size: 8 bits 4098: responder port least lane: D15-D8: */ 4099: /* D7-D0 */ TME_BUS_LANE_ABORT, 4100: /* D15-D8 */ TME_BUS_LANE_ABORT, 4101: /* D23-D16 */ TME_BUS_LANE_ABORT, 4102: /* D31-D24 */ TME_BUS_LANE_ABORT, 4103: 4104: /* initiator maximum cycle size: 32 bits 4105: initiator address offset: 16 bits 4106: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 4107: responder bus port size: 8 bits 4108: responder port least lane: D23-D16: */ 4109: /* D7-D0 */ TME_BUS_LANE_ABORT, 4110: /* D15-D8 */ TME_BUS_LANE_ABORT, 4111: /* D23-D16 */ TME_BUS_LANE_ABORT, 4112: /* D31-D24 */ TME_BUS_LANE_ABORT, 4113: 4114: /* initiator maximum cycle size: 32 bits 4115: initiator address offset: 16 bits 4116: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 4117: responder bus port size: 8 bits 4118: responder port least lane: D31-D24: */ 4119: /* D7-D0 */ TME_BUS_LANE_ABORT, 4120: /* D15-D8 */ TME_BUS_LANE_ABORT, 4121: /* D23-D16 */ TME_BUS_LANE_ABORT, 4122: /* D31-D24 */ TME_BUS_LANE_ABORT, 4123: 4124: /* initiator maximum cycle size: 32 bits 4125: initiator address offset: 16 bits 4126: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 4127: responder bus port size: 16 bits 4128: responder port least lane: D7-D0: */ 4129: /* D7-D0 */ TME_BUS_LANE_ABORT, 4130: /* D15-D8 */ TME_BUS_LANE_ABORT, 4131: /* D23-D16 */ TME_BUS_LANE_ABORT, 4132: /* D31-D24 */ TME_BUS_LANE_ABORT, 4133: 4134: /* initiator maximum cycle size: 32 bits 4135: initiator address offset: 16 bits 4136: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 4137: responder bus port size: 16 bits 4138: responder port least lane: D15-D8: */ 4139: /* D7-D0 */ TME_BUS_LANE_ABORT, 4140: /* D15-D8 */ TME_BUS_LANE_ABORT, 4141: /* D23-D16 */ TME_BUS_LANE_ABORT, 4142: /* D31-D24 */ TME_BUS_LANE_ABORT, 4143: 4144: /* initiator maximum cycle size: 32 bits 4145: initiator address offset: 16 bits 4146: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 4147: responder bus port size: 16 bits 4148: responder port least lane: D23-D16: */ 4149: /* D7-D0 */ TME_BUS_LANE_ABORT, 4150: /* D15-D8 */ TME_BUS_LANE_ABORT, 4151: /* D23-D16 */ TME_BUS_LANE_ABORT, 4152: /* D31-D24 */ TME_BUS_LANE_ABORT, 4153: 4154: /* initiator maximum cycle size: 32 bits 4155: initiator address offset: 16 bits 4156: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 4157: responder bus port size: 16 bits 4158: responder port least lane: D31-D24 4159: (responder port not correctly positioned for this initiator): */ 4160: /* D7-D0 */ TME_BUS_LANE_ABORT, 4161: /* D15-D8 */ TME_BUS_LANE_ABORT, 4162: /* D23-D16 */ TME_BUS_LANE_ABORT, 4163: /* D31-D24 */ TME_BUS_LANE_ABORT, 4164: 4165: /* initiator maximum cycle size: 32 bits 4166: initiator address offset: 16 bits 4167: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 4168: responder bus port size: 32 bits 4169: responder port least lane: D7-D0: */ 4170: /* D7-D0 */ TME_BUS_LANE_ABORT, 4171: /* D15-D8 */ TME_BUS_LANE_ABORT, 4172: /* D23-D16 */ TME_BUS_LANE_ABORT, 4173: /* D31-D24 */ TME_BUS_LANE_ABORT, 4174: 4175: /* initiator maximum cycle size: 32 bits 4176: initiator address offset: 16 bits 4177: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 4178: responder bus port size: 32 bits 4179: responder port least lane: D15-D8 4180: (responder port not correctly positioned for this initiator): */ 4181: /* D7-D0 */ TME_BUS_LANE_ABORT, 4182: /* D15-D8 */ TME_BUS_LANE_ABORT, 4183: /* D23-D16 */ TME_BUS_LANE_ABORT, 4184: /* D31-D24 */ TME_BUS_LANE_ABORT, 4185: 4186: /* initiator maximum cycle size: 32 bits 4187: initiator address offset: 16 bits 4188: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 4189: responder bus port size: 32 bits 4190: responder port least lane: D23-D16 4191: (responder port not correctly positioned for this initiator): */ 4192: /* D7-D0 */ TME_BUS_LANE_ABORT, 4193: /* D15-D8 */ TME_BUS_LANE_ABORT, 4194: /* D23-D16 */ TME_BUS_LANE_ABORT, 4195: /* D31-D24 */ TME_BUS_LANE_ABORT, 4196: 4197: /* initiator maximum cycle size: 32 bits 4198: initiator address offset: 16 bits 4199: (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder) 4200: responder bus port size: 32 bits 4201: responder port least lane: D31-D24 4202: (responder port not correctly positioned for this initiator): */ 4203: /* D7-D0 */ TME_BUS_LANE_ABORT, 4204: /* D15-D8 */ TME_BUS_LANE_ABORT, 4205: /* D23-D16 */ TME_BUS_LANE_ABORT, 4206: /* D31-D24 */ TME_BUS_LANE_ABORT, 4207: 4208: /* initiator maximum cycle size: 32 bits 4209: initiator address offset: 24 bits 4210: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 4211: responder bus port size: 8 bits 4212: responder port least lane: D7-D0: */ 4213: /* D7-D0 */ TME_BUS_LANE_ABORT, 4214: /* D15-D8 */ TME_BUS_LANE_ABORT, 4215: /* D23-D16 */ TME_BUS_LANE_ABORT, 4216: /* D31-D24 */ TME_BUS_LANE_ABORT, 4217: 4218: /* initiator maximum cycle size: 32 bits 4219: initiator address offset: 24 bits 4220: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 4221: responder bus port size: 8 bits 4222: responder port least lane: D15-D8: */ 4223: /* D7-D0 */ TME_BUS_LANE_ABORT, 4224: /* D15-D8 */ TME_BUS_LANE_ABORT, 4225: /* D23-D16 */ TME_BUS_LANE_ABORT, 4226: /* D31-D24 */ TME_BUS_LANE_ABORT, 4227: 4228: /* initiator maximum cycle size: 32 bits 4229: initiator address offset: 24 bits 4230: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 4231: responder bus port size: 8 bits 4232: responder port least lane: D23-D16: */ 4233: /* D7-D0 */ TME_BUS_LANE_ABORT, 4234: /* D15-D8 */ TME_BUS_LANE_ABORT, 4235: /* D23-D16 */ TME_BUS_LANE_ABORT, 4236: /* D31-D24 */ TME_BUS_LANE_ABORT, 4237: 4238: /* initiator maximum cycle size: 32 bits 4239: initiator address offset: 24 bits 4240: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 4241: responder bus port size: 8 bits 4242: responder port least lane: D31-D24: */ 4243: /* D7-D0 */ TME_BUS_LANE_ABORT, 4244: /* D15-D8 */ TME_BUS_LANE_ABORT, 4245: /* D23-D16 */ TME_BUS_LANE_ABORT, 4246: /* D31-D24 */ TME_BUS_LANE_ABORT, 4247: 4248: /* initiator maximum cycle size: 32 bits 4249: initiator address offset: 24 bits 4250: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 4251: responder bus port size: 16 bits 4252: responder port least lane: D7-D0: */ 4253: /* D7-D0 */ TME_BUS_LANE_ABORT, 4254: /* D15-D8 */ TME_BUS_LANE_ABORT, 4255: /* D23-D16 */ TME_BUS_LANE_ABORT, 4256: /* D31-D24 */ TME_BUS_LANE_ABORT, 4257: 4258: /* initiator maximum cycle size: 32 bits 4259: initiator address offset: 24 bits 4260: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 4261: responder bus port size: 16 bits 4262: responder port least lane: D15-D8: */ 4263: /* D7-D0 */ TME_BUS_LANE_ABORT, 4264: /* D15-D8 */ TME_BUS_LANE_ABORT, 4265: /* D23-D16 */ TME_BUS_LANE_ABORT, 4266: /* D31-D24 */ TME_BUS_LANE_ABORT, 4267: 4268: /* initiator maximum cycle size: 32 bits 4269: initiator address offset: 24 bits 4270: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 4271: responder bus port size: 16 bits 4272: responder port least lane: D23-D16: */ 4273: /* D7-D0 */ TME_BUS_LANE_ABORT, 4274: /* D15-D8 */ TME_BUS_LANE_ABORT, 4275: /* D23-D16 */ TME_BUS_LANE_ABORT, 4276: /* D31-D24 */ TME_BUS_LANE_ABORT, 4277: 4278: /* initiator maximum cycle size: 32 bits 4279: initiator address offset: 24 bits 4280: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 4281: responder bus port size: 16 bits 4282: responder port least lane: D31-D24 4283: (responder port not correctly positioned for this initiator): */ 4284: /* D7-D0 */ TME_BUS_LANE_ABORT, 4285: /* D15-D8 */ TME_BUS_LANE_ABORT, 4286: /* D23-D16 */ TME_BUS_LANE_ABORT, 4287: /* D31-D24 */ TME_BUS_LANE_ABORT, 4288: 4289: /* initiator maximum cycle size: 32 bits 4290: initiator address offset: 24 bits 4291: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 4292: responder bus port size: 32 bits 4293: responder port least lane: D7-D0: */ 4294: /* D7-D0 */ TME_BUS_LANE_ABORT, 4295: /* D15-D8 */ TME_BUS_LANE_ABORT, 4296: /* D23-D16 */ TME_BUS_LANE_ABORT, 4297: /* D31-D24 */ TME_BUS_LANE_ABORT, 4298: 4299: /* initiator maximum cycle size: 32 bits 4300: initiator address offset: 24 bits 4301: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 4302: responder bus port size: 32 bits 4303: responder port least lane: D15-D8 4304: (responder port not correctly positioned for this initiator): */ 4305: /* D7-D0 */ TME_BUS_LANE_ABORT, 4306: /* D15-D8 */ TME_BUS_LANE_ABORT, 4307: /* D23-D16 */ TME_BUS_LANE_ABORT, 4308: /* D31-D24 */ TME_BUS_LANE_ABORT, 4309: 4310: /* initiator maximum cycle size: 32 bits 4311: initiator address offset: 24 bits 4312: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 4313: responder bus port size: 32 bits 4314: responder port least lane: D23-D16 4315: (responder port not correctly positioned for this initiator): */ 4316: /* D7-D0 */ TME_BUS_LANE_ABORT, 4317: /* D15-D8 */ TME_BUS_LANE_ABORT, 4318: /* D23-D16 */ TME_BUS_LANE_ABORT, 4319: /* D31-D24 */ TME_BUS_LANE_ABORT, 4320: 4321: /* initiator maximum cycle size: 32 bits 4322: initiator address offset: 24 bits 4323: (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder) 4324: responder bus port size: 32 bits 4325: responder port least lane: D31-D24 4326: (responder port not correctly positioned for this initiator): */ 4327: /* D7-D0 */ TME_BUS_LANE_ABORT, 4328: /* D15-D8 */ TME_BUS_LANE_ABORT, 4329: /* D23-D16 */ TME_BUS_LANE_ABORT, 4330: /* D31-D24 */ TME_BUS_LANE_ABORT, 4331: }; 4332: 4333: /* the 32-bit bus master DMA read function: */ 4334: int 4335: tme_bus_device_dma_read_32(struct tme_bus_device *bus_device, 4336: tme_bus_addr_t address_init, 4337: tme_bus_addr_t size, 4338: tme_uint8_t *buffer, 4339: unsigned int locks) 4340: { 4341: struct tme_bus_tlb *tlb, tlb_local; 4342: struct tme_bus_connection *conn_bus; 4343: tme_bus_addr_t count_minus_one, count; 4344: struct tme_bus_cycle cycle; 4345: tme_bus_addr_t address_resp; 4346: int shift; 4347: int err; 4348: 4349: /* assume no error: */ 4350: err = TME_OK; 4351: 4352: /* loop while we have more bytes to read: */ 4353: for (; err == TME_OK && size > 0; ) { 4354: 4355: /* hash this address into a TLB entry: */ 4356: tlb = (*bus_device->tme_bus_device_tlb_hash) 4357: (bus_device, 4358: address_init, 4359: TME_BUS_CYCLE_READ); 4360: 1.1.1.2 ! root 4361: /* busy this TLB entry: */ ! 4362: tme_bus_tlb_busy(tlb); ! 4363: ! 4364: /* if this TLB entry is invalid, doesn't cover this address, or if it doesn't 1.1 root 4365: allow reading, reload it: */ 1.1.1.2 ! root 4366: if (tme_bus_tlb_is_invalid(tlb) ! 4367: || address_init < tlb->tme_bus_tlb_addr_first ! 4368: || address_init > tlb->tme_bus_tlb_addr_last 1.1 root 4369: || (tlb->tme_bus_tlb_emulator_off_read == TME_EMULATOR_OFF_UNDEF 4370: && !(tlb->tme_bus_tlb_cycles_ok & TME_BUS_CYCLE_READ))) { 4371: 1.1.1.2 ! root 4372: /* unbusy this TLB entry for filling: */ ! 4373: tme_bus_tlb_unbusy_fill(tlb); ! 4374: 1.1 root 4375: /* reserve this TLB entry: */ 1.1.1.2 ! root 4376: tlb_local.tme_bus_tlb_global = tlb; 1.1 root 4377: tlb = &tlb_local; 4378: 4379: /* get our bus connection: */ 1.1.1.2 ! root 4380: conn_bus = tme_memory_atomic_pointer_read(struct tme_bus_connection *, ! 4381: bus_device->tme_bus_device_connection, ! 4382: &bus_device->tme_bus_device_connection_rwlock); 1.1 root 4383: 4384: /* unlock the device: */ 4385: (*bus_device->tme_bus_device_unlock)(bus_device, locks); 4386: 4387: /* reload the TLB entry: */ 4388: err = (*conn_bus->tme_bus_tlb_fill) 4389: (conn_bus, 4390: tlb, 4391: address_init, 4392: TME_BUS_CYCLE_READ); 4393: 4394: /* lock the device: */ 4395: (*bus_device->tme_bus_device_lock)(bus_device, locks); 4396: 4397: /* return if we couldn't fill the TLB entry: */ 4398: if (err != TME_OK) { 4399: return (err); 4400: } 4401: 4402: /* store the TLB entry: */ 4403: tme_bus_tlb_back(tlb); 1.1.1.2 ! root 4404: ! 4405: /* loop to check the newly filled TLB entry: */ ! 4406: continue; 1.1 root 4407: } 4408: 4409: /* if this TLB entry allows fast reading: */ 4410: if (tlb->tme_bus_tlb_emulator_off_read != TME_EMULATOR_OFF_UNDEF) { 4411: 4412: /* see how many bytes we can fast read from this TLB entry, 4413: starting at this address: */ 1.1.1.2 ! root 4414: count_minus_one = (tlb->tme_bus_tlb_addr_last - address_init); 1.1 root 4415: 4416: /* read that many bytes or size bytes, whichever is smaller: */ 4417: count_minus_one = TME_MIN(count_minus_one, 4418: (size - 1)); 4419: count = count_minus_one + 1; 4420: assert (count != 0); 4421: 1.1.1.2 ! root 4422: /* do the bus read: */ ! 4423: tme_memory_bus_read_buffer((tlb->tme_bus_tlb_emulator_off_read + address_init), buffer, count, tlb->tme_bus_tlb_rwlock, sizeof(tme_uint8_t), sizeof(tme_uint32_t)); ! 4424: ! 4425: /* unbusy this TLB entry: */ ! 4426: tme_bus_tlb_unbusy(tlb); 1.1 root 4427: } 4428: 4429: /* otherwise, we have to do a slow read: */ 4430: else { 4431: 4432: /* get the size of this bus cycle: */ 4433: count = (1 << TME_BUS32_LOG2); 4434: count -= (address_init & (count - 1)); 4435: count = TME_MIN(count, size); 4436: 4437: /* fill the cycle structure: */ 4438: cycle.tme_bus_cycle_type = TME_BUS_CYCLE_READ; 4439: cycle.tme_bus_cycle_size = count; 4440: cycle.tme_bus_cycle_buffer = (tme_uint8_t *) buffer; /* XXX this breaks const */ 4441: cycle.tme_bus_cycle_buffer_increment = 1; 4442: cycle.tme_bus_cycle_lane_routing 4443: = (bus_device->tme_bus_device_router 4444: + TME_BUS_ROUTER_INIT_INDEX(TME_BUS32_LOG2, count, address_init)); 4445: 4446: /* XXX this should come from a socket configuration: */ 4447: cycle.tme_bus_cycle_port = TME_BUS_CYCLE_PORT(0, TME_BUS32_LOG2); 4448: 4449: /* form the physical address for the bus cycle handler: */ 4450: address_resp = tlb->tme_bus_tlb_addr_offset + address_init; 4451: shift = tlb->tme_bus_tlb_addr_shift; 4452: if (shift < 0) { 4453: address_resp <<= (0 - shift); 4454: } 4455: else if (shift > 0) { 4456: address_resp >>= shift; 4457: } 4458: cycle.tme_bus_cycle_address = address_resp; 4459: 1.1.1.2 ! root 4460: /* unbusy this TLB entry: */ ! 4461: tme_bus_tlb_unbusy(tlb); ! 4462: 1.1 root 4463: /* unlock the device: */ 4464: (*bus_device->tme_bus_device_unlock)(bus_device, locks); 4465: 4466: /* run the bus cycle: */ 4467: err = (*tlb->tme_bus_tlb_cycle) 4468: (tlb->tme_bus_tlb_cycle_private, &cycle); 4469: 1.1.1.2 ! root 4470: /* if the TLB entry was invalidated before the read: */ ! 4471: if (err == EBADF ! 4472: && tme_bus_tlb_is_invalid(tlb)) { ! 4473: count = 0; 1.1 root 4474: } 4475: 4476: /* otherwise, any other error might be a bus error: */ 4477: else if (err != TME_OK) { 4478: err = tme_bus_tlb_fault(tlb, &cycle, err); 4479: assert (err != TME_OK); 4480: } 4481: 4482: /* lock the device: */ 4483: (*bus_device->tme_bus_device_lock)(bus_device, locks); 4484: } 4485: 4486: /* update the address, buffer, and size and continue: */ 4487: address_init += count; 4488: buffer += count; 4489: size -= count; 4490: } 4491: 4492: return (err); 4493: } 4494: 4495: /* the 32-bit bus master DMA write function: */ 4496: int 4497: tme_bus_device_dma_write_32(struct tme_bus_device *bus_device, 4498: tme_bus_addr_t address_init, 4499: tme_bus_addr_t size, 4500: const tme_uint8_t *buffer, 4501: unsigned int locks) 4502: { 4503: struct tme_bus_tlb *tlb, tlb_local; 4504: struct tme_bus_connection *conn_bus; 4505: tme_bus_addr_t count_minus_one, count; 4506: struct tme_bus_cycle cycle; 4507: tme_bus_addr_t address_resp; 4508: int shift; 4509: int err; 4510: 4511: /* assume no error: */ 4512: err = TME_OK; 4513: 4514: /* loop while we have more bytes to write: */ 4515: for (; err == TME_OK && size > 0; ) { 4516: 4517: /* hash this address into a TLB entry: */ 4518: tlb = (*bus_device->tme_bus_device_tlb_hash) 4519: (bus_device, 4520: address_init, 4521: TME_BUS_CYCLE_WRITE); 4522: 1.1.1.2 ! root 4523: /* busy this TLB entry: */ ! 4524: tme_bus_tlb_busy(tlb); ! 4525: ! 4526: /* if this TLB entry is invalid, doesn't cover this address, or if it doesn't 1.1 root 4527: allow writing, reload it: */ 1.1.1.2 ! root 4528: if (tme_bus_tlb_is_invalid(tlb) ! 4529: || address_init < tlb->tme_bus_tlb_addr_first ! 4530: || address_init > tlb->tme_bus_tlb_addr_last 1.1 root 4531: || (tlb->tme_bus_tlb_emulator_off_write == TME_EMULATOR_OFF_UNDEF 4532: && !(tlb->tme_bus_tlb_cycles_ok & TME_BUS_CYCLE_WRITE))) { 4533: 1.1.1.2 ! root 4534: /* unbusy this TLB entry for filling: */ ! 4535: tme_bus_tlb_unbusy_fill(tlb); ! 4536: 1.1 root 4537: /* reserve this TLB entry: */ 1.1.1.2 ! root 4538: tlb_local.tme_bus_tlb_global = tlb; 1.1 root 4539: tlb = &tlb_local; 4540: 4541: /* get our bus connection: */ 1.1.1.2 ! root 4542: conn_bus = tme_memory_atomic_pointer_read(struct tme_bus_connection *, ! 4543: bus_device->tme_bus_device_connection, ! 4544: &bus_device->tme_bus_device_connection_rwlock); 1.1 root 4545: 4546: /* unlock the device: */ 4547: (*bus_device->tme_bus_device_unlock)(bus_device, locks); 4548: 4549: /* reload the TLB entry: */ 4550: err = (*conn_bus->tme_bus_tlb_fill) 4551: (conn_bus, 4552: tlb, 4553: address_init, 4554: TME_BUS_CYCLE_WRITE); 4555: 4556: /* lock the device: */ 4557: (*bus_device->tme_bus_device_lock)(bus_device, locks); 4558: 4559: /* return if we couldn't fill the TLB entry: */ 4560: if (err != TME_OK) { 4561: return (err); 4562: } 4563: 4564: /* store the TLB entry: */ 4565: tme_bus_tlb_back(tlb); 1.1.1.2 ! root 4566: ! 4567: /* loop to check the newly filled TLB entry: */ ! 4568: continue; 1.1 root 4569: } 4570: 4571: /* if this TLB entry allows fast writing: */ 4572: if (tlb->tme_bus_tlb_emulator_off_write != TME_EMULATOR_OFF_UNDEF) { 4573: 4574: /* see how many bytes we can fast write to this TLB entry, 4575: starting at this address: */ 1.1.1.2 ! root 4576: count_minus_one = (tlb->tme_bus_tlb_addr_last - address_init); 1.1 root 4577: 4578: /* write that many bytes or size bytes, whichever is smaller: */ 4579: count_minus_one = TME_MIN(count_minus_one, 4580: (size - 1)); 4581: count = count_minus_one + 1; 4582: assert (count != 0); 4583: 1.1.1.2 ! root 4584: /* do the bus write: */ ! 4585: tme_memory_bus_write_buffer((tlb->tme_bus_tlb_emulator_off_write + address_init), buffer, count, tlb->tme_bus_tlb_rwlock, sizeof(tme_uint8_t), sizeof(tme_uint32_t)); ! 4586: ! 4587: /* unbusy this TLB entry: */ ! 4588: tme_bus_tlb_unbusy(tlb); 1.1 root 4589: } 4590: 4591: /* otherwise, we have to do a slow write: */ 4592: else { 4593: 4594: /* get the size of this bus cycle: */ 4595: count = (1 << TME_BUS32_LOG2); 4596: count -= (address_init & (count - 1)); 4597: count = TME_MIN(count, size); 4598: 4599: /* fill the cycle structure: */ 4600: cycle.tme_bus_cycle_type = TME_BUS_CYCLE_WRITE; 4601: cycle.tme_bus_cycle_size = count; 4602: cycle.tme_bus_cycle_buffer = (tme_uint8_t *) buffer; /* XXX this breaks const */ 4603: cycle.tme_bus_cycle_buffer_increment = 1; 4604: cycle.tme_bus_cycle_lane_routing 4605: = (bus_device->tme_bus_device_router 4606: + TME_BUS_ROUTER_INIT_INDEX(TME_BUS32_LOG2, count, address_init)); 4607: 4608: /* XXX this should come from a socket configuration: */ 4609: cycle.tme_bus_cycle_port = TME_BUS_CYCLE_PORT(0, TME_BUS32_LOG2); 4610: 4611: /* form the physical address for the bus cycle handler: */ 4612: address_resp = tlb->tme_bus_tlb_addr_offset + address_init; 4613: shift = tlb->tme_bus_tlb_addr_shift; 4614: if (shift < 0) { 4615: address_resp <<= (0 - shift); 4616: } 4617: else if (shift > 0) { 4618: address_resp >>= shift; 4619: } 4620: cycle.tme_bus_cycle_address = address_resp; 4621: 1.1.1.2 ! root 4622: /* unbusy this TLB entry: */ ! 4623: tme_bus_tlb_unbusy(tlb); ! 4624: 1.1 root 4625: /* unlock the device: */ 4626: (*bus_device->tme_bus_device_unlock)(bus_device, locks); 4627: 4628: /* run the bus cycle: */ 4629: err = (*tlb->tme_bus_tlb_cycle) 4630: (tlb->tme_bus_tlb_cycle_private, &cycle); 4631: 1.1.1.2 ! root 4632: /* if the TLB entry was invalidated before the write: */ ! 4633: if (err == EBADF ! 4634: && tme_bus_tlb_is_invalid(tlb)) { ! 4635: count = 0; 1.1 root 4636: } 4637: 4638: /* otherwise, any other error might be a bus error: */ 4639: else if (err != TME_OK) { 4640: err = tme_bus_tlb_fault(tlb, &cycle, err); 4641: assert (err != TME_OK); 4642: } 4643: 4644: /* lock the device: */ 4645: (*bus_device->tme_bus_device_lock)(bus_device, locks); 4646: } 4647: 4648: /* update the address, buffer, and size and continue: */ 4649: address_init += count; 4650: buffer += count; 4651: size -= count; 4652: } 4653: 4654: return (err); 4655: }
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