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Annotation of tme/ic/i825x6reg.h, revision 1.1.1.2

1.1.1.2 ! root        1: /* $Id: i825x6reg.h,v 1.2 2007/02/21 01:26:19 fredette Exp $ */
1.1       root        2: 
                      3: /* ic/i825x6reg.h - register definitions for Intel 82586/82596 emulation: */
                      4: 
                      5: /*
                      6:  * Copyright (c) 2004 Matt Fredette
                      7:  * All rights reserved.
                      8:  *
                      9:  * Redistribution and use in source and binary forms, with or without
                     10:  * modification, are permitted provided that the following conditions
                     11:  * are met:
                     12:  * 1. Redistributions of source code must retain the above copyright
                     13:  *    notice, this list of conditions and the following disclaimer.
                     14:  * 2. Redistributions in binary form must reproduce the above copyright
                     15:  *    notice, this list of conditions and the following disclaimer in the
                     16:  *    documentation and/or other materials provided with the distribution.
                     17:  * 3. All advertising materials mentioning features or use of this software
                     18:  *    must display the following acknowledgement:
                     19:  *      This product includes software developed by Matt Fredette.
                     20:  * 4. The name of the author may not be used to endorse or promote products
                     21:  *    derived from this software without specific prior written permission.
                     22:  *
                     23:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
                     24:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
                     25:  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
                     26:  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
                     27:  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
                     28:  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
                     29:  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
                     30:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
                     31:  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
                     32:  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
                     33:  * POSSIBILITY OF SUCH DAMAGE.
                     34:  */
                     35: 
                     36: #ifndef _TME_I825X6REG_H
                     37: #define _TME_I825X6REG_H
                     38: 
                     39: #include <tme/common.h>
1.1.1.2 ! root       40: _TME_RCSID("$Id: i825x6reg.h,v 1.2 2007/02/21 01:26:19 fredette Exp $");
1.1       root       41: 
                     42: /* macros: */
                     43: 
                     44: /* the SCP address: */
                     45: #define TME_I825X6_SCP_ADDRESS         (0x00fffff4)
                     46: 
                     47: /* the SCP: */
                     48: #define TME_I825X6_SCP_SYSBUS          (2)
                     49: #define  TME_I825X6_SCP_SYSBUS_MODE_MASK (0x06)
                     50: #define   TME_I825X6_SCP_SYSBUS_MODE_82586 (0x00)
                     51: #define   TME_I825X6_SCP_SYSBUS_MODE_32S   (0x02)
                     52: #define   TME_I825X6_SCP_SYSBUS_MODE_LINEAR (0x04)
                     53: #define  TME_I825X6_SCP_SYSBUS_BE       (0x80)
                     54: #define TME_I825X6_SCP_ISCP_ADDRESS    (8)
                     55: #define TME_I825X6_SCP_SIZE            (12)
                     56: 
                     57: /* the ISCP: */
                     58: #define TME_I825X6_ISCP_BUSY           (0)
                     59: #define TME_I82586_ISCP_SCB_OFFSET     (2)
                     60: #define TME_I82586_ISCP_SCB_BASE       (4)
                     61: #define TME_I825X6_ISCP_SIZE           (8)
                     62: 
                     63: /* the common SCB offsets: */
                     64: #define TME_I825X6_SCB_STAT_CUS_RUS_T  (0)
                     65: #define TME_I825X6_SCB_ACK_CUC_R_RUC   (2)
                     66: 
                     67: /* the i82586 and 32-bit segmented i82596 Command Block List and Receive Frame Area SCB offsets: */
                     68: #define TME_I82586_SCB_CBL_OFFSET      (4)
                     69: #define TME_I82586_SCB_RFA_OFFSET      (6)
                     70: 
                     71: /* the i82586 error counter SCB offsets: */
                     72: #define TME_I82586_SCB_ERRORS_CRC      (8)
                     73: #define TME_I82586_SCB_ERRORS_ALIGN    (10)
                     74: #define TME_I82586_SCB_ERRORS_RESOURCE (12)
                     75: #define TME_I82586_SCB_ERRORS_OVERRUN  (14)
                     76: 
                     77: /* the i82586 SCB size: */
                     78: #define TME_I82586_SCB_SIZE            (16)
                     79: 
                     80: /* the SCB Status bits: */
                     81: #define TME_I825X6_SCB_STAT_MASK       (0xf000)
                     82: #define  TME_I825X6_SCB_STAT_CX                 (0x8000)
                     83: #define  TME_I825X6_SCB_STAT_FR                 (0x4000)
                     84: #define  TME_I825X6_SCB_STAT_CNA        (0x2000)
                     85: #define  TME_I825X6_SCB_STAT_RNR        (0x1000)
                     86: 
                     87: /* the SCB Command Unit Status field: */
                     88: #define TME_I825X6_SCB_CUS_MASK                (0x0700)
                     89: #define  TME_I825X6_SCB_CUS_IDLE        (0x0000)
                     90: #define  TME_I825X6_SCB_CUS_SUSPENDED   (0x0100)
                     91: #define  TME_I825X6_SCB_CUS_ACTIVE      (0x0200)
                     92: 
                     93: /* the SCB Receive Unit Status: */
                     94: #define TME_I82586_SCB_RUS_MASK                (0x0070)
                     95: #define  TME_I825X6_SCB_RUS_READY       (0x0040)
                     96: #define  TME_I825X6_SCB_RUS_ERESOURCE   (0x0020)
                     97: #define  TME_I825X6_SCB_RUS_SUSPENDED   (0x0010)
                     98: #define  TME_I825X6_SCB_RUS_IDLE        (0x0000)
                     99: 
                    100: /* the SCB Command Unit Command field: */
                    101: #define TME_I825X6_SCB_CUC_MASK                (0x0700)
                    102: #define  TME_I825X6_SCB_CUC_NOP                 (0x0000)
                    103: #define  TME_I825X6_SCB_CUC_START       (0x0100)
                    104: #define  TME_I825X6_SCB_CUC_RESUME      (0x0200)
                    105: #define  TME_I825X6_SCB_CUC_SUSPEND     (0x0300)
                    106: #define  TME_I825X6_SCB_CUC_ABORT       (0x0400)
                    107: 
                    108: /* the SCB Reset bit: */
                    109: #define TME_I825X6_SCB_RESET           (0x0080)
                    110: 
                    111: /* the SCB Receive Unit Command field: */
                    112: #define TME_I825X6_SCB_RUC_MASK                (0x0070)
                    113: #define  TME_I825X6_SCB_RUC_NOP                 (0x0000)
                    114: #define  TME_I825X6_SCB_RUC_START       (0x0010)
                    115: #define  TME_I825X6_SCB_RUC_RESUME      (0x0020)
                    116: #define  TME_I825X6_SCB_RUC_SUSPEND     (0x0030)
                    117: #define  TME_I825X6_SCB_RUC_ABORT       (0x0040)
                    118: 
                    119: /* the i825x6 Command Block, Receive Frame Descriptor, and Receive
                    120:    Buffer Descriptor flags: */
                    121: #define  TME_I825X6_FLAG_EL             (0x8000)
                    122: #define  TME_I825X6_FLAG_S              (0x4000)
                    123: #define  TME_I825X6_FLAG_C              (0x8000)
                    124: #define  TME_I825X6_FLAG_B              (0x4000)
                    125: #define  TME_I825X6_FLAG_OK             (0x2000)
                    126: 
                    127: /* the i825x6 Command Block: */
                    128: #define TME_I825X6_CB_C_B_OK_A         (0)
                    129: #define  TME_I825X6_CB_A                (0x1000)
                    130: #define TME_I825X6_CB_EL_S_I_CMD       (2)
                    131: #define  TME_I825X6_CB_I                (0x2000)
                    132: #define  TME_I825X6_CB_CMD_MASK                 (0x0007)
                    133: #define   TME_I825X6_CB_CMD_NOP                  (0x0000)
                    134: #define   TME_I825X6_CB_CMD_SETUP_IA     (0x0001)
                    135: #define   TME_I825X6_CB_CMD_CONFIGURE    (0x0002)
                    136: #define   TME_I825X6_CB_CMD_SETUP_MC     (0x0003)
                    137: #define   TME_I825X6_CB_CMD_TRANSMIT     (0x0004)
                    138: #define   TME_I825X6_CB_CMD_TDR                  (0x0005)
                    139: #define   TME_I825X6_CB_CMD_DUMP         (0x0006)
                    140: #define   TME_I825X6_CB_CMD_DIAGNOSE     (0x0007)
                    141: 
                    142: /* the i82586 and 32-bit segmented i82596 Command Block: */
                    143: #define TME_I82586_CB_LINK_OFFSET      (4)
                    144: #define TME_I82586_CB_X                        (6)
                    145: 
                    146: /* the i82586 and 32-bit segmented i82596 Transmit Command Block Transmit Buffer field: */
                    147: #define TME_I82586_TCB_TBD_OFFSET      (6)
                    148: 
                    149: /* the i82586 Transmit Command Block: */
                    150: #define  TME_I825X6_TCB_STATUS_MASK     (0x0ff0)
                    151: #define   TME_I825X6_TCB_STATUS_UNDERRUN  (0x0100)
                    152: #define TME_I82586_TCB_ADDR_DEST       (8)
                    153: #define TME_I82586_TCB_LENGTH          (14)
                    154: #define TME_I82585_TCB_SIZE            (16)
                    155: 
                    156: /* the i82586 and 32-bit segmented i82586 Transmit Buffer: */
                    157: #define TME_I82586_TBD_EOF_SIZE                (0)
                    158: #define  TME_I82586_TBD_EOF             (0x8000)
1.1.1.2 ! root      159: #define  TME_I82586_TBD_SIZE_MASK       (0x3fff)
1.1       root      160: #define TME_I82586_TBD_TBD_OFFSET      (2)
                    161: #define TME_I82586_TBD_TB_ADDRESS      (4)
                    162: 
                    163: /* the i82586 and 32-bit segmented i82596 TDR result field: */
                    164: #define TME_I82586_TDR_STATUS_OK       (0x8000)
                    165: 
                    166: /* the i825x6 Receive Frame Descriptor: */
                    167: #define TME_I825X6_RFD_C_B_OK_STATUS   (0)
                    168: #define  TME_I825X6_RFD_STATUS_RNR      (0x0200)
                    169: #define TME_I825X6_RFD_EL_S_SF         (2)
                    170: #define  TME_I82596_RFD_SF              (0x0008)
                    171: 
                    172: /* the i82586 and 32-bit segmented i82596 Receive Frame Descriptor: */
                    173: #define TME_I82586_RFD_LINK_OFFSET     (4)
                    174: #define TME_I82586_RFD_RBD_OFFSET      (6)
                    175: 
                    176: /* the i82586 Receive Frame Descriptor: */
                    177: #define TME_I82586_RFD_RBD_ETH_HEADER  (6)
                    178: 
                    179: /* the i825x6 Receive Buffer Descriptor: */
                    180: #define TME_I825X6_RBD_EOF_F_ACT_COUNT (0)
                    181: #define  TME_I825X6_RBD_EOF             (0x8000)
                    182: #define  TME_I825X6_RBD_F               (0x4000)
                    183: #define  TME_I825X6_RBD_ACT_COUNT_MASK  (0x3fff)
                    184: 
                    185: /* the i82586 and 32-bit segmented i82596 Receive Buffer Descriptor: */
                    186: #define TME_I82586_RBD_RBD_OFFSET      (2)
                    187: #define TME_I82586_RBD_RB_ADDRESS      (4)
                    188: #define TME_I82586_RBD_EL_P_SIZE       (8)
                    189: #define  TME_I825X6_RBD_EL              (0x8000)
                    190: #define  TME_I82596_RBD_P               (0x4000)
                    191: #define  TME_I825X6_RBD_SIZE_MASK       (0x3fff)
                    192: 
                    193: #endif /* !_TME_I825X6REG_H */

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