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1.1 root 1: /* automatically generated by sparc-bus-auto.sh, do not edit! */
2: _TME_RCSID("$Id: sparc-bus-auto.sh,v 1.1 2006/09/30 12:55:59 fredette Exp $");
3:
4: /* it was easiest, but probably not the most correct, to reuse the
5: m68020 bus router, at least for the early SPARCs. there are
6: probably real differences between the m68020 bus router and the bus
7: router used by the MB89600, for example, but I don't have a
8: datasheet for the latter. the placement of devices in the Sun
9: 4/2x0 address space, however, hints that the two probably are very
10: similar. */
11:
12: /* we use OP3, OP2, OP1, and OP0 to represent bytes of lesser
13: significance to more significance, respectively, matching Table 5-5
14: in the MC68020 User's Manual (linear page 56 in my .ps copy).
15:
16: the Motorola OPn convention numbers bytes by decreasing
17: significance (OP2 is less significant than OP1), and since Motorola
18: CPUs are big-endian, this means that a higher numbered byte is
19: meant to go to a higher address, which is good, because we can then
20: use this to easily form indexes for TME_BUS_LANE_ROUTE, which
21: expects a higher numbered index to correspond to a higher address
22: in memory.
23:
24: however, since the same Motorola OPn convention always calls the
25: least significant byte of any value OP3, regardless of the total
26: size of the value, we need to adjust each OPn given the total
27: size of the value, so that OP3 in a 24-bit value means address + 2,
28: but OP3 in a 32-bit value means address + 3: */
29: #define SIZ8_OP(n) ((n) - 3)
30: #define SIZ16_OP(n) ((n) - 2)
31: #define SIZ24_OP(n) ((n) - 1)
32: #define SIZ32_OP(n) ((n) - 0)
33:
34: /* the 32-bit bus router used on the early SPARCs: */
35: static const tme_bus_lane_t tme_sparc32_router[TME_SPARC_BUS_ROUTER_SIZE(TME_BUS32_LOG2)] = {
36:
37: /* [sparc] initiator maximum cycle size: 8 bits
38: [sparc] initiator A1,A0: 00
39: [gen] responder port size: 8 bits
40: [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit sparc)
41: (code 1.0.1.0, OP3 lane 3): */
42: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
43: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
44: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
45: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
46:
47: /* [sparc] initiator maximum cycle size: 8 bits
48: [sparc] initiator A1,A0: 00
49: [gen] responder port size: 8 bits
50: [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit sparc)
51: (code 1.0.1.1, OP3 lane 3): */
52: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
53: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
54: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
55: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
56:
57: /* [sparc] initiator maximum cycle size: 8 bits
58: [sparc] initiator A1,A0: 00
59: [gen] responder port size: 8 bits
60: [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit sparc)
61: (code 1.0.1.2, OP3 lane 3): */
62: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
63: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
64: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
65: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
66:
67: /* [sparc] initiator maximum cycle size: 8 bits
68: [sparc] initiator A1,A0: 00
69: [gen] responder port size: 8 bits
70: [gen] responder port least lane: 3 (lanes D31-D24)
71: (code 1.0.1.3, OP3 lane 3): */
72: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
73: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
74: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
75: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
76:
77: /* [sparc] initiator maximum cycle size: 8 bits
78: [sparc] initiator A1,A0: 00
79: [gen] responder port size: 16 bits
80: [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit sparc)
81: (code 1.0.2.0, OP3 lane 3): */
82: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
83: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
84: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
85: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
86:
87: /* [sparc] initiator maximum cycle size: 8 bits
88: [sparc] initiator A1,A0: 00
89: [gen] responder port size: 16 bits
90: [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit sparc)
91: (code 1.0.2.1, OP3 lane 3): */
92: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
93: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
94: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
95: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
96:
97: /* [sparc] initiator maximum cycle size: 8 bits
98: [sparc] initiator A1,A0: 00
99: [gen] responder port size: 16 bits
100: [gen] responder port least lane: 2 (lanes D31-D24 D23-D16)
101: (code 1.0.2.2, OP3 lane 3): */
102: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
103: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
104: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
105: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
106:
107: /* [sparc] initiator maximum cycle size: 8 bits
108: [sparc] initiator A1,A0: 00
109: [gen] responder port size: 16 bits
110: [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder)
111: (code 1.0.2.3, OP3 lane 3): */
112: /* D7-D0 */ TME_BUS_LANE_ABORT,
113: /* D15-D8 */ TME_BUS_LANE_ABORT,
114: /* D23-D16 */ TME_BUS_LANE_ABORT,
115: /* D31-D24 */ TME_BUS_LANE_ABORT,
116:
117: /* [sparc] initiator maximum cycle size: 8 bits
118: [sparc] initiator A1,A0: 00
119: [gen] responder port size: 32 bits
120: [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0)
121: (code 1.0.4.0, OP3 lane 3): */
122: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
123: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
124: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
125: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
126:
127: /* [sparc] initiator maximum cycle size: 8 bits
128: [sparc] initiator A1,A0: 00
129: [gen] responder port size: 32 bits
130: [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder)
131: (code 1.0.4.1, OP3 lane 3): */
132: /* D7-D0 */ TME_BUS_LANE_ABORT,
133: /* D15-D8 */ TME_BUS_LANE_ABORT,
134: /* D23-D16 */ TME_BUS_LANE_ABORT,
135: /* D31-D24 */ TME_BUS_LANE_ABORT,
136:
137: /* [sparc] initiator maximum cycle size: 8 bits
138: [sparc] initiator A1,A0: 00
139: [gen] responder port size: 32 bits
140: [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder)
141: (code 1.0.4.2, OP3 lane 3): */
142: /* D7-D0 */ TME_BUS_LANE_ABORT,
143: /* D15-D8 */ TME_BUS_LANE_ABORT,
144: /* D23-D16 */ TME_BUS_LANE_ABORT,
145: /* D31-D24 */ TME_BUS_LANE_ABORT,
146:
147: /* [sparc] initiator maximum cycle size: 8 bits
148: [sparc] initiator A1,A0: 00
149: [gen] responder port size: 32 bits
150: [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder)
151: (code 1.0.4.3, OP3 lane 3): */
152: /* D7-D0 */ TME_BUS_LANE_ABORT,
153: /* D15-D8 */ TME_BUS_LANE_ABORT,
154: /* D23-D16 */ TME_BUS_LANE_ABORT,
155: /* D31-D24 */ TME_BUS_LANE_ABORT,
156:
157: /* [sparc] initiator maximum cycle size: 8 bits
158: [sparc] initiator A1,A0: 01
159: [gen] responder port size: 8 bits
160: [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit sparc)
161: (code 1.1.1.0, OP3 lane 3): */
162: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
163: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
164: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
165: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
166:
167: /* [sparc] initiator maximum cycle size: 8 bits
168: [sparc] initiator A1,A0: 01
169: [gen] responder port size: 8 bits
170: [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit sparc)
171: (code 1.1.1.1, OP3 lane 3): */
172: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
173: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
174: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
175: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
176:
177: /* [sparc] initiator maximum cycle size: 8 bits
178: [sparc] initiator A1,A0: 01
179: [gen] responder port size: 8 bits
180: [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit sparc)
181: (code 1.1.1.2, OP3 lane 3): */
182: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
183: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
184: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
185: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
186:
187: /* [sparc] initiator maximum cycle size: 8 bits
188: [sparc] initiator A1,A0: 01
189: [gen] responder port size: 8 bits
190: [gen] responder port least lane: 3 (lanes D31-D24)
191: (code 1.1.1.3, OP3 lane 3): */
192: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
193: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
194: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
195: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
196:
197: /* [sparc] initiator maximum cycle size: 8 bits
198: [sparc] initiator A1,A0: 01
199: [gen] responder port size: 16 bits
200: [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit sparc)
201: (code 1.1.2.0, OP3 lane 2): */
202: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
203: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
204: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
205: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
206:
207: /* [sparc] initiator maximum cycle size: 8 bits
208: [sparc] initiator A1,A0: 01
209: [gen] responder port size: 16 bits
210: [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit sparc)
211: (code 1.1.2.1, OP3 lane 2): */
212: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
213: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
214: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
215: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
216:
217: /* [sparc] initiator maximum cycle size: 8 bits
218: [sparc] initiator A1,A0: 01
219: [gen] responder port size: 16 bits
220: [gen] responder port least lane: 2 (lanes D31-D24 D23-D16)
221: (code 1.1.2.2, OP3 lane 2): */
222: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
223: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
224: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
225: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
226:
227: /* [sparc] initiator maximum cycle size: 8 bits
228: [sparc] initiator A1,A0: 01
229: [gen] responder port size: 16 bits
230: [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder)
231: (code 1.1.2.3, OP3 lane 2): */
232: /* D7-D0 */ TME_BUS_LANE_ABORT,
233: /* D15-D8 */ TME_BUS_LANE_ABORT,
234: /* D23-D16 */ TME_BUS_LANE_ABORT,
235: /* D31-D24 */ TME_BUS_LANE_ABORT,
236:
237: /* [sparc] initiator maximum cycle size: 8 bits
238: [sparc] initiator A1,A0: 01
239: [gen] responder port size: 32 bits
240: [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0)
241: (code 1.1.4.0, OP3 lane 2): */
242: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
243: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
244: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
245: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
246:
247: /* [sparc] initiator maximum cycle size: 8 bits
248: [sparc] initiator A1,A0: 01
249: [gen] responder port size: 32 bits
250: [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder)
251: (code 1.1.4.1, OP3 lane 2): */
252: /* D7-D0 */ TME_BUS_LANE_ABORT,
253: /* D15-D8 */ TME_BUS_LANE_ABORT,
254: /* D23-D16 */ TME_BUS_LANE_ABORT,
255: /* D31-D24 */ TME_BUS_LANE_ABORT,
256:
257: /* [sparc] initiator maximum cycle size: 8 bits
258: [sparc] initiator A1,A0: 01
259: [gen] responder port size: 32 bits
260: [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder)
261: (code 1.1.4.2, OP3 lane 2): */
262: /* D7-D0 */ TME_BUS_LANE_ABORT,
263: /* D15-D8 */ TME_BUS_LANE_ABORT,
264: /* D23-D16 */ TME_BUS_LANE_ABORT,
265: /* D31-D24 */ TME_BUS_LANE_ABORT,
266:
267: /* [sparc] initiator maximum cycle size: 8 bits
268: [sparc] initiator A1,A0: 01
269: [gen] responder port size: 32 bits
270: [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder)
271: (code 1.1.4.3, OP3 lane 2): */
272: /* D7-D0 */ TME_BUS_LANE_ABORT,
273: /* D15-D8 */ TME_BUS_LANE_ABORT,
274: /* D23-D16 */ TME_BUS_LANE_ABORT,
275: /* D31-D24 */ TME_BUS_LANE_ABORT,
276:
277: /* [sparc] initiator maximum cycle size: 8 bits
278: [sparc] initiator A1,A0: 10
279: [gen] responder port size: 8 bits
280: [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit sparc)
281: (code 1.2.1.0, OP3 lane 3): */
282: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
283: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
284: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
285: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
286:
287: /* [sparc] initiator maximum cycle size: 8 bits
288: [sparc] initiator A1,A0: 10
289: [gen] responder port size: 8 bits
290: [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit sparc)
291: (code 1.2.1.1, OP3 lane 3): */
292: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
293: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
294: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
295: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
296:
297: /* [sparc] initiator maximum cycle size: 8 bits
298: [sparc] initiator A1,A0: 10
299: [gen] responder port size: 8 bits
300: [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit sparc)
301: (code 1.2.1.2, OP3 lane 3): */
302: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
303: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
304: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
305: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
306:
307: /* [sparc] initiator maximum cycle size: 8 bits
308: [sparc] initiator A1,A0: 10
309: [gen] responder port size: 8 bits
310: [gen] responder port least lane: 3 (lanes D31-D24)
311: (code 1.2.1.3, OP3 lane 3): */
312: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
313: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
314: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
315: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
316:
317: /* [sparc] initiator maximum cycle size: 8 bits
318: [sparc] initiator A1,A0: 10
319: [gen] responder port size: 16 bits
320: [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit sparc)
321: (code 1.2.2.0, OP3 lane 3): */
322: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
323: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
324: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
325: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
326:
327: /* [sparc] initiator maximum cycle size: 8 bits
328: [sparc] initiator A1,A0: 10
329: [gen] responder port size: 16 bits
330: [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit sparc)
331: (code 1.2.2.1, OP3 lane 3): */
332: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
333: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
334: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
335: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
336:
337: /* [sparc] initiator maximum cycle size: 8 bits
338: [sparc] initiator A1,A0: 10
339: [gen] responder port size: 16 bits
340: [gen] responder port least lane: 2 (lanes D31-D24 D23-D16)
341: (code 1.2.2.2, OP3 lane 3): */
342: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
343: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
344: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
345: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
346:
347: /* [sparc] initiator maximum cycle size: 8 bits
348: [sparc] initiator A1,A0: 10
349: [gen] responder port size: 16 bits
350: [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder)
351: (code 1.2.2.3, OP3 lane 3): */
352: /* D7-D0 */ TME_BUS_LANE_ABORT,
353: /* D15-D8 */ TME_BUS_LANE_ABORT,
354: /* D23-D16 */ TME_BUS_LANE_ABORT,
355: /* D31-D24 */ TME_BUS_LANE_ABORT,
356:
357: /* [sparc] initiator maximum cycle size: 8 bits
358: [sparc] initiator A1,A0: 10
359: [gen] responder port size: 32 bits
360: [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0)
361: (code 1.2.4.0, OP3 lane 1): */
362: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
363: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
364: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
365: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
366:
367: /* [sparc] initiator maximum cycle size: 8 bits
368: [sparc] initiator A1,A0: 10
369: [gen] responder port size: 32 bits
370: [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder)
371: (code 1.2.4.1, OP3 lane 1): */
372: /* D7-D0 */ TME_BUS_LANE_ABORT,
373: /* D15-D8 */ TME_BUS_LANE_ABORT,
374: /* D23-D16 */ TME_BUS_LANE_ABORT,
375: /* D31-D24 */ TME_BUS_LANE_ABORT,
376:
377: /* [sparc] initiator maximum cycle size: 8 bits
378: [sparc] initiator A1,A0: 10
379: [gen] responder port size: 32 bits
380: [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder)
381: (code 1.2.4.2, OP3 lane 1): */
382: /* D7-D0 */ TME_BUS_LANE_ABORT,
383: /* D15-D8 */ TME_BUS_LANE_ABORT,
384: /* D23-D16 */ TME_BUS_LANE_ABORT,
385: /* D31-D24 */ TME_BUS_LANE_ABORT,
386:
387: /* [sparc] initiator maximum cycle size: 8 bits
388: [sparc] initiator A1,A0: 10
389: [gen] responder port size: 32 bits
390: [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder)
391: (code 1.2.4.3, OP3 lane 1): */
392: /* D7-D0 */ TME_BUS_LANE_ABORT,
393: /* D15-D8 */ TME_BUS_LANE_ABORT,
394: /* D23-D16 */ TME_BUS_LANE_ABORT,
395: /* D31-D24 */ TME_BUS_LANE_ABORT,
396:
397: /* [sparc] initiator maximum cycle size: 8 bits
398: [sparc] initiator A1,A0: 11
399: [gen] responder port size: 8 bits
400: [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit sparc)
401: (code 1.3.1.0, OP3 lane 3): */
402: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
403: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
404: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
405: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
406:
407: /* [sparc] initiator maximum cycle size: 8 bits
408: [sparc] initiator A1,A0: 11
409: [gen] responder port size: 8 bits
410: [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit sparc)
411: (code 1.3.1.1, OP3 lane 3): */
412: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
413: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
414: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
415: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
416:
417: /* [sparc] initiator maximum cycle size: 8 bits
418: [sparc] initiator A1,A0: 11
419: [gen] responder port size: 8 bits
420: [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit sparc)
421: (code 1.3.1.2, OP3 lane 3): */
422: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
423: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
424: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
425: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
426:
427: /* [sparc] initiator maximum cycle size: 8 bits
428: [sparc] initiator A1,A0: 11
429: [gen] responder port size: 8 bits
430: [gen] responder port least lane: 3 (lanes D31-D24)
431: (code 1.3.1.3, OP3 lane 3): */
432: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
433: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
434: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
435: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
436:
437: /* [sparc] initiator maximum cycle size: 8 bits
438: [sparc] initiator A1,A0: 11
439: [gen] responder port size: 16 bits
440: [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit sparc)
441: (code 1.3.2.0, OP3 lane 2): */
442: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
443: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
444: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
445: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
446:
447: /* [sparc] initiator maximum cycle size: 8 bits
448: [sparc] initiator A1,A0: 11
449: [gen] responder port size: 16 bits
450: [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit sparc)
451: (code 1.3.2.1, OP3 lane 2): */
452: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
453: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
454: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
455: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
456:
457: /* [sparc] initiator maximum cycle size: 8 bits
458: [sparc] initiator A1,A0: 11
459: [gen] responder port size: 16 bits
460: [gen] responder port least lane: 2 (lanes D31-D24 D23-D16)
461: (code 1.3.2.2, OP3 lane 2): */
462: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
463: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
464: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
465: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
466:
467: /* [sparc] initiator maximum cycle size: 8 bits
468: [sparc] initiator A1,A0: 11
469: [gen] responder port size: 16 bits
470: [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder)
471: (code 1.3.2.3, OP3 lane 2): */
472: /* D7-D0 */ TME_BUS_LANE_ABORT,
473: /* D15-D8 */ TME_BUS_LANE_ABORT,
474: /* D23-D16 */ TME_BUS_LANE_ABORT,
475: /* D31-D24 */ TME_BUS_LANE_ABORT,
476:
477: /* [sparc] initiator maximum cycle size: 8 bits
478: [sparc] initiator A1,A0: 11
479: [gen] responder port size: 32 bits
480: [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0)
481: (code 1.3.4.0, OP3 lane 0): */
482: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)),
483: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
484: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
485: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
486:
487: /* [sparc] initiator maximum cycle size: 8 bits
488: [sparc] initiator A1,A0: 11
489: [gen] responder port size: 32 bits
490: [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder)
491: (code 1.3.4.1, OP3 lane 0): */
492: /* D7-D0 */ TME_BUS_LANE_ABORT,
493: /* D15-D8 */ TME_BUS_LANE_ABORT,
494: /* D23-D16 */ TME_BUS_LANE_ABORT,
495: /* D31-D24 */ TME_BUS_LANE_ABORT,
496:
497: /* [sparc] initiator maximum cycle size: 8 bits
498: [sparc] initiator A1,A0: 11
499: [gen] responder port size: 32 bits
500: [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder)
501: (code 1.3.4.2, OP3 lane 0): */
502: /* D7-D0 */ TME_BUS_LANE_ABORT,
503: /* D15-D8 */ TME_BUS_LANE_ABORT,
504: /* D23-D16 */ TME_BUS_LANE_ABORT,
505: /* D31-D24 */ TME_BUS_LANE_ABORT,
506:
507: /* [sparc] initiator maximum cycle size: 8 bits
508: [sparc] initiator A1,A0: 11
509: [gen] responder port size: 32 bits
510: [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder)
511: (code 1.3.4.3, OP3 lane 0): */
512: /* D7-D0 */ TME_BUS_LANE_ABORT,
513: /* D15-D8 */ TME_BUS_LANE_ABORT,
514: /* D23-D16 */ TME_BUS_LANE_ABORT,
515: /* D31-D24 */ TME_BUS_LANE_ABORT,
516:
517: /* [sparc] initiator maximum cycle size: 16 bits
518: [sparc] initiator A1,A0: 00
519: [gen] responder port size: 8 bits
520: [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit sparc)
521: (code 2.0.1.0, OP3 lane 2): */
522: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
523: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
524: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
525: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
526:
527: /* [sparc] initiator maximum cycle size: 16 bits
528: [sparc] initiator A1,A0: 00
529: [gen] responder port size: 8 bits
530: [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit sparc)
531: (code 2.0.1.1, OP3 lane 2): */
532: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
533: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
534: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
535: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
536:
537: /* [sparc] initiator maximum cycle size: 16 bits
538: [sparc] initiator A1,A0: 00
539: [gen] responder port size: 8 bits
540: [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit sparc)
541: (code 2.0.1.2, OP3 lane 2): */
542: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
543: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
544: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
545: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
546:
547: /* [sparc] initiator maximum cycle size: 16 bits
548: [sparc] initiator A1,A0: 00
549: [gen] responder port size: 8 bits
550: [gen] responder port least lane: 3 (lanes D31-D24)
551: (code 2.0.1.3, OP3 lane 2): */
552: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
553: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
554: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
555: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
556:
557: /* [sparc] initiator maximum cycle size: 16 bits
558: [sparc] initiator A1,A0: 00
559: [gen] responder port size: 16 bits
560: [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit sparc)
561: (code 2.0.2.0, OP3 lane 2): */
562: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
563: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
564: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)),
565: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
566:
567: /* [sparc] initiator maximum cycle size: 16 bits
568: [sparc] initiator A1,A0: 00
569: [gen] responder port size: 16 bits
570: [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit sparc)
571: (code 2.0.2.1, OP3 lane 2): */
572: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
573: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
574: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)),
575: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
576:
577: /* [sparc] initiator maximum cycle size: 16 bits
578: [sparc] initiator A1,A0: 00
579: [gen] responder port size: 16 bits
580: [gen] responder port least lane: 2 (lanes D31-D24 D23-D16)
581: (code 2.0.2.2, OP3 lane 2): */
582: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
583: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
584: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)),
585: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
586:
587: /* [sparc] initiator maximum cycle size: 16 bits
588: [sparc] initiator A1,A0: 00
589: [gen] responder port size: 16 bits
590: [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder)
591: (code 2.0.2.3, OP3 lane 2): */
592: /* D7-D0 */ TME_BUS_LANE_ABORT,
593: /* D15-D8 */ TME_BUS_LANE_ABORT,
594: /* D23-D16 */ TME_BUS_LANE_ABORT,
595: /* D31-D24 */ TME_BUS_LANE_ABORT,
596:
597: /* [sparc] initiator maximum cycle size: 16 bits
598: [sparc] initiator A1,A0: 00
599: [gen] responder port size: 32 bits
600: [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0)
601: (code 2.0.4.0, OP3 lane 2): */
602: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
603: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
604: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)),
605: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
606:
607: /* [sparc] initiator maximum cycle size: 16 bits
608: [sparc] initiator A1,A0: 00
609: [gen] responder port size: 32 bits
610: [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder)
611: (code 2.0.4.1, OP3 lane 2): */
612: /* D7-D0 */ TME_BUS_LANE_ABORT,
613: /* D15-D8 */ TME_BUS_LANE_ABORT,
614: /* D23-D16 */ TME_BUS_LANE_ABORT,
615: /* D31-D24 */ TME_BUS_LANE_ABORT,
616:
617: /* [sparc] initiator maximum cycle size: 16 bits
618: [sparc] initiator A1,A0: 00
619: [gen] responder port size: 32 bits
620: [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder)
621: (code 2.0.4.2, OP3 lane 2): */
622: /* D7-D0 */ TME_BUS_LANE_ABORT,
623: /* D15-D8 */ TME_BUS_LANE_ABORT,
624: /* D23-D16 */ TME_BUS_LANE_ABORT,
625: /* D31-D24 */ TME_BUS_LANE_ABORT,
626:
627: /* [sparc] initiator maximum cycle size: 16 bits
628: [sparc] initiator A1,A0: 00
629: [gen] responder port size: 32 bits
630: [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder)
631: (code 2.0.4.3, OP3 lane 2): */
632: /* D7-D0 */ TME_BUS_LANE_ABORT,
633: /* D15-D8 */ TME_BUS_LANE_ABORT,
634: /* D23-D16 */ TME_BUS_LANE_ABORT,
635: /* D31-D24 */ TME_BUS_LANE_ABORT,
636:
637: /* [sparc] initiator maximum cycle size: 16 bits
638: [sparc] initiator A1,A0: 01
639: [gen] responder port size: 8 bits
640: [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit sparc)
641: (code 2.1.1.0, OP3 lane 2): */
642: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
643: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
644: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
645: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
646:
647: /* [sparc] initiator maximum cycle size: 16 bits
648: [sparc] initiator A1,A0: 01
649: [gen] responder port size: 8 bits
650: [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit sparc)
651: (code 2.1.1.1, OP3 lane 2): */
652: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
653: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
654: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
655: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
656:
657: /* [sparc] initiator maximum cycle size: 16 bits
658: [sparc] initiator A1,A0: 01
659: [gen] responder port size: 8 bits
660: [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit sparc)
661: (code 2.1.1.2, OP3 lane 2): */
662: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
663: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
664: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
665: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
666:
667: /* [sparc] initiator maximum cycle size: 16 bits
668: [sparc] initiator A1,A0: 01
669: [gen] responder port size: 8 bits
670: [gen] responder port least lane: 3 (lanes D31-D24)
671: (code 2.1.1.3, OP3 lane 2): */
672: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
673: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
674: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
675: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
676:
677: /* [sparc] initiator maximum cycle size: 16 bits
678: [sparc] initiator A1,A0: 01
679: [gen] responder port size: 16 bits
680: [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit sparc)
681: (code 2.1.2.0, OP3 lane 1): */
682: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
683: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
684: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
685: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
686:
687: /* [sparc] initiator maximum cycle size: 16 bits
688: [sparc] initiator A1,A0: 01
689: [gen] responder port size: 16 bits
690: [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit sparc)
691: (code 2.1.2.1, OP3 lane 1): */
692: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
693: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
694: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
695: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
696:
697: /* [sparc] initiator maximum cycle size: 16 bits
698: [sparc] initiator A1,A0: 01
699: [gen] responder port size: 16 bits
700: [gen] responder port least lane: 2 (lanes D31-D24 D23-D16)
701: (code 2.1.2.2, OP3 lane 1): */
702: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
703: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
704: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
705: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
706:
707: /* [sparc] initiator maximum cycle size: 16 bits
708: [sparc] initiator A1,A0: 01
709: [gen] responder port size: 16 bits
710: [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder)
711: (code 2.1.2.3, OP3 lane 1): */
712: /* D7-D0 */ TME_BUS_LANE_ABORT,
713: /* D15-D8 */ TME_BUS_LANE_ABORT,
714: /* D23-D16 */ TME_BUS_LANE_ABORT,
715: /* D31-D24 */ TME_BUS_LANE_ABORT,
716:
717: /* [sparc] initiator maximum cycle size: 16 bits
718: [sparc] initiator A1,A0: 01
719: [gen] responder port size: 32 bits
720: [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0)
721: (code 2.1.4.0, OP3 lane 1): */
722: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
723: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)),
724: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
725: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
726:
727: /* [sparc] initiator maximum cycle size: 16 bits
728: [sparc] initiator A1,A0: 01
729: [gen] responder port size: 32 bits
730: [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder)
731: (code 2.1.4.1, OP3 lane 1): */
732: /* D7-D0 */ TME_BUS_LANE_ABORT,
733: /* D15-D8 */ TME_BUS_LANE_ABORT,
734: /* D23-D16 */ TME_BUS_LANE_ABORT,
735: /* D31-D24 */ TME_BUS_LANE_ABORT,
736:
737: /* [sparc] initiator maximum cycle size: 16 bits
738: [sparc] initiator A1,A0: 01
739: [gen] responder port size: 32 bits
740: [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder)
741: (code 2.1.4.2, OP3 lane 1): */
742: /* D7-D0 */ TME_BUS_LANE_ABORT,
743: /* D15-D8 */ TME_BUS_LANE_ABORT,
744: /* D23-D16 */ TME_BUS_LANE_ABORT,
745: /* D31-D24 */ TME_BUS_LANE_ABORT,
746:
747: /* [sparc] initiator maximum cycle size: 16 bits
748: [sparc] initiator A1,A0: 01
749: [gen] responder port size: 32 bits
750: [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder)
751: (code 2.1.4.3, OP3 lane 1): */
752: /* D7-D0 */ TME_BUS_LANE_ABORT,
753: /* D15-D8 */ TME_BUS_LANE_ABORT,
754: /* D23-D16 */ TME_BUS_LANE_ABORT,
755: /* D31-D24 */ TME_BUS_LANE_ABORT,
756:
757: /* [sparc] initiator maximum cycle size: 16 bits
758: [sparc] initiator A1,A0: 10
759: [gen] responder port size: 8 bits
760: [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit sparc)
761: (code 2.2.1.0, OP3 lane 2): */
762: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
763: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
764: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
765: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
766:
767: /* [sparc] initiator maximum cycle size: 16 bits
768: [sparc] initiator A1,A0: 10
769: [gen] responder port size: 8 bits
770: [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit sparc)
771: (code 2.2.1.1, OP3 lane 2): */
772: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
773: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
774: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
775: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
776:
777: /* [sparc] initiator maximum cycle size: 16 bits
778: [sparc] initiator A1,A0: 10
779: [gen] responder port size: 8 bits
780: [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit sparc)
781: (code 2.2.1.2, OP3 lane 2): */
782: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
783: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
784: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
785: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
786:
787: /* [sparc] initiator maximum cycle size: 16 bits
788: [sparc] initiator A1,A0: 10
789: [gen] responder port size: 8 bits
790: [gen] responder port least lane: 3 (lanes D31-D24)
791: (code 2.2.1.3, OP3 lane 2): */
792: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
793: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
794: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
795: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
796:
797: /* [sparc] initiator maximum cycle size: 16 bits
798: [sparc] initiator A1,A0: 10
799: [gen] responder port size: 16 bits
800: [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit sparc)
801: (code 2.2.2.0, OP3 lane 2): */
802: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
803: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
804: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)),
805: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
806:
807: /* [sparc] initiator maximum cycle size: 16 bits
808: [sparc] initiator A1,A0: 10
809: [gen] responder port size: 16 bits
810: [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit sparc)
811: (code 2.2.2.1, OP3 lane 2): */
812: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
813: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
814: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)),
815: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
816:
817: /* [sparc] initiator maximum cycle size: 16 bits
818: [sparc] initiator A1,A0: 10
819: [gen] responder port size: 16 bits
820: [gen] responder port least lane: 2 (lanes D31-D24 D23-D16)
821: (code 2.2.2.2, OP3 lane 2): */
822: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
823: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
824: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)),
825: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
826:
827: /* [sparc] initiator maximum cycle size: 16 bits
828: [sparc] initiator A1,A0: 10
829: [gen] responder port size: 16 bits
830: [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder)
831: (code 2.2.2.3, OP3 lane 2): */
832: /* D7-D0 */ TME_BUS_LANE_ABORT,
833: /* D15-D8 */ TME_BUS_LANE_ABORT,
834: /* D23-D16 */ TME_BUS_LANE_ABORT,
835: /* D31-D24 */ TME_BUS_LANE_ABORT,
836:
837: /* [sparc] initiator maximum cycle size: 16 bits
838: [sparc] initiator A1,A0: 10
839: [gen] responder port size: 32 bits
840: [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0)
841: (code 2.2.4.0, OP3 lane 0): */
842: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)),
843: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
844: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
845: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
846:
847: /* [sparc] initiator maximum cycle size: 16 bits
848: [sparc] initiator A1,A0: 10
849: [gen] responder port size: 32 bits
850: [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder)
851: (code 2.2.4.1, OP3 lane 0): */
852: /* D7-D0 */ TME_BUS_LANE_ABORT,
853: /* D15-D8 */ TME_BUS_LANE_ABORT,
854: /* D23-D16 */ TME_BUS_LANE_ABORT,
855: /* D31-D24 */ TME_BUS_LANE_ABORT,
856:
857: /* [sparc] initiator maximum cycle size: 16 bits
858: [sparc] initiator A1,A0: 10
859: [gen] responder port size: 32 bits
860: [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder)
861: (code 2.2.4.2, OP3 lane 0): */
862: /* D7-D0 */ TME_BUS_LANE_ABORT,
863: /* D15-D8 */ TME_BUS_LANE_ABORT,
864: /* D23-D16 */ TME_BUS_LANE_ABORT,
865: /* D31-D24 */ TME_BUS_LANE_ABORT,
866:
867: /* [sparc] initiator maximum cycle size: 16 bits
868: [sparc] initiator A1,A0: 10
869: [gen] responder port size: 32 bits
870: [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder)
871: (code 2.2.4.3, OP3 lane 0): */
872: /* D7-D0 */ TME_BUS_LANE_ABORT,
873: /* D15-D8 */ TME_BUS_LANE_ABORT,
874: /* D23-D16 */ TME_BUS_LANE_ABORT,
875: /* D31-D24 */ TME_BUS_LANE_ABORT,
876:
877: /* [sparc] initiator maximum cycle size: 16 bits
878: [sparc] initiator A1,A0: 11
879: [gen] responder port size: 8 bits
880: [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit sparc)
881: (code 2.3.1.0, OP3 lane 2): */
882: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
883: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
884: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
885: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
886:
887: /* [sparc] initiator maximum cycle size: 16 bits
888: [sparc] initiator A1,A0: 11
889: [gen] responder port size: 8 bits
890: [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit sparc)
891: (code 2.3.1.1, OP3 lane 2): */
892: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
893: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
894: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
895: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
896:
897: /* [sparc] initiator maximum cycle size: 16 bits
898: [sparc] initiator A1,A0: 11
899: [gen] responder port size: 8 bits
900: [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit sparc)
901: (code 2.3.1.2, OP3 lane 2): */
902: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
903: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
904: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
905: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
906:
907: /* [sparc] initiator maximum cycle size: 16 bits
908: [sparc] initiator A1,A0: 11
909: [gen] responder port size: 8 bits
910: [gen] responder port least lane: 3 (lanes D31-D24)
911: (code 2.3.1.3, OP3 lane 2): */
912: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
913: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
914: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
915: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
916:
917: /* [sparc] initiator maximum cycle size: 16 bits
918: [sparc] initiator A1,A0: 11
919: [gen] responder port size: 16 bits
920: [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit sparc)
921: (code 2.3.2.0, OP3 lane 1): */
922: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
923: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
924: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
925: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
926:
927: /* [sparc] initiator maximum cycle size: 16 bits
928: [sparc] initiator A1,A0: 11
929: [gen] responder port size: 16 bits
930: [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit sparc)
931: (code 2.3.2.1, OP3 lane 1): */
932: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
933: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
934: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
935: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
936:
937: /* [sparc] initiator maximum cycle size: 16 bits
938: [sparc] initiator A1,A0: 11
939: [gen] responder port size: 16 bits
940: [gen] responder port least lane: 2 (lanes D31-D24 D23-D16)
941: (code 2.3.2.2, OP3 lane 1): */
942: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
943: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
944: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
945: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
946:
947: /* [sparc] initiator maximum cycle size: 16 bits
948: [sparc] initiator A1,A0: 11
949: [gen] responder port size: 16 bits
950: [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder)
951: (code 2.3.2.3, OP3 lane 1): */
952: /* D7-D0 */ TME_BUS_LANE_ABORT,
953: /* D15-D8 */ TME_BUS_LANE_ABORT,
954: /* D23-D16 */ TME_BUS_LANE_ABORT,
955: /* D31-D24 */ TME_BUS_LANE_ABORT,
956:
957: /* [sparc] initiator maximum cycle size: 16 bits
958: [sparc] initiator A1,A0: 11
959: [gen] responder port size: 32 bits
960: [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0)
961: (code 2.3.4.0, OP3 lane -1): */
962: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)),
963: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
964: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
965: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
966:
967: /* [sparc] initiator maximum cycle size: 16 bits
968: [sparc] initiator A1,A0: 11
969: [gen] responder port size: 32 bits
970: [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder)
971: (code 2.3.4.1, OP3 lane -1): */
972: /* D7-D0 */ TME_BUS_LANE_ABORT,
973: /* D15-D8 */ TME_BUS_LANE_ABORT,
974: /* D23-D16 */ TME_BUS_LANE_ABORT,
975: /* D31-D24 */ TME_BUS_LANE_ABORT,
976:
977: /* [sparc] initiator maximum cycle size: 16 bits
978: [sparc] initiator A1,A0: 11
979: [gen] responder port size: 32 bits
980: [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder)
981: (code 2.3.4.2, OP3 lane -1): */
982: /* D7-D0 */ TME_BUS_LANE_ABORT,
983: /* D15-D8 */ TME_BUS_LANE_ABORT,
984: /* D23-D16 */ TME_BUS_LANE_ABORT,
985: /* D31-D24 */ TME_BUS_LANE_ABORT,
986:
987: /* [sparc] initiator maximum cycle size: 16 bits
988: [sparc] initiator A1,A0: 11
989: [gen] responder port size: 32 bits
990: [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder)
991: (code 2.3.4.3, OP3 lane -1): */
992: /* D7-D0 */ TME_BUS_LANE_ABORT,
993: /* D15-D8 */ TME_BUS_LANE_ABORT,
994: /* D23-D16 */ TME_BUS_LANE_ABORT,
995: /* D31-D24 */ TME_BUS_LANE_ABORT,
996:
997: /* [sparc] initiator maximum cycle size: 24 bits
998: [sparc] initiator A1,A0: 00
999: [gen] responder port size: 8 bits
1000: [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit sparc)
1001: (code 3.0.1.0, OP3 lane 1): */
1002: /* D7-D0 */ TME_BUS_LANE_UNDEF | TME_BUS_LANE_WARN,
1003: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1004: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1005: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1006:
1007: /* [sparc] initiator maximum cycle size: 24 bits
1008: [sparc] initiator A1,A0: 00
1009: [gen] responder port size: 8 bits
1010: [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit sparc)
1011: (code 3.0.1.1, OP3 lane 1): */
1012: /* D7-D0 */ TME_BUS_LANE_UNDEF,
1013: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1014: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1015: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1016:
1017: /* [sparc] initiator maximum cycle size: 24 bits
1018: [sparc] initiator A1,A0: 00
1019: [gen] responder port size: 8 bits
1020: [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit sparc)
1021: (code 3.0.1.2, OP3 lane 1): */
1022: /* D7-D0 */ TME_BUS_LANE_UNDEF,
1023: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1024: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1025: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1026:
1027: /* [sparc] initiator maximum cycle size: 24 bits
1028: [sparc] initiator A1,A0: 00
1029: [gen] responder port size: 8 bits
1030: [gen] responder port least lane: 3 (lanes D31-D24)
1031: (code 3.0.1.3, OP3 lane 1): */
1032: /* D7-D0 */ TME_BUS_LANE_UNDEF,
1033: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1034: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1035: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1036:
1037: /* [sparc] initiator maximum cycle size: 24 bits
1038: [sparc] initiator A1,A0: 00
1039: [gen] responder port size: 16 bits
1040: [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit sparc)
1041: (code 3.0.2.0, OP3 lane 1): */
1042: /* D7-D0 */ TME_BUS_LANE_UNDEF | TME_BUS_LANE_WARN,
1043: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1044: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)),
1045: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1046:
1047: /* [sparc] initiator maximum cycle size: 24 bits
1048: [sparc] initiator A1,A0: 00
1049: [gen] responder port size: 16 bits
1050: [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit sparc)
1051: (code 3.0.2.1, OP3 lane 1): */
1052: /* D7-D0 */ TME_BUS_LANE_UNDEF,
1053: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1054: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)),
1055: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1056:
1057: /* [sparc] initiator maximum cycle size: 24 bits
1058: [sparc] initiator A1,A0: 00
1059: [gen] responder port size: 16 bits
1060: [gen] responder port least lane: 2 (lanes D31-D24 D23-D16)
1061: (code 3.0.2.2, OP3 lane 1): */
1062: /* D7-D0 */ TME_BUS_LANE_UNDEF,
1063: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1064: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)),
1065: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1066:
1067: /* [sparc] initiator maximum cycle size: 24 bits
1068: [sparc] initiator A1,A0: 00
1069: [gen] responder port size: 16 bits
1070: [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder)
1071: (code 3.0.2.3, OP3 lane 1): */
1072: /* D7-D0 */ TME_BUS_LANE_ABORT,
1073: /* D15-D8 */ TME_BUS_LANE_ABORT,
1074: /* D23-D16 */ TME_BUS_LANE_ABORT,
1075: /* D31-D24 */ TME_BUS_LANE_ABORT,
1076:
1077: /* [sparc] initiator maximum cycle size: 24 bits
1078: [sparc] initiator A1,A0: 00
1079: [gen] responder port size: 32 bits
1080: [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0)
1081: (code 3.0.4.0, OP3 lane 1): */
1082: /* D7-D0 */ TME_BUS_LANE_UNDEF,
1083: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)),
1084: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)),
1085: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1086:
1087: /* [sparc] initiator maximum cycle size: 24 bits
1088: [sparc] initiator A1,A0: 00
1089: [gen] responder port size: 32 bits
1090: [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder)
1091: (code 3.0.4.1, OP3 lane 1): */
1092: /* D7-D0 */ TME_BUS_LANE_ABORT,
1093: /* D15-D8 */ TME_BUS_LANE_ABORT,
1094: /* D23-D16 */ TME_BUS_LANE_ABORT,
1095: /* D31-D24 */ TME_BUS_LANE_ABORT,
1096:
1097: /* [sparc] initiator maximum cycle size: 24 bits
1098: [sparc] initiator A1,A0: 00
1099: [gen] responder port size: 32 bits
1100: [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder)
1101: (code 3.0.4.2, OP3 lane 1): */
1102: /* D7-D0 */ TME_BUS_LANE_ABORT,
1103: /* D15-D8 */ TME_BUS_LANE_ABORT,
1104: /* D23-D16 */ TME_BUS_LANE_ABORT,
1105: /* D31-D24 */ TME_BUS_LANE_ABORT,
1106:
1107: /* [sparc] initiator maximum cycle size: 24 bits
1108: [sparc] initiator A1,A0: 00
1109: [gen] responder port size: 32 bits
1110: [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder)
1111: (code 3.0.4.3, OP3 lane 1): */
1112: /* D7-D0 */ TME_BUS_LANE_ABORT,
1113: /* D15-D8 */ TME_BUS_LANE_ABORT,
1114: /* D23-D16 */ TME_BUS_LANE_ABORT,
1115: /* D31-D24 */ TME_BUS_LANE_ABORT,
1116:
1117: /* [sparc] initiator maximum cycle size: 24 bits
1118: [sparc] initiator A1,A0: 01
1119: [gen] responder port size: 8 bits
1120: [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit sparc)
1121: (code 3.1.1.0, OP3 lane 1): */
1122: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1123: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1124: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1125: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1126:
1127: /* [sparc] initiator maximum cycle size: 24 bits
1128: [sparc] initiator A1,A0: 01
1129: [gen] responder port size: 8 bits
1130: [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit sparc)
1131: (code 3.1.1.1, OP3 lane 1): */
1132: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1133: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1134: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1135: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1136:
1137: /* [sparc] initiator maximum cycle size: 24 bits
1138: [sparc] initiator A1,A0: 01
1139: [gen] responder port size: 8 bits
1140: [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit sparc)
1141: (code 3.1.1.2, OP3 lane 1): */
1142: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1143: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1144: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1145: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1146:
1147: /* [sparc] initiator maximum cycle size: 24 bits
1148: [sparc] initiator A1,A0: 01
1149: [gen] responder port size: 8 bits
1150: [gen] responder port least lane: 3 (lanes D31-D24)
1151: (code 3.1.1.3, OP3 lane 1): */
1152: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1153: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1154: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1155: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1156:
1157: /* [sparc] initiator maximum cycle size: 24 bits
1158: [sparc] initiator A1,A0: 01
1159: [gen] responder port size: 16 bits
1160: [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit sparc)
1161: (code 3.1.2.0, OP3 lane 0): */
1162: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1163: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1164: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1165: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1166:
1167: /* [sparc] initiator maximum cycle size: 24 bits
1168: [sparc] initiator A1,A0: 01
1169: [gen] responder port size: 16 bits
1170: [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit sparc)
1171: (code 3.1.2.1, OP3 lane 0): */
1172: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1173: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1174: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1175: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1176:
1177: /* [sparc] initiator maximum cycle size: 24 bits
1178: [sparc] initiator A1,A0: 01
1179: [gen] responder port size: 16 bits
1180: [gen] responder port least lane: 2 (lanes D31-D24 D23-D16)
1181: (code 3.1.2.2, OP3 lane 0): */
1182: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1183: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1184: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1185: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1186:
1187: /* [sparc] initiator maximum cycle size: 24 bits
1188: [sparc] initiator A1,A0: 01
1189: [gen] responder port size: 16 bits
1190: [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder)
1191: (code 3.1.2.3, OP3 lane 0): */
1192: /* D7-D0 */ TME_BUS_LANE_ABORT,
1193: /* D15-D8 */ TME_BUS_LANE_ABORT,
1194: /* D23-D16 */ TME_BUS_LANE_ABORT,
1195: /* D31-D24 */ TME_BUS_LANE_ABORT,
1196:
1197: /* [sparc] initiator maximum cycle size: 24 bits
1198: [sparc] initiator A1,A0: 01
1199: [gen] responder port size: 32 bits
1200: [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0)
1201: (code 3.1.4.0, OP3 lane 0): */
1202: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)),
1203: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)),
1204: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1205: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1206:
1207: /* [sparc] initiator maximum cycle size: 24 bits
1208: [sparc] initiator A1,A0: 01
1209: [gen] responder port size: 32 bits
1210: [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder)
1211: (code 3.1.4.1, OP3 lane 0): */
1212: /* D7-D0 */ TME_BUS_LANE_ABORT,
1213: /* D15-D8 */ TME_BUS_LANE_ABORT,
1214: /* D23-D16 */ TME_BUS_LANE_ABORT,
1215: /* D31-D24 */ TME_BUS_LANE_ABORT,
1216:
1217: /* [sparc] initiator maximum cycle size: 24 bits
1218: [sparc] initiator A1,A0: 01
1219: [gen] responder port size: 32 bits
1220: [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder)
1221: (code 3.1.4.2, OP3 lane 0): */
1222: /* D7-D0 */ TME_BUS_LANE_ABORT,
1223: /* D15-D8 */ TME_BUS_LANE_ABORT,
1224: /* D23-D16 */ TME_BUS_LANE_ABORT,
1225: /* D31-D24 */ TME_BUS_LANE_ABORT,
1226:
1227: /* [sparc] initiator maximum cycle size: 24 bits
1228: [sparc] initiator A1,A0: 01
1229: [gen] responder port size: 32 bits
1230: [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder)
1231: (code 3.1.4.3, OP3 lane 0): */
1232: /* D7-D0 */ TME_BUS_LANE_ABORT,
1233: /* D15-D8 */ TME_BUS_LANE_ABORT,
1234: /* D23-D16 */ TME_BUS_LANE_ABORT,
1235: /* D31-D24 */ TME_BUS_LANE_ABORT,
1236:
1237: /* [sparc] initiator maximum cycle size: 24 bits
1238: [sparc] initiator A1,A0: 10
1239: [gen] responder port size: 8 bits
1240: [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit sparc)
1241: (code 3.2.1.0, OP3 lane 1): */
1242: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1243: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1244: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1245: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1246:
1247: /* [sparc] initiator maximum cycle size: 24 bits
1248: [sparc] initiator A1,A0: 10
1249: [gen] responder port size: 8 bits
1250: [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit sparc)
1251: (code 3.2.1.1, OP3 lane 1): */
1252: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1253: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1254: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1255: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1256:
1257: /* [sparc] initiator maximum cycle size: 24 bits
1258: [sparc] initiator A1,A0: 10
1259: [gen] responder port size: 8 bits
1260: [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit sparc)
1261: (code 3.2.1.2, OP3 lane 1): */
1262: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1263: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1264: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1265: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1266:
1267: /* [sparc] initiator maximum cycle size: 24 bits
1268: [sparc] initiator A1,A0: 10
1269: [gen] responder port size: 8 bits
1270: [gen] responder port least lane: 3 (lanes D31-D24)
1271: (code 3.2.1.3, OP3 lane 1): */
1272: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1273: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1274: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1275: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1276:
1277: /* [sparc] initiator maximum cycle size: 24 bits
1278: [sparc] initiator A1,A0: 10
1279: [gen] responder port size: 16 bits
1280: [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit sparc)
1281: (code 3.2.2.0, OP3 lane 1): */
1282: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1283: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1284: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)),
1285: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1286:
1287: /* [sparc] initiator maximum cycle size: 24 bits
1288: [sparc] initiator A1,A0: 10
1289: [gen] responder port size: 16 bits
1290: [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit sparc)
1291: (code 3.2.2.1, OP3 lane 1): */
1292: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1293: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1294: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)),
1295: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1296:
1297: /* [sparc] initiator maximum cycle size: 24 bits
1298: [sparc] initiator A1,A0: 10
1299: [gen] responder port size: 16 bits
1300: [gen] responder port least lane: 2 (lanes D31-D24 D23-D16)
1301: (code 3.2.2.2, OP3 lane 1): */
1302: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1303: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1304: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)),
1305: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1306:
1307: /* [sparc] initiator maximum cycle size: 24 bits
1308: [sparc] initiator A1,A0: 10
1309: [gen] responder port size: 16 bits
1310: [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder)
1311: (code 3.2.2.3, OP3 lane 1): */
1312: /* D7-D0 */ TME_BUS_LANE_ABORT,
1313: /* D15-D8 */ TME_BUS_LANE_ABORT,
1314: /* D23-D16 */ TME_BUS_LANE_ABORT,
1315: /* D31-D24 */ TME_BUS_LANE_ABORT,
1316:
1317: /* [sparc] initiator maximum cycle size: 24 bits
1318: [sparc] initiator A1,A0: 10
1319: [gen] responder port size: 32 bits
1320: [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0)
1321: (code 3.2.4.0, OP3 lane -1): */
1322: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)),
1323: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1324: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1325: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1326:
1327: /* [sparc] initiator maximum cycle size: 24 bits
1328: [sparc] initiator A1,A0: 10
1329: [gen] responder port size: 32 bits
1330: [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder)
1331: (code 3.2.4.1, OP3 lane -1): */
1332: /* D7-D0 */ TME_BUS_LANE_ABORT,
1333: /* D15-D8 */ TME_BUS_LANE_ABORT,
1334: /* D23-D16 */ TME_BUS_LANE_ABORT,
1335: /* D31-D24 */ TME_BUS_LANE_ABORT,
1336:
1337: /* [sparc] initiator maximum cycle size: 24 bits
1338: [sparc] initiator A1,A0: 10
1339: [gen] responder port size: 32 bits
1340: [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder)
1341: (code 3.2.4.2, OP3 lane -1): */
1342: /* D7-D0 */ TME_BUS_LANE_ABORT,
1343: /* D15-D8 */ TME_BUS_LANE_ABORT,
1344: /* D23-D16 */ TME_BUS_LANE_ABORT,
1345: /* D31-D24 */ TME_BUS_LANE_ABORT,
1346:
1347: /* [sparc] initiator maximum cycle size: 24 bits
1348: [sparc] initiator A1,A0: 10
1349: [gen] responder port size: 32 bits
1350: [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder)
1351: (code 3.2.4.3, OP3 lane -1): */
1352: /* D7-D0 */ TME_BUS_LANE_ABORT,
1353: /* D15-D8 */ TME_BUS_LANE_ABORT,
1354: /* D23-D16 */ TME_BUS_LANE_ABORT,
1355: /* D31-D24 */ TME_BUS_LANE_ABORT,
1356:
1357: /* [sparc] initiator maximum cycle size: 24 bits
1358: [sparc] initiator A1,A0: 11
1359: [gen] responder port size: 8 bits
1360: [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit sparc)
1361: (code 3.3.1.0, OP3 lane 1): */
1362: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1363: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1364: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1365: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1366:
1367: /* [sparc] initiator maximum cycle size: 24 bits
1368: [sparc] initiator A1,A0: 11
1369: [gen] responder port size: 8 bits
1370: [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit sparc)
1371: (code 3.3.1.1, OP3 lane 1): */
1372: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1373: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1374: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1375: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1376:
1377: /* [sparc] initiator maximum cycle size: 24 bits
1378: [sparc] initiator A1,A0: 11
1379: [gen] responder port size: 8 bits
1380: [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit sparc)
1381: (code 3.3.1.2, OP3 lane 1): */
1382: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1383: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1384: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1385: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1386:
1387: /* [sparc] initiator maximum cycle size: 24 bits
1388: [sparc] initiator A1,A0: 11
1389: [gen] responder port size: 8 bits
1390: [gen] responder port least lane: 3 (lanes D31-D24)
1391: (code 3.3.1.3, OP3 lane 1): */
1392: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1393: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1394: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1395: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1396:
1397: /* [sparc] initiator maximum cycle size: 24 bits
1398: [sparc] initiator A1,A0: 11
1399: [gen] responder port size: 16 bits
1400: [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit sparc)
1401: (code 3.3.2.0, OP3 lane 0): */
1402: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1403: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1404: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1405: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1406:
1407: /* [sparc] initiator maximum cycle size: 24 bits
1408: [sparc] initiator A1,A0: 11
1409: [gen] responder port size: 16 bits
1410: [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit sparc)
1411: (code 3.3.2.1, OP3 lane 0): */
1412: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1413: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1414: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1415: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1416:
1417: /* [sparc] initiator maximum cycle size: 24 bits
1418: [sparc] initiator A1,A0: 11
1419: [gen] responder port size: 16 bits
1420: [gen] responder port least lane: 2 (lanes D31-D24 D23-D16)
1421: (code 3.3.2.2, OP3 lane 0): */
1422: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1423: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1424: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1425: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1426:
1427: /* [sparc] initiator maximum cycle size: 24 bits
1428: [sparc] initiator A1,A0: 11
1429: [gen] responder port size: 16 bits
1430: [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder)
1431: (code 3.3.2.3, OP3 lane 0): */
1432: /* D7-D0 */ TME_BUS_LANE_ABORT,
1433: /* D15-D8 */ TME_BUS_LANE_ABORT,
1434: /* D23-D16 */ TME_BUS_LANE_ABORT,
1435: /* D31-D24 */ TME_BUS_LANE_ABORT,
1436:
1437: /* [sparc] initiator maximum cycle size: 24 bits
1438: [sparc] initiator A1,A0: 11
1439: [gen] responder port size: 32 bits
1440: [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0)
1441: (code 3.3.4.0, OP3 lane -2): */
1442: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)),
1443: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1444: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1445: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1446:
1447: /* [sparc] initiator maximum cycle size: 24 bits
1448: [sparc] initiator A1,A0: 11
1449: [gen] responder port size: 32 bits
1450: [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder)
1451: (code 3.3.4.1, OP3 lane -2): */
1452: /* D7-D0 */ TME_BUS_LANE_ABORT,
1453: /* D15-D8 */ TME_BUS_LANE_ABORT,
1454: /* D23-D16 */ TME_BUS_LANE_ABORT,
1455: /* D31-D24 */ TME_BUS_LANE_ABORT,
1456:
1457: /* [sparc] initiator maximum cycle size: 24 bits
1458: [sparc] initiator A1,A0: 11
1459: [gen] responder port size: 32 bits
1460: [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder)
1461: (code 3.3.4.2, OP3 lane -2): */
1462: /* D7-D0 */ TME_BUS_LANE_ABORT,
1463: /* D15-D8 */ TME_BUS_LANE_ABORT,
1464: /* D23-D16 */ TME_BUS_LANE_ABORT,
1465: /* D31-D24 */ TME_BUS_LANE_ABORT,
1466:
1467: /* [sparc] initiator maximum cycle size: 24 bits
1468: [sparc] initiator A1,A0: 11
1469: [gen] responder port size: 32 bits
1470: [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder)
1471: (code 3.3.4.3, OP3 lane -2): */
1472: /* D7-D0 */ TME_BUS_LANE_ABORT,
1473: /* D15-D8 */ TME_BUS_LANE_ABORT,
1474: /* D23-D16 */ TME_BUS_LANE_ABORT,
1475: /* D31-D24 */ TME_BUS_LANE_ABORT,
1476:
1477: /* [sparc] initiator maximum cycle size: 32 bits
1478: [sparc] initiator A1,A0: 00
1479: [gen] responder port size: 8 bits
1480: [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit sparc)
1481: (code 4.0.1.0, OP3 lane 0): */
1482: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1483: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1484: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1485: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1486:
1487: /* [sparc] initiator maximum cycle size: 32 bits
1488: [sparc] initiator A1,A0: 00
1489: [gen] responder port size: 8 bits
1490: [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit sparc)
1491: (code 4.0.1.1, OP3 lane 0): */
1492: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1493: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1494: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1495: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1496:
1497: /* [sparc] initiator maximum cycle size: 32 bits
1498: [sparc] initiator A1,A0: 00
1499: [gen] responder port size: 8 bits
1500: [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit sparc)
1501: (code 4.0.1.2, OP3 lane 0): */
1502: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1503: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1504: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1505: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1506:
1507: /* [sparc] initiator maximum cycle size: 32 bits
1508: [sparc] initiator A1,A0: 00
1509: [gen] responder port size: 8 bits
1510: [gen] responder port least lane: 3 (lanes D31-D24)
1511: (code 4.0.1.3, OP3 lane 0): */
1512: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1513: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1514: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1515: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1516:
1517: /* [sparc] initiator maximum cycle size: 32 bits
1518: [sparc] initiator A1,A0: 00
1519: [gen] responder port size: 16 bits
1520: [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit sparc)
1521: (code 4.0.2.0, OP3 lane 0): */
1522: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1523: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1524: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)),
1525: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1526:
1527: /* [sparc] initiator maximum cycle size: 32 bits
1528: [sparc] initiator A1,A0: 00
1529: [gen] responder port size: 16 bits
1530: [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit sparc)
1531: (code 4.0.2.1, OP3 lane 0): */
1532: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1533: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1534: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)),
1535: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1536:
1537: /* [sparc] initiator maximum cycle size: 32 bits
1538: [sparc] initiator A1,A0: 00
1539: [gen] responder port size: 16 bits
1540: [gen] responder port least lane: 2 (lanes D31-D24 D23-D16)
1541: (code 4.0.2.2, OP3 lane 0): */
1542: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1543: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1544: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)),
1545: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1546:
1547: /* [sparc] initiator maximum cycle size: 32 bits
1548: [sparc] initiator A1,A0: 00
1549: [gen] responder port size: 16 bits
1550: [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder)
1551: (code 4.0.2.3, OP3 lane 0): */
1552: /* D7-D0 */ TME_BUS_LANE_ABORT,
1553: /* D15-D8 */ TME_BUS_LANE_ABORT,
1554: /* D23-D16 */ TME_BUS_LANE_ABORT,
1555: /* D31-D24 */ TME_BUS_LANE_ABORT,
1556:
1557: /* [sparc] initiator maximum cycle size: 32 bits
1558: [sparc] initiator A1,A0: 00
1559: [gen] responder port size: 32 bits
1560: [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0)
1561: (code 4.0.4.0, OP3 lane 0): */
1562: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(3)),
1563: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)),
1564: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)),
1565: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1566:
1567: /* [sparc] initiator maximum cycle size: 32 bits
1568: [sparc] initiator A1,A0: 00
1569: [gen] responder port size: 32 bits
1570: [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder)
1571: (code 4.0.4.1, OP3 lane 0): */
1572: /* D7-D0 */ TME_BUS_LANE_ABORT,
1573: /* D15-D8 */ TME_BUS_LANE_ABORT,
1574: /* D23-D16 */ TME_BUS_LANE_ABORT,
1575: /* D31-D24 */ TME_BUS_LANE_ABORT,
1576:
1577: /* [sparc] initiator maximum cycle size: 32 bits
1578: [sparc] initiator A1,A0: 00
1579: [gen] responder port size: 32 bits
1580: [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder)
1581: (code 4.0.4.2, OP3 lane 0): */
1582: /* D7-D0 */ TME_BUS_LANE_ABORT,
1583: /* D15-D8 */ TME_BUS_LANE_ABORT,
1584: /* D23-D16 */ TME_BUS_LANE_ABORT,
1585: /* D31-D24 */ TME_BUS_LANE_ABORT,
1586:
1587: /* [sparc] initiator maximum cycle size: 32 bits
1588: [sparc] initiator A1,A0: 00
1589: [gen] responder port size: 32 bits
1590: [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder)
1591: (code 4.0.4.3, OP3 lane 0): */
1592: /* D7-D0 */ TME_BUS_LANE_ABORT,
1593: /* D15-D8 */ TME_BUS_LANE_ABORT,
1594: /* D23-D16 */ TME_BUS_LANE_ABORT,
1595: /* D31-D24 */ TME_BUS_LANE_ABORT,
1596:
1597: /* [sparc] initiator maximum cycle size: 32 bits
1598: [sparc] initiator A1,A0: 01
1599: [gen] responder port size: 8 bits
1600: [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit sparc)
1601: (code 4.1.1.0, OP3 lane 0): */
1602: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1603: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1604: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1605: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1606:
1607: /* [sparc] initiator maximum cycle size: 32 bits
1608: [sparc] initiator A1,A0: 01
1609: [gen] responder port size: 8 bits
1610: [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit sparc)
1611: (code 4.1.1.1, OP3 lane 0): */
1612: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1613: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1614: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1615: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1616:
1617: /* [sparc] initiator maximum cycle size: 32 bits
1618: [sparc] initiator A1,A0: 01
1619: [gen] responder port size: 8 bits
1620: [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit sparc)
1621: (code 4.1.1.2, OP3 lane 0): */
1622: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1623: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1624: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1625: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1626:
1627: /* [sparc] initiator maximum cycle size: 32 bits
1628: [sparc] initiator A1,A0: 01
1629: [gen] responder port size: 8 bits
1630: [gen] responder port least lane: 3 (lanes D31-D24)
1631: (code 4.1.1.3, OP3 lane 0): */
1632: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1633: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1634: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1635: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1636:
1637: /* [sparc] initiator maximum cycle size: 32 bits
1638: [sparc] initiator A1,A0: 01
1639: [gen] responder port size: 16 bits
1640: [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit sparc)
1641: (code 4.1.2.0, OP3 lane -1): */
1642: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1643: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1644: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1645: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1646:
1647: /* [sparc] initiator maximum cycle size: 32 bits
1648: [sparc] initiator A1,A0: 01
1649: [gen] responder port size: 16 bits
1650: [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit sparc)
1651: (code 4.1.2.1, OP3 lane -1): */
1652: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1653: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1654: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1655: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1656:
1657: /* [sparc] initiator maximum cycle size: 32 bits
1658: [sparc] initiator A1,A0: 01
1659: [gen] responder port size: 16 bits
1660: [gen] responder port least lane: 2 (lanes D31-D24 D23-D16)
1661: (code 4.1.2.2, OP3 lane -1): */
1662: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1663: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1664: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1665: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1666:
1667: /* [sparc] initiator maximum cycle size: 32 bits
1668: [sparc] initiator A1,A0: 01
1669: [gen] responder port size: 16 bits
1670: [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder)
1671: (code 4.1.2.3, OP3 lane -1): */
1672: /* D7-D0 */ TME_BUS_LANE_ABORT,
1673: /* D15-D8 */ TME_BUS_LANE_ABORT,
1674: /* D23-D16 */ TME_BUS_LANE_ABORT,
1675: /* D31-D24 */ TME_BUS_LANE_ABORT,
1676:
1677: /* [sparc] initiator maximum cycle size: 32 bits
1678: [sparc] initiator A1,A0: 01
1679: [gen] responder port size: 32 bits
1680: [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0)
1681: (code 4.1.4.0, OP3 lane -1): */
1682: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)),
1683: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)),
1684: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1685: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1686:
1687: /* [sparc] initiator maximum cycle size: 32 bits
1688: [sparc] initiator A1,A0: 01
1689: [gen] responder port size: 32 bits
1690: [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder)
1691: (code 4.1.4.1, OP3 lane -1): */
1692: /* D7-D0 */ TME_BUS_LANE_ABORT,
1693: /* D15-D8 */ TME_BUS_LANE_ABORT,
1694: /* D23-D16 */ TME_BUS_LANE_ABORT,
1695: /* D31-D24 */ TME_BUS_LANE_ABORT,
1696:
1697: /* [sparc] initiator maximum cycle size: 32 bits
1698: [sparc] initiator A1,A0: 01
1699: [gen] responder port size: 32 bits
1700: [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder)
1701: (code 4.1.4.2, OP3 lane -1): */
1702: /* D7-D0 */ TME_BUS_LANE_ABORT,
1703: /* D15-D8 */ TME_BUS_LANE_ABORT,
1704: /* D23-D16 */ TME_BUS_LANE_ABORT,
1705: /* D31-D24 */ TME_BUS_LANE_ABORT,
1706:
1707: /* [sparc] initiator maximum cycle size: 32 bits
1708: [sparc] initiator A1,A0: 01
1709: [gen] responder port size: 32 bits
1710: [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder)
1711: (code 4.1.4.3, OP3 lane -1): */
1712: /* D7-D0 */ TME_BUS_LANE_ABORT,
1713: /* D15-D8 */ TME_BUS_LANE_ABORT,
1714: /* D23-D16 */ TME_BUS_LANE_ABORT,
1715: /* D31-D24 */ TME_BUS_LANE_ABORT,
1716:
1717: /* [sparc] initiator maximum cycle size: 32 bits
1718: [sparc] initiator A1,A0: 10
1719: [gen] responder port size: 8 bits
1720: [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit sparc)
1721: (code 4.2.1.0, OP3 lane 0): */
1722: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1723: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1724: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1725: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1726:
1727: /* [sparc] initiator maximum cycle size: 32 bits
1728: [sparc] initiator A1,A0: 10
1729: [gen] responder port size: 8 bits
1730: [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit sparc)
1731: (code 4.2.1.1, OP3 lane 0): */
1732: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1733: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1734: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1735: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1736:
1737: /* [sparc] initiator maximum cycle size: 32 bits
1738: [sparc] initiator A1,A0: 10
1739: [gen] responder port size: 8 bits
1740: [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit sparc)
1741: (code 4.2.1.2, OP3 lane 0): */
1742: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1743: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1744: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1745: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1746:
1747: /* [sparc] initiator maximum cycle size: 32 bits
1748: [sparc] initiator A1,A0: 10
1749: [gen] responder port size: 8 bits
1750: [gen] responder port least lane: 3 (lanes D31-D24)
1751: (code 4.2.1.3, OP3 lane 0): */
1752: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1753: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1754: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1755: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1756:
1757: /* [sparc] initiator maximum cycle size: 32 bits
1758: [sparc] initiator A1,A0: 10
1759: [gen] responder port size: 16 bits
1760: [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit sparc)
1761: (code 4.2.2.0, OP3 lane 0): */
1762: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1763: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1764: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)),
1765: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1766:
1767: /* [sparc] initiator maximum cycle size: 32 bits
1768: [sparc] initiator A1,A0: 10
1769: [gen] responder port size: 16 bits
1770: [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit sparc)
1771: (code 4.2.2.1, OP3 lane 0): */
1772: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1773: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1774: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)),
1775: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1776:
1777: /* [sparc] initiator maximum cycle size: 32 bits
1778: [sparc] initiator A1,A0: 10
1779: [gen] responder port size: 16 bits
1780: [gen] responder port least lane: 2 (lanes D31-D24 D23-D16)
1781: (code 4.2.2.2, OP3 lane 0): */
1782: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1783: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1784: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)),
1785: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1786:
1787: /* [sparc] initiator maximum cycle size: 32 bits
1788: [sparc] initiator A1,A0: 10
1789: [gen] responder port size: 16 bits
1790: [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder)
1791: (code 4.2.2.3, OP3 lane 0): */
1792: /* D7-D0 */ TME_BUS_LANE_ABORT,
1793: /* D15-D8 */ TME_BUS_LANE_ABORT,
1794: /* D23-D16 */ TME_BUS_LANE_ABORT,
1795: /* D31-D24 */ TME_BUS_LANE_ABORT,
1796:
1797: /* [sparc] initiator maximum cycle size: 32 bits
1798: [sparc] initiator A1,A0: 10
1799: [gen] responder port size: 32 bits
1800: [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0)
1801: (code 4.2.4.0, OP3 lane -2): */
1802: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)),
1803: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1804: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1805: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1806:
1807: /* [sparc] initiator maximum cycle size: 32 bits
1808: [sparc] initiator A1,A0: 10
1809: [gen] responder port size: 32 bits
1810: [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder)
1811: (code 4.2.4.1, OP3 lane -2): */
1812: /* D7-D0 */ TME_BUS_LANE_ABORT,
1813: /* D15-D8 */ TME_BUS_LANE_ABORT,
1814: /* D23-D16 */ TME_BUS_LANE_ABORT,
1815: /* D31-D24 */ TME_BUS_LANE_ABORT,
1816:
1817: /* [sparc] initiator maximum cycle size: 32 bits
1818: [sparc] initiator A1,A0: 10
1819: [gen] responder port size: 32 bits
1820: [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder)
1821: (code 4.2.4.2, OP3 lane -2): */
1822: /* D7-D0 */ TME_BUS_LANE_ABORT,
1823: /* D15-D8 */ TME_BUS_LANE_ABORT,
1824: /* D23-D16 */ TME_BUS_LANE_ABORT,
1825: /* D31-D24 */ TME_BUS_LANE_ABORT,
1826:
1827: /* [sparc] initiator maximum cycle size: 32 bits
1828: [sparc] initiator A1,A0: 10
1829: [gen] responder port size: 32 bits
1830: [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder)
1831: (code 4.2.4.3, OP3 lane -2): */
1832: /* D7-D0 */ TME_BUS_LANE_ABORT,
1833: /* D15-D8 */ TME_BUS_LANE_ABORT,
1834: /* D23-D16 */ TME_BUS_LANE_ABORT,
1835: /* D31-D24 */ TME_BUS_LANE_ABORT,
1836:
1837: /* [sparc] initiator maximum cycle size: 32 bits
1838: [sparc] initiator A1,A0: 11
1839: [gen] responder port size: 8 bits
1840: [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit sparc)
1841: (code 4.3.1.0, OP3 lane 0): */
1842: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1843: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1844: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1845: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1846:
1847: /* [sparc] initiator maximum cycle size: 32 bits
1848: [sparc] initiator A1,A0: 11
1849: [gen] responder port size: 8 bits
1850: [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit sparc)
1851: (code 4.3.1.1, OP3 lane 0): */
1852: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1853: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1854: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1855: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1856:
1857: /* [sparc] initiator maximum cycle size: 32 bits
1858: [sparc] initiator A1,A0: 11
1859: [gen] responder port size: 8 bits
1860: [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit sparc)
1861: (code 4.3.1.2, OP3 lane 0): */
1862: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1863: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1864: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1865: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1866:
1867: /* [sparc] initiator maximum cycle size: 32 bits
1868: [sparc] initiator A1,A0: 11
1869: [gen] responder port size: 8 bits
1870: [gen] responder port least lane: 3 (lanes D31-D24)
1871: (code 4.3.1.3, OP3 lane 0): */
1872: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1873: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1874: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1875: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1876:
1877: /* [sparc] initiator maximum cycle size: 32 bits
1878: [sparc] initiator A1,A0: 11
1879: [gen] responder port size: 16 bits
1880: [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit sparc)
1881: (code 4.3.2.0, OP3 lane -1): */
1882: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1883: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1884: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1885: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1886:
1887: /* [sparc] initiator maximum cycle size: 32 bits
1888: [sparc] initiator A1,A0: 11
1889: [gen] responder port size: 16 bits
1890: [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit sparc)
1891: (code 4.3.2.1, OP3 lane -1): */
1892: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1893: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN,
1894: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1895: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1896:
1897: /* [sparc] initiator maximum cycle size: 32 bits
1898: [sparc] initiator A1,A0: 11
1899: [gen] responder port size: 16 bits
1900: [gen] responder port least lane: 2 (lanes D31-D24 D23-D16)
1901: (code 4.3.2.2, OP3 lane -1): */
1902: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1903: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1904: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1905: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1906:
1907: /* [sparc] initiator maximum cycle size: 32 bits
1908: [sparc] initiator A1,A0: 11
1909: [gen] responder port size: 16 bits
1910: [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder)
1911: (code 4.3.2.3, OP3 lane -1): */
1912: /* D7-D0 */ TME_BUS_LANE_ABORT,
1913: /* D15-D8 */ TME_BUS_LANE_ABORT,
1914: /* D23-D16 */ TME_BUS_LANE_ABORT,
1915: /* D31-D24 */ TME_BUS_LANE_ABORT,
1916:
1917: /* [sparc] initiator maximum cycle size: 32 bits
1918: [sparc] initiator A1,A0: 11
1919: [gen] responder port size: 32 bits
1920: [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0)
1921: (code 4.3.4.0, OP3 lane -3): */
1922: /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)),
1923: /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1924: /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1925: /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE,
1926:
1927: /* [sparc] initiator maximum cycle size: 32 bits
1928: [sparc] initiator A1,A0: 11
1929: [gen] responder port size: 32 bits
1930: [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder)
1931: (code 4.3.4.1, OP3 lane -3): */
1932: /* D7-D0 */ TME_BUS_LANE_ABORT,
1933: /* D15-D8 */ TME_BUS_LANE_ABORT,
1934: /* D23-D16 */ TME_BUS_LANE_ABORT,
1935: /* D31-D24 */ TME_BUS_LANE_ABORT,
1936:
1937: /* [sparc] initiator maximum cycle size: 32 bits
1938: [sparc] initiator A1,A0: 11
1939: [gen] responder port size: 32 bits
1940: [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder)
1941: (code 4.3.4.2, OP3 lane -3): */
1942: /* D7-D0 */ TME_BUS_LANE_ABORT,
1943: /* D15-D8 */ TME_BUS_LANE_ABORT,
1944: /* D23-D16 */ TME_BUS_LANE_ABORT,
1945: /* D31-D24 */ TME_BUS_LANE_ABORT,
1946:
1947: /* [sparc] initiator maximum cycle size: 32 bits
1948: [sparc] initiator A1,A0: 11
1949: [gen] responder port size: 32 bits
1950: [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder)
1951: (code 4.3.4.3, OP3 lane -3): */
1952: /* D7-D0 */ TME_BUS_LANE_ABORT,
1953: /* D15-D8 */ TME_BUS_LANE_ABORT,
1954: /* D23-D16 */ TME_BUS_LANE_ABORT,
1955: /* D31-D24 */ TME_BUS_LANE_ABORT,
1956: };
1957: #undef SIZ8_OP
1958: #undef SIZ16_OP
1959: #undef SIZ24_OP
1960: #undef SIZ32_OP
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