--- tme/ic/sparc/sparc-fpu-auto.c 2018/04/24 16:42:00 1.1.1.1 +++ tme/ic/sparc/sparc-fpu-auto.c 2018/04/24 16:43:50 1.1.1.2 @@ -1,5 +1,5 @@ /* automatically generated by sparc-fpu-auto.sh, do not edit! */ -_TME_RCSID("$Id: sparc-fpu-auto.c,v 1.1.1.1 2018/04/24 16:42:00 root Exp $"); +_TME_RCSID("$Id: sparc-fpu-auto.c,v 1.1.1.2 2018/04/24 16:43:50 root Exp $"); /* this sets the floating-point condition codes after a single-precision operation: */ @@ -7,6 +7,7 @@ static void inline _tme_sparc_fpu_fcc_single(struct tme_sparc *ic, const struct tme_float *dst, int trap_on_nan) { tme_uint32_t fcc; + unsigned int cc; /* set fcc: */ fcc = (tme_float_is_nan(dst, (TME_FLOAT_FORMAT_IEEE754_SINGLE | TME_FLOAT_FORMAT_IEEE754_SINGLE_BUILTIN)) @@ -23,6 +24,17 @@ _tme_sparc_fpu_fcc_single(struct tme_spa } /* set the floating-point condition codes: */ + if (TME_SPARC_VERSION(ic) >= 9) { + cc = TME_FIELD_MASK_EXTRACTU(TME_SPARC_INSN, (0x3 << 25)); + if (cc != 0) { + fcc = TME_FIELD_MASK_EXTRACTU(fcc, TME_SPARC_FSR_FCC); + ic->tme_sparc_fpu_xfsr + = ((ic->tme_sparc_fpu_xfsr + & ~ (tme_uint32_t) (0x3 << (2 * (cc - 1)))) + | (fcc << (2 * (cc - 1)))); + return; + } + } ic->tme_sparc_fpu_fsr = (ic->tme_sparc_fpu_fsr & ~TME_SPARC_FSR_FCC) | fcc; } @@ -78,6 +90,7 @@ static void inline _tme_sparc_fpu_fcc_double(struct tme_sparc *ic, const struct tme_float *dst, int trap_on_nan) { tme_uint32_t fcc; + unsigned int cc; /* set fcc: */ fcc = (tme_float_is_nan(dst, (TME_FLOAT_FORMAT_IEEE754_DOUBLE | TME_FLOAT_FORMAT_IEEE754_DOUBLE_BUILTIN)) @@ -94,6 +107,17 @@ _tme_sparc_fpu_fcc_double(struct tme_spa } /* set the floating-point condition codes: */ + if (TME_SPARC_VERSION(ic) >= 9) { + cc = TME_FIELD_MASK_EXTRACTU(TME_SPARC_INSN, (0x3 << 25)); + if (cc != 0) { + fcc = TME_FIELD_MASK_EXTRACTU(fcc, TME_SPARC_FSR_FCC); + ic->tme_sparc_fpu_xfsr + = ((ic->tme_sparc_fpu_xfsr + & ~ (tme_uint32_t) (0x3 << (2 * (cc - 1)))) + | (fcc << (2 * (cc - 1)))); + return; + } + } ic->tme_sparc_fpu_fsr = (ic->tme_sparc_fpu_fsr & ~TME_SPARC_FSR_FCC) | fcc; } @@ -149,6 +173,7 @@ static void inline _tme_sparc_fpu_fcc_quad(struct tme_sparc *ic, const struct tme_float *dst, int trap_on_nan) { tme_uint32_t fcc; + unsigned int cc; /* set fcc: */ fcc = (tme_float_is_nan(dst, (TME_FLOAT_FORMAT_IEEE754_QUAD | TME_FLOAT_FORMAT_IEEE754_QUAD_BUILTIN)) @@ -165,6 +190,17 @@ _tme_sparc_fpu_fcc_quad(struct tme_sparc } /* set the floating-point condition codes: */ + if (TME_SPARC_VERSION(ic) >= 9) { + cc = TME_FIELD_MASK_EXTRACTU(TME_SPARC_INSN, (0x3 << 25)); + if (cc != 0) { + fcc = TME_FIELD_MASK_EXTRACTU(fcc, TME_SPARC_FSR_FCC); + ic->tme_sparc_fpu_xfsr + = ((ic->tme_sparc_fpu_xfsr + & ~ (tme_uint32_t) (0x3 << (2 * (cc - 1)))) + | (fcc << (2 * (cc - 1)))); + return; + } + } ic->tme_sparc_fpu_fsr = (ic->tme_sparc_fpu_fsr & ~TME_SPARC_FSR_FCC) | fcc; } @@ -221,6 +257,7 @@ tme_sparc_fpu_fpop1(struct tme_sparc *ic { tme_uint8_t rounding_mode; unsigned int opf; + unsigned int fpreg_rd_number_encoded; unsigned int fpreg_rd_number; const struct tme_float *fpreg_rs1; const struct tme_float *fpreg_rs2; @@ -240,14 +277,22 @@ tme_sparc_fpu_fpop1(struct tme_sparc *ic ic->tme_sparc_fpu_ieee754_ctl.tme_ieee754_ctl_rounding_mode = rounding_mode; /* decode the rd and opf fields: */ - fpreg_rd_number = TME_FIELD_MASK_EXTRACTU(TME_SPARC_INSN, TME_SPARC_FORMAT3_MASK_RD); + fpreg_rd_number_encoded = TME_FIELD_MASK_EXTRACTU(TME_SPARC_INSN, TME_SPARC_FORMAT3_MASK_RD); opf = TME_FIELD_MASK_EXTRACTU(TME_SPARC_INSN, (0x1ff << 5)); + /* silence uninitialized variable warnings: */ + fpreg_rd_number = 0; + +#ifdef _TME_SPARC_RECODE_VERIFY + /* clear the rd buffer: */ + memset(&fpreg_rd, 0, sizeof(fpreg_rd)); +#endif /* _TME_SPARC_RECODE_VERIFY */ + /* dispatch on the opf field: */ switch (opf) { #define _TME_SPARC_FPU_FORMAT_RS1(format) fpreg_rs1 = tme_sparc_fpu_fpreg_read(ic, TME_SPARC_FORMAT3_MASK_RS1, (format)) #define _TME_SPARC_FPU_FORMAT_RS2(format) fpreg_rs2 = tme_sparc_fpu_fpreg_read(ic, TME_SPARC_FORMAT3_MASK_RS2, (format)) -#define _TME_SPARC_FPU_FORMAT_RD(format) do { fpreg_rd_format = (format) | TME_IEEE754_FPREG_FORMAT_BUILTIN; tme_sparc_fpu_fpreg_aligned(ic, fpreg_rd_number, fpreg_rd_format); } while (/* CONSTCOND */ 0) +#define _TME_SPARC_FPU_FORMAT_RD(format) do { fpreg_rd_format = (format) | TME_IEEE754_FPREG_FORMAT_BUILTIN; fpreg_rd_number = tme_sparc_fpu_fpreg_decode(ic, fpreg_rd_number_encoded, fpreg_rd_format); } while (/* CONSTCOND */ 0) case 1: /* 000000001 FMOVs: */ _TME_SPARC_FPU_FORMAT_RS2(TME_IEEE754_FPREG_FORMAT_SINGLE | TME_IEEE754_FPREG_FORMAT_BUILTIN); @@ -256,6 +301,13 @@ tme_sparc_fpu_fpop1(struct tme_sparc *ic fpreg_rd = *fpreg_rs2; break; + case 2: /* 000000010 FMOVd: */ + _TME_SPARC_FPU_FORMAT_RS2(TME_IEEE754_FPREG_FORMAT_DOUBLE | TME_IEEE754_FPREG_FORMAT_BUILTIN); + _TME_SPARC_FPU_FORMAT_RD(TME_IEEE754_FPREG_FORMAT_DOUBLE); + _TME_SPARC_FPU_BEGIN; + fpreg_rd = *fpreg_rs2; + break; + case 5: /* 000000101 FNEGs: */ _TME_SPARC_FPU_FORMAT_RS2(TME_IEEE754_FPREG_FORMAT_SINGLE); _TME_SPARC_FPU_FORMAT_RD(TME_IEEE754_FPREG_FORMAT_SINGLE); @@ -264,6 +316,14 @@ tme_sparc_fpu_fpop1(struct tme_sparc *ic fpreg_rd.tme_float_value_ieee754_single ^= 0x80000000; break; + case 6: /* 000000110 FNEGd: */ + _TME_SPARC_FPU_FORMAT_RS2(TME_IEEE754_FPREG_FORMAT_DOUBLE); + _TME_SPARC_FPU_FORMAT_RD(TME_IEEE754_FPREG_FORMAT_DOUBLE); + _TME_SPARC_FPU_BEGIN; + fpreg_rd = *fpreg_rs2; + fpreg_rd.tme_float_value_ieee754_double.tme_value64_uint32_hi ^= 0x80000000; + break; + case 9: /* 000001001 FABSs: */ _TME_SPARC_FPU_FORMAT_RS2(TME_IEEE754_FPREG_FORMAT_SINGLE); _TME_SPARC_FPU_FORMAT_RD(TME_IEEE754_FPREG_FORMAT_SINGLE); @@ -272,6 +332,14 @@ tme_sparc_fpu_fpop1(struct tme_sparc *ic fpreg_rd.tme_float_value_ieee754_single &= ~0x80000000; break; + case 10: /* 000001010 FABSd: */ + _TME_SPARC_FPU_FORMAT_RS2(TME_IEEE754_FPREG_FORMAT_DOUBLE); + _TME_SPARC_FPU_FORMAT_RD(TME_IEEE754_FPREG_FORMAT_DOUBLE); + _TME_SPARC_FPU_BEGIN; + fpreg_rd = *fpreg_rs2; + fpreg_rd.tme_float_value_ieee754_double.tme_value64_uint32_hi &= ~0x80000000; + break; + case 41: /* 000101001 FSQRTs: */ _TME_SPARC_FPU_UNIMPL_IF(TME_SPARC_FPU_FLAG_NO_FSQRT); _TME_SPARC_FPU_FORMAT_RS2(TME_IEEE754_FPREG_FORMAT_SINGLE | TME_IEEE754_FPREG_FORMAT_BUILTIN); @@ -405,7 +473,7 @@ tme_sparc_fpu_fpop1(struct tme_sparc *ic fpreg_rs1, &fpreg_rs1_buffer); _TME_SPARC_FPU_OP_MONADIC(tme_ieee754_ops_double_from_single, fpreg_rs2, &fpreg_rs2_buffer); - _TME_SPARC_FPU_OP_DYADIC(tme_ieee754_ops_single_mul, + _TME_SPARC_FPU_OP_DYADIC(tme_ieee754_ops_double_mul, &fpreg_rs1_buffer, &fpreg_rs2_buffer, &fpreg_rd); break; @@ -422,6 +490,104 @@ tme_sparc_fpu_fpop1(struct tme_sparc *ic &fpreg_rs1_buffer, &fpreg_rs2_buffer, &fpreg_rd); break; + case 129: /* 010000001 FsTOx: */ +#ifdef TME_HAVE_INT64_T + if (__tme_predict_true(TME_SPARC_VERSION(ic) >= 9)) { + _TME_SPARC_FPU_FORMAT_RS2(TME_IEEE754_FPREG_FORMAT_SINGLE | TME_IEEE754_FPREG_FORMAT_BUILTIN); + _TME_SPARC_FPU_FORMAT_RD(TME_IEEE754_FPREG_FORMAT_DOUBLE); + _TME_SPARC_FPU_BEGIN; + fpreg_rd.tme_float_format = TME_FLOAT_FORMAT_IEEE754_DOUBLE; + ic->tme_sparc_fpu_ieee754_ctl.tme_ieee754_ctl_rounding_mode = TME_FLOAT_ROUND_TO_ZERO; + _TME_SPARC_FPU_OP_MONADIC(tme_ieee754_ops_single_to_int64, + fpreg_rs2, &fpreg_rd.tme_float_value_ieee754_double.tme_value64_int); + break; + } +#endif /* TME_HAVE_INT64_T */ + _TME_SPARC_FPU_UNIMPL; + fpreg_rd_format = TME_IEEE754_FPREG_FORMAT_NULL; + break; + + case 130: /* 010000010 FdTOx: */ +#ifdef TME_HAVE_INT64_T + if (__tme_predict_true(TME_SPARC_VERSION(ic) >= 9)) { + _TME_SPARC_FPU_FORMAT_RS2(TME_IEEE754_FPREG_FORMAT_DOUBLE | TME_IEEE754_FPREG_FORMAT_BUILTIN); + _TME_SPARC_FPU_FORMAT_RD(TME_IEEE754_FPREG_FORMAT_DOUBLE); + _TME_SPARC_FPU_BEGIN; + fpreg_rd.tme_float_format = TME_FLOAT_FORMAT_IEEE754_DOUBLE; + ic->tme_sparc_fpu_ieee754_ctl.tme_ieee754_ctl_rounding_mode = TME_FLOAT_ROUND_TO_ZERO; + _TME_SPARC_FPU_OP_MONADIC(tme_ieee754_ops_double_to_int64, + fpreg_rs2, &fpreg_rd.tme_float_value_ieee754_double.tme_value64_int); + break; + } +#endif /* TME_HAVE_INT64_T */ + _TME_SPARC_FPU_UNIMPL; + fpreg_rd_format = TME_IEEE754_FPREG_FORMAT_NULL; + break; + + case 131: /* 010000011 FqTOx: */ +#ifdef TME_HAVE_INT64_T + if (__tme_predict_true(TME_SPARC_VERSION(ic) >= 9)) { + _TME_SPARC_FPU_UNIMPL_IF(TME_SPARC_FPU_FLAG_NO_QUAD); + _TME_SPARC_FPU_FORMAT_RS2(TME_IEEE754_FPREG_FORMAT_QUAD | TME_IEEE754_FPREG_FORMAT_BUILTIN); + _TME_SPARC_FPU_FORMAT_RD(TME_IEEE754_FPREG_FORMAT_DOUBLE); + _TME_SPARC_FPU_BEGIN; + fpreg_rd.tme_float_format = TME_FLOAT_FORMAT_IEEE754_DOUBLE; + ic->tme_sparc_fpu_ieee754_ctl.tme_ieee754_ctl_rounding_mode = TME_FLOAT_ROUND_TO_ZERO; + _TME_SPARC_FPU_OP_MONADIC(tme_ieee754_ops_quad_to_int64, + fpreg_rs2, &fpreg_rd.tme_float_value_ieee754_double.tme_value64_int); + break; + } +#endif /* TME_HAVE_INT64_T */ + _TME_SPARC_FPU_UNIMPL; + fpreg_rd_format = TME_IEEE754_FPREG_FORMAT_NULL; + break; + + case 132: /* 010000100 FxTOs: */ +#ifdef TME_HAVE_INT64_T + if (__tme_predict_true(TME_SPARC_VERSION(ic) >= 9)) { + _TME_SPARC_FPU_FORMAT_RS2(TME_IEEE754_FPREG_FORMAT_DOUBLE); + _TME_SPARC_FPU_FORMAT_RD(TME_IEEE754_FPREG_FORMAT_SINGLE); + _TME_SPARC_FPU_BEGIN; + _TME_SPARC_FPU_OP_MONADIC(tme_ieee754_ops_single_from_int64, + fpreg_rs2->tme_float_value_ieee754_double.tme_value64_int, &fpreg_rd); + break; + } +#endif /* TME_HAVE_INT64_T */ + _TME_SPARC_FPU_UNIMPL; + fpreg_rd_format = TME_IEEE754_FPREG_FORMAT_NULL; + break; + + case 136: /* 010001000 FxTOd: */ +#ifdef TME_HAVE_INT64_T + if (__tme_predict_true(TME_SPARC_VERSION(ic) >= 9)) { + _TME_SPARC_FPU_FORMAT_RS2(TME_IEEE754_FPREG_FORMAT_DOUBLE); + _TME_SPARC_FPU_FORMAT_RD(TME_IEEE754_FPREG_FORMAT_DOUBLE); + _TME_SPARC_FPU_BEGIN; + _TME_SPARC_FPU_OP_MONADIC(tme_ieee754_ops_double_from_int64, + fpreg_rs2->tme_float_value_ieee754_double.tme_value64_int, &fpreg_rd); + break; + } +#endif /* TME_HAVE_INT64_T */ + _TME_SPARC_FPU_UNIMPL; + fpreg_rd_format = TME_IEEE754_FPREG_FORMAT_NULL; + break; + + case 140: /* 010001100 FxTOq: */ +#ifdef TME_HAVE_INT64_T + if (__tme_predict_true(TME_SPARC_VERSION(ic) >= 9)) { + _TME_SPARC_FPU_UNIMPL_IF(TME_SPARC_FPU_FLAG_NO_QUAD); + _TME_SPARC_FPU_FORMAT_RS2(TME_IEEE754_FPREG_FORMAT_DOUBLE); + _TME_SPARC_FPU_FORMAT_RD(TME_IEEE754_FPREG_FORMAT_QUAD); + _TME_SPARC_FPU_BEGIN; + _TME_SPARC_FPU_OP_MONADIC(tme_ieee754_ops_quad_from_int64, + fpreg_rs2->tme_float_value_ieee754_double.tme_value64_int, &fpreg_rd); + break; + } +#endif /* TME_HAVE_INT64_T */ + _TME_SPARC_FPU_UNIMPL; + fpreg_rd_format = TME_IEEE754_FPREG_FORMAT_NULL; + break; + case 196: /* 011000100 FiTOs: */ _TME_SPARC_FPU_FORMAT_RS2(TME_IEEE754_FPREG_FORMAT_SINGLE); _TME_SPARC_FPU_FORMAT_RD(TME_IEEE754_FPREG_FORMAT_SINGLE); @@ -523,7 +689,10 @@ tme_sparc_fpu_fpop1(struct tme_sparc *ic fpreg_rs2, (tme_int32_t *) &fpreg_rd.tme_float_value_ieee754_single); break; - default: _TME_SPARC_FPU_UNIMPL; fpreg_rd_format = TME_IEEE754_FPREG_FORMAT_NULL; break; + default: + _TME_SPARC_FPU_UNIMPL; + fpreg_rd_format = TME_IEEE754_FPREG_FORMAT_NULL; + break; #undef _TME_SPARC_FPU_FORMAT_RS1 #undef _TME_SPARC_FPU_FORMAT_RS2 @@ -534,6 +703,7 @@ tme_sparc_fpu_fpop1(struct tme_sparc *ic if (fpreg_rd_format != TME_IEEE754_FPREG_FORMAT_NULL) { tme_sparc_fpu_fpreg_format(ic, fpreg_rd_number, fpreg_rd_format); ic->tme_sparc_fpu_fpregs[fpreg_rd_number] = fpreg_rd; + TME_SPARC_FPU_DIRTY(ic, fpreg_rd_number); } } @@ -543,9 +713,14 @@ tme_sparc_fpu_fpop2(struct tme_sparc *ic { tme_uint8_t rounding_mode; unsigned int opf; + unsigned int fpreg_rd_number_encoded; unsigned int fpreg_rd_number; const struct tme_float *fpreg_rs1; const struct tme_float *fpreg_rs2; + unsigned int cc; + tme_uint32_t conds_mask; + unsigned int cc_i; + tme_uint32_t cond; struct tme_float fpreg_rd; unsigned int fpreg_rd_format; @@ -560,14 +735,93 @@ tme_sparc_fpu_fpop2(struct tme_sparc *ic ic->tme_sparc_fpu_ieee754_ctl.tme_ieee754_ctl_rounding_mode = rounding_mode; /* decode the rd and opf fields: */ - fpreg_rd_number = TME_FIELD_MASK_EXTRACTU(TME_SPARC_INSN, TME_SPARC_FORMAT3_MASK_RD); + fpreg_rd_number_encoded = TME_FIELD_MASK_EXTRACTU(TME_SPARC_INSN, TME_SPARC_FORMAT3_MASK_RD); opf = TME_FIELD_MASK_EXTRACTU(TME_SPARC_INSN, (0x1ff << 5)); + /* silence uninitialized variable warnings: */ + fpreg_rd_number = 0; + +#ifdef _TME_SPARC_RECODE_VERIFY + /* clear the rd buffer: */ + memset(&fpreg_rd, 0, sizeof(fpreg_rd)); +#endif /* _TME_SPARC_RECODE_VERIFY */ + + /* if this is an FMOVcc: */ + if (((opf - 1) & 0x3f) < 3) { + + /* if opf bit eight is set, this uses integer condition codes: */ + if (opf & TME_BIT(8)) { + + /* if opf bit six is set, this is unimplemented: */ + if (__tme_predict_false(opf & TME_BIT(6))) { + _TME_SPARC_FPU_UNIMPL; + } + + /* get %icc or %xcc, depending on opf bit seven: */ + cc = ic->tme_sparc64_ireg_ccr; + if (opf & TME_BIT(7)) { + cc /= (TME_SPARC64_CCR_XCC / TME_SPARC64_CCR_ICC); + } + cc = TME_FIELD_MASK_EXTRACTU(cc, TME_SPARC64_CCR_ICC); + + /* get the conditions mask: */ + conds_mask = _tme_sparc_conds_icc[cc]; + } + + /* otherwise, this uses floating-point condition codes: */ + else { + + /* get the right %fcc: */ + cc_i = TME_FIELD_MASK_EXTRACTU(opf, (0x3 << 6)); + if (cc_i == 0) { + cc = TME_FIELD_MASK_EXTRACTU(ic->tme_sparc_fpu_fsr, TME_SPARC_FSR_FCC); + } + else { + cc = (ic->tme_sparc_fpu_xfsr >> (2 * (cc_i - 1))) & 0x3; + } + + /* get the conditions mask: */ + conds_mask = _tme_sparc_conds_fcc[cc]; + } + + /* add the not-conditions to the conditions mask: */ + conds_mask += ((~conds_mask) << 8); + + /* get the cond field: */ + cond = TME_BIT(TME_FIELD_MASK_EXTRACTU(TME_SPARC_INSN, (0xf << 14))); + + /* if the condition is not true: */ + if (!(conds_mask & cond)) { + + /* return now: */ + /* NB that this may expose us to guests, since we do not check + that the floating-point register numbers are valid: */ + return; + } + + /* clear bits six, seven, and eight in opf: */ + opf &= 0x3f; + } + /* dispatch on the opf field: */ switch (opf) { #define _TME_SPARC_FPU_FORMAT_RS1(format) fpreg_rs1 = tme_sparc_fpu_fpreg_read(ic, TME_SPARC_FORMAT3_MASK_RS1, (format)) #define _TME_SPARC_FPU_FORMAT_RS2(format) fpreg_rs2 = tme_sparc_fpu_fpreg_read(ic, TME_SPARC_FORMAT3_MASK_RS2, (format)) -#define _TME_SPARC_FPU_FORMAT_RD(format) do { fpreg_rd_format = (format) | TME_IEEE754_FPREG_FORMAT_BUILTIN; tme_sparc_fpu_fpreg_aligned(ic, fpreg_rd_number, fpreg_rd_format); } while (/* CONSTCOND */ 0) +#define _TME_SPARC_FPU_FORMAT_RD(format) do { fpreg_rd_format = (format) | TME_IEEE754_FPREG_FORMAT_BUILTIN; fpreg_rd_number = tme_sparc_fpu_fpreg_decode(ic, fpreg_rd_number_encoded, fpreg_rd_format); } while (/* CONSTCOND */ 0) + + case 1: /* 000000001 FMOVscc: */ + _TME_SPARC_FPU_FORMAT_RS2(TME_IEEE754_FPREG_FORMAT_SINGLE | TME_IEEE754_FPREG_FORMAT_BUILTIN); + _TME_SPARC_FPU_FORMAT_RD(TME_IEEE754_FPREG_FORMAT_SINGLE); + _TME_SPARC_FPU_BEGIN; + fpreg_rd = *fpreg_rs2; + break; + + case 2: /* 000000010 FMOVdcc: */ + _TME_SPARC_FPU_FORMAT_RS2(TME_IEEE754_FPREG_FORMAT_DOUBLE | TME_IEEE754_FPREG_FORMAT_BUILTIN); + _TME_SPARC_FPU_FORMAT_RD(TME_IEEE754_FPREG_FORMAT_DOUBLE); + _TME_SPARC_FPU_BEGIN; + fpreg_rd = *fpreg_rs2; + break; case 81: /* 001010001 FCMPs: */ _TME_SPARC_FPU_FORMAT_RS1(TME_IEEE754_FPREG_FORMAT_SINGLE | TME_IEEE754_FPREG_FORMAT_BUILTIN); @@ -625,7 +879,10 @@ tme_sparc_fpu_fpop2(struct tme_sparc *ic fpreg_rd_format = TME_IEEE754_FPREG_FORMAT_NULL; break; - default: _TME_SPARC_FPU_UNIMPL; fpreg_rd_format = TME_IEEE754_FPREG_FORMAT_NULL; break; + default: + _TME_SPARC_FPU_UNIMPL; + fpreg_rd_format = TME_IEEE754_FPREG_FORMAT_NULL; + break; #undef _TME_SPARC_FPU_FORMAT_RS1 #undef _TME_SPARC_FPU_FORMAT_RS2 @@ -636,6 +893,7 @@ tme_sparc_fpu_fpop2(struct tme_sparc *ic if (fpreg_rd_format != TME_IEEE754_FPREG_FORMAT_NULL) { tme_sparc_fpu_fpreg_format(ic, fpreg_rd_number, fpreg_rd_format); ic->tme_sparc_fpu_fpregs[fpreg_rd_number] = fpreg_rd; + TME_SPARC_FPU_DIRTY(ic, fpreg_rd_number); } }