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1.1 ! root 1: /* $Id: sparc-impl.h,v 1.5 2007/03/29 01:13:33 fredette Exp $ */ ! 2: ! 3: /* ic/sparc/sparc-impl.h - implementation header file for SPARC emulation: */ ! 4: ! 5: /* ! 6: * Copyright (c) 2005 Matt Fredette ! 7: * All rights reserved. ! 8: * ! 9: * Redistribution and use in source and binary forms, with or without ! 10: * modification, are permitted provided that the following conditions ! 11: * are met: ! 12: * 1. Redistributions of source code must retain the above copyright ! 13: * notice, this list of conditions and the following disclaimer. ! 14: * 2. Redistributions in binary form must reproduce the above copyright ! 15: * notice, this list of conditions and the following disclaimer in the ! 16: * documentation and/or other materials provided with the distribution. ! 17: * 3. All advertising materials mentioning features or use of this software ! 18: * must display the following acknowledgement: ! 19: * This product includes software developed by Matt Fredette. ! 20: * 4. The name of the author may not be used to endorse or promote products ! 21: * derived from this software without specific prior written permission. ! 22: * ! 23: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ! 24: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ! 25: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ! 26: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, ! 27: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ! 28: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ! 29: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ! 30: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, ! 31: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ! 32: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ! 33: * POSSIBILITY OF SUCH DAMAGE. ! 34: */ ! 35: ! 36: #ifndef _IC_SPARC_IMPL_H ! 37: #define _IC_SPARC_IMPL_H ! 38: ! 39: #include <tme/common.h> ! 40: _TME_RCSID("$Id: sparc-impl.h,v 1.5 2007/03/29 01:13:33 fredette Exp $"); ! 41: ! 42: /* includes: */ ! 43: #include <tme/ic/sparc.h> ! 44: #include <tme/ic/ieee754.h> ! 45: #include <tme/generic/ic.h> ! 46: #include <setjmp.h> ! 47: ! 48: /* macros: */ ! 49: ! 50: /* generic registers: */ ! 51: #define tme_sparc_ireg_uint64(x) tme_sparc_ic.tme_ic_ireg_uint64(x) ! 52: #define tme_sparc_ireg_int64(x) tme_sparc_ic.tme_ic_ireg_int64(x) ! 53: #define tme_sparc_ireg_uint32(x) tme_sparc_ic.tme_ic_ireg_uint32(x) ! 54: #define tme_sparc_ireg_int32(x) tme_sparc_ic.tme_ic_ireg_int32(x) ! 55: #define tme_sparc_ireg_uint8(x) tme_sparc_ic.tme_ic_ireg_uint8(x) ! 56: ! 57: /* format 3 instruction fields: */ ! 58: #define TME_SPARC_FORMAT3_MASK_RS2 (0x1f << 0) ! 59: #define TME_SPARC_FORMAT3_MASK_RS1 (0x1f << 14) ! 60: #define TME_SPARC_FORMAT3_MASK_RD (0x1f << 25) ! 61: ! 62: /* traps: */ ! 63: #define TME_SPARC_TRAP_none (0x00) ! 64: #define TME_SPARC_TRAP_reset (0x100) ! 65: #define TME_SPARC_TRAP_instruction_access_MMU_miss (0x3C) ! 66: #define TME_SPARC_TRAP_instruction_access_error (0x21) ! 67: #define TME_SPARC_TRAP_r_register_access_error (0x20) ! 68: #define TME_SPARC_TRAP_instruction_access_exception (0x01) ! 69: #define TME_SPARC_TRAP_privileged_instruction (0x03) ! 70: #define TME_SPARC_TRAP_illegal_instruction (0x02) ! 71: #define TME_SPARC_TRAP_fp_disabled (0x04) ! 72: #define TME_SPARC_TRAP_cp_disabled (0x24) ! 73: #define TME_SPARC_TRAP_unimplemented_FLUSH (0x25) ! 74: #define TME_SPARC_TRAP_watchpoint_detected (0x0B) ! 75: #define TME_SPARC_TRAP_window_overflow (0x05) ! 76: #define TME_SPARC_TRAP_window_underflow (0x06) ! 77: #define TME_SPARC_TRAP_mem_address_not_aligned (0x07) ! 78: #define TME_SPARC_TRAP_fp_exception (0x08) ! 79: #define TME_SPARC_TRAP_cp_exception (0x28) ! 80: #define TME_SPARC_TRAP_data_access_error (0x29) ! 81: #define TME_SPARC_TRAP_data_access_MMU_miss (0x2C) ! 82: #define TME_SPARC_TRAP_data_access_exception (0x09) ! 83: #define TME_SPARC_TRAP_tag_overflow (0x0A) ! 84: #define TME_SPARC_TRAP_division_by_zero (0x2A) ! 85: #define TME_SPARC_TRAP_trap_instruction(x) (0x80 + (x)) ! 86: #define TME_SPARC_TRAP_interrupt_level(il) (0x10 + (il)) ! 87: ! 88: /* SPARC FPU FSR fields: */ ! 89: #define TME_SPARC_FSR_RND (0xc0000000) ! 90: #define TME_SPARC_FSR_RND_RN (0x00000000) ! 91: #define TME_SPARC_FSR_RND_RZ (0x40000000) ! 92: #define TME_SPARC_FSR_RND_RP (0x80000000) ! 93: #define TME_SPARC_FSR_RND_RM (0xc0000000) ! 94: #define TME_SPARC_FSR_TEM (0x0f800000) ! 95: #define TME_SPARC_FSR_NS TME_BIT(22) ! 96: #define TME_SPARC_FSR_VER (0x000e0000) ! 97: #define TME_SPARC_FSR_VER_missing (0x000e0000) ! 98: #define TME_SPARC_FSR_FTT (0x0001c000) ! 99: #define TME_SPARC_FSR_FTT_none (0x00000000) ! 100: #define TME_SPARC_FSR_FTT_IEEE754_exception (0x00004000) ! 101: #define TME_SPARC_FSR_FTT_unfinished_FPop (0x00008000) ! 102: #define TME_SPARC_FSR_FTT_unimplemented_FPop (0x0000c000) ! 103: #define TME_SPARC_FSR_FTT_sequence_error (0x00010000) ! 104: #define TME_SPARC_FSR_FTT_hardware_error (0x00014000) ! 105: #define TME_SPARC_FSR_FTT_invalid_fp_register (0x00018000) ! 106: #define TME_SPARC_FSR_QNE TME_BIT(13) ! 107: #define TME_SPARC_FSR_FCC (0x00000c00) ! 108: #define TME_SPARC_FSR_FCC_EQ (0x00000000) ! 109: #define TME_SPARC_FSR_FCC_LT (0x00000400) ! 110: #define TME_SPARC_FSR_FCC_GT (0x00000800) ! 111: #define TME_SPARC_FSR_FCC_UN (0x00000c00) ! 112: #define TME_SPARC_FSR_AEXC (0x000003e0) ! 113: #define TME_SPARC_FSR_CEXC (0x0000001f) ! 114: #define TME_SPARC_FSR_CEXC_NVC TME_BIT(4) ! 115: #define TME_SPARC_FSR_CEXC_OFC TME_BIT(3) ! 116: #define TME_SPARC_FSR_CEXC_UFC TME_BIT(2) ! 117: #define TME_SPARC_FSR_CEXC_DZC TME_BIT(1) ! 118: #define TME_SPARC_FSR_CEXC_NXC TME_BIT(0) ! 119: ! 120: /* sparc32 PSR fields: */ ! 121: #define TME_SPARC32_PSR_IMPL (0xf0000000) ! 122: #define TME_SPARC32_PSR_VER (0x0f000000) ! 123: #define TME_SPARC32_PSR_ICC_N TME_BIT(23) ! 124: #define TME_SPARC32_PSR_ICC_Z TME_BIT(22) ! 125: #define TME_SPARC32_PSR_ICC_V TME_BIT(21) ! 126: #define TME_SPARC32_PSR_ICC_C TME_BIT(20) ! 127: #define TME_SPARC32_PSR_ICC (TME_SPARC32_PSR_ICC_N | TME_SPARC32_PSR_ICC_Z | TME_SPARC32_PSR_ICC_V | TME_SPARC32_PSR_ICC_C) ! 128: #define TME_SPARC32_PSR_EC TME_BIT(13) ! 129: #define TME_SPARC32_PSR_EF TME_BIT(12) ! 130: #define TME_SPARC32_PSR_PIL (0x00000f00) ! 131: #define TME_SPARC32_PSR_S TME_BIT(7) ! 132: #define TME_SPARC32_PSR_PS TME_BIT(6) ! 133: #define TME_SPARC32_PSR_ET TME_BIT(5) ! 134: #define TME_SPARC32_PSR_CWP (0x0000001f) ! 135: ! 136: /* sparc64 PSTATE flags: */ ! 137: #define TME_SPARC64_PSTATE_CLE TME_BIT(9) ! 138: #define TME_SPARC64_PSTATE_PRIV TME_BIT(2) ! 139: #define TME_SPARC64_PSTATE_PEF TME_BIT(4) ! 140: ! 141: /* sparc64 CCR flags: */ ! 142: #define TME_SPARC64_CCR_XCC_N TME_BIT(7) ! 143: #define TME_SPARC64_CCR_XCC_Z TME_BIT(6) ! 144: #define TME_SPARC64_CCR_XCC_V TME_BIT(5) ! 145: #define TME_SPARC64_CCR_XCC_C TME_BIT(4) ! 146: #define TME_SPARC64_CCR_ICC_N TME_BIT(3) ! 147: #define TME_SPARC64_CCR_ICC_Z TME_BIT(2) ! 148: #define TME_SPARC64_CCR_ICC_V TME_BIT(1) ! 149: #define TME_SPARC64_CCR_ICC_C TME_BIT(0) ! 150: #define TME_SPARC64_CCR_ICC (TME_SPARC64_CCR_ICC_N | TME_SPARC64_CCR_ICC_Z | TME_SPARC64_CCR_ICC_V | TME_SPARC64_CCR_ICC_C) ! 151: ! 152: /* idle types and idle type state: */ ! 153: #define TME_SPARC_IDLE_TYPE_NULL (0) ! 154: #define TME_SPARC_IDLE_TYPE_NETBSD32_TYPE_0 TME_BIT(0) ! 155: #define TME_SPARC_IDLE_TYPE_SUNOS32_TYPE_0 TME_BIT(1) ! 156: #define TME_SPARC_IDLE_TYPES_SUPPORTED (((unsigned int) 0) - 1) ! 157: #define TME_SPARC_IDLE_TYPE_IS(ic, x) \ ! 158: ((TME_SPARC_IDLE_TYPES_SUPPORTED & (x)) \ ! 159: && (ic)->tme_sparc_idle_type == (x)) ! 160: #define TME_SPARC_IDLE_TYPE_PC_STATE(x) ((x) % sizeof(tme_uint32_t)) ! 161: ! 162: /* major modes of the emulator: */ ! 163: #define TME_SPARC_MODE_EXECUTION (0) ! 164: #define TME_SPARC_MODE_STOP (1) ! 165: #define TME_SPARC_MODE_HALT (2) ! 166: ! 167: /* the maximum number of windows: */ ! 168: #define TME_SPARC_WINDOWS_MAX (16) ! 169: ! 170: /* given a CWP value, this returns the CWP register offset: */ ! 171: #define TME_SPARC_CWP_OFFSET(cwp) ((cwp) * 16) ! 172: ! 173: /* this converts the given lvalue from a register number into a ! 174: register set index: */ ! 175: #define TME_SPARC_REG_INDEX(ic, reg) \ ! 176: do { \ ! 177: if ((reg) > 7) { \ ! 178: (reg) += ic->tme_sparc_cwp_offset; \ ! 179: } \ ! 180: if ((reg) \ ! 181: > (TME_SPARC_CWP_OFFSET(TME_SPARC_NWINDOWS(ic)) + 7)) { \ ! 182: (reg) -= TME_SPARC_CWP_OFFSET(TME_SPARC_NWINDOWS(ic)); \ ! 183: } \ ! 184: } while (/* CONSTCOND */ 0) ! 185: ! 186: /* given a linear address, this hashes it into a DTLB entry: */ ! 187: #define _TME_SPARC_DTLB_HASH_SIZE (1024) ! 188: #define TME_SPARC_DTLB_ENTRY(ic, address) \ ! 189: (tme_memory_atomic_pointer_read(struct tme_sparc_tlb *, \ ! 190: (ic)->_tme_sparc_dtlb_array, \ ! 191: &(ic)->_tme_sparc_tlb_rwlock) \ ! 192: + ((address >> 10) & (_TME_SPARC_DTLB_HASH_SIZE - 1))) ! 193: ! 194: /* the size of the ITLB hash: */ ! 195: #define _TME_SPARC_ITLB_HASH_SIZE (32) ! 196: ! 197: /* flags for the slow load and store functions: */ ! 198: #define TME_SPARC_SLOW_FLAG_A TME_BIT(5) ! 199: #define TME_SPARC_SLOW_FLAG_ATOMIC TME_BIT(6) ! 200: #define TME_SPARC_SLOW_FLAG_INSN TME_BIT(7) ! 201: #define TME_SPARC_SLOW_FLAG_NO_FAULTS TME_BIT(8) ! 202: ! 203: /* flags for FPU features: */ ! 204: #define TME_SPARC_FPU_FLAG_NO_QUAD TME_BIT(0) ! 205: #define TME_SPARC_FPU_FLAG_NO_FSQRT TME_BIT(1) ! 206: #define TME_SPARC_FPU_FLAG_NO_FMUL_WIDER TME_BIT(2) ! 207: #define TME_SPARC_FPU_FLAG_OK_REG_MISALIGNED TME_BIT(3) ! 208: ! 209: /* FPU modes: */ ! 210: #define TME_SPARC_FPU_MODE_EXECUTE (0) ! 211: #define TME_SPARC_FPU_MODE_EXCEPTION_PENDING (1) ! 212: #define TME_SPARC_FPU_MODE_EXCEPTION (2) ! 213: ! 214: /* instruction handler macros: */ ! 215: #define TME_SPARC_FORMAT3_DECL(name, type) void name _TME_P((struct tme_sparc *, const type *, const type *, type *)) ! 216: #ifdef __STDC__ ! 217: #define TME_SPARC_FORMAT3(name, type) void name(struct tme_sparc *ic, const type *_rs1, const type *_rs2, type *_rd) ! 218: #else /* !__STDC__ */ ! 219: #define TME_SPARC_FORMAT3(name, type) void name(ic, _rs1, _rs2, _rd) struct tme_sparc *ic; const type *_rs1, *_rs2; type *_rd; ! 220: #endif /* !__STDC__ */ ! 221: #define TME_SPARC_FORMAT3_RS1 (*_rs1) ! 222: #define TME_SPARC_FORMAT3_RS2 (*_rs2) ! 223: #define TME_SPARC_FORMAT3_RD (*_rd) ! 224: #define TME_SPARC_FORMAT3_RD_ODD (*(_rd + (&(((struct tme_ic *) NULL)->tme_ic_ireg_uint32(1)) - &(((struct tme_ic *) NULL)->tme_ic_ireg_uint32(0))))) ! 225: #define TME_SPARC_INSN ic->_tme_sparc_insn ! 226: #define TME_SPARC_INSN_OK return ! 227: #define TME_SPARC_INSN_TRAP(trap) \ ! 228: do { \ ! 229: if (TME_SPARC_VERSION(ic) < 9) { \ ! 230: tme_sparc32_trap(ic, trap); \ ! 231: } \ ! 232: else { \ ! 233: tme_sparc64_trap(ic, trap); \ ! 234: } \ ! 235: } while (/* CONSTCOND */ 0) ! 236: #define TME_SPARC_INSN_PRIV \ ! 237: do { \ ! 238: if (__tme_predict_false(!TME_SPARC_PRIV(ic))) { \ ! 239: TME_SPARC_INSN_TRAP(TME_SPARC_TRAP_privileged_instruction);\ ! 240: } \ ! 241: } while (/* CONSTCOND */ 0) ! 242: #define TME_SPARC_INSN_FPU \ ! 243: do { \ ! 244: if (__tme_predict_false((TME_SPARC_VERSION(ic) < 9) \ ! 245: ? ((ic)->tme_sparc32_ireg_psr & TME_SPARC32_PSR_EF) == 0 \ ! 246: : ((ic)->tme_sparc64_ireg_pstate & TME_SPARC64_PSTATE_PEF) == 0)) { \ ! 247: TME_SPARC_INSN_TRAP(TME_SPARC_TRAP_fp_disabled); \ ! 248: } \ ! 249: if (__tme_predict_false((ic)->tme_sparc_fpu_mode \ ! 250: != TME_SPARC_FPU_MODE_EXECUTE)) { \ ! 251: tme_sparc_fpu_exception_check(ic); \ ! 252: } \ ! 253: } while (/* CONSTCOND */ 0) ! 254: #define TME_SPARC_INSN_FPU_STORE(size) \ ! 255: do { \ ! 256: if (__tme_predict_false((TME_SPARC_VERSION(ic) < 9) \ ! 257: ? ((ic)->tme_sparc32_ireg_psr & TME_SPARC32_PSR_EF) == 0 \ ! 258: : ((ic)->tme_sparc64_ireg_pstate & TME_SPARC64_PSTATE_PEF) == 0)) { \ ! 259: TME_SPARC_INSN_TRAP(TME_SPARC_TRAP_fp_disabled); \ ! 260: } \ ! 261: if (__tme_predict_false(((TME_SPARC_FORMAT3_RS1 \ ! 262: + TME_SPARC_FORMAT3_RS2) \ ! 263: % (size)) != 0)) { \ ! 264: TME_SPARC_INSN_TRAP(TME_SPARC_TRAP_mem_address_not_aligned); \ ! 265: } \ ! 266: if (__tme_predict_false((ic)->tme_sparc_fpu_mode \ ! 267: == TME_SPARC_FPU_MODE_EXCEPTION_PENDING)) { \ ! 268: tme_sparc_fpu_exception_check(ic); \ ! 269: } \ ! 270: } while (/* CONSTCOND */ 0) ! 271: ! 272: #define TME_SPARC_INSN_ILL \ ! 273: TME_SPARC_INSN_TRAP(TME_SPARC_TRAP_illegal_instruction) ! 274: ! 275: /* logging: */ ! 276: #define TME_SPARC_LOG_HANDLE(ic) \ ! 277: (&(ic)->tme_sparc_element->tme_element_log_handle) ! 278: #define tme_sparc_log_start(ic, level, rc) \ ! 279: do { \ ! 280: tme_log_start(TME_SPARC_LOG_HANDLE(ic), level, rc) { \ ! 281: if ((ic)->_tme_sparc_mode != TME_SPARC_MODE_EXECUTION) { \ ! 282: tme_log_part(TME_SPARC_LOG_HANDLE(ic), \ ! 283: "mode=%d ", \ ! 284: (ic)->_tme_sparc_mode); \ ! 285: } \ ! 286: else { \ ! 287: tme_log_part(TME_SPARC_LOG_HANDLE(ic), \ ! 288: "pc=%c/0x%08x ", \ ! 289: (TME_SPARC_PRIV(ic) \ ! 290: ? 'S' \ ! 291: : 'U'), \ ! 292: ((TME_SPARC_VERSION(ic) < 9) \ ! 293: ? ic->tme_sparc_ireg_uint32(TME_SPARC_IREG_PC)\ ! 294: : (tme_uint32_t) ic->tme_sparc_ireg_uint64(TME_SPARC_IREG_PC)));\ ! 295: } \ ! 296: do ! 297: #define tme_sparc_log_finish(ic) \ ! 298: while (/* CONSTCOND */ 0); \ ! 299: } tme_log_finish(TME_SPARC_LOG_HANDLE(ic)); \ ! 300: } while (/* CONSTCOND */ 0) ! 301: #define tme_sparc_log(ic, level, rc, x) \ ! 302: do { \ ! 303: tme_sparc_log_start(ic, level, rc) { \ ! 304: tme_log_part x; \ ! 305: } tme_sparc_log_finish(ic); \ ! 306: } while (/* CONSTCOND */ 0) ! 307: ! 308: /* miscellaneous: */ ! 309: #define _TME_SPARC_VERSION(ic) ((ic)->tme_sparc_version) ! 310: #define _TME_SPARC_NWINDOWS(ic) ((ic)->tme_sparc_nwindows) ! 311: #define _TME_SPARC32_PRIV(ic) (((ic)->tme_sparc32_ireg_psr & TME_SPARC32_PSR_S) != 0) ! 312: #define _TME_SPARC64_PRIV(ic) (((ic)->tme_sparc64_ireg_pstate & TME_SPARC64_PSTATE_PRIV) != 0) ! 313: #define TME_SPARC_VERSION(ic) _TME_SPARC_VERSION(ic) ! 314: #define TME_SPARC_NWINDOWS(ic) _TME_SPARC_NWINDOWS(ic) ! 315: #define TME_SPARC_PRIV(ic) \ ! 316: ((TME_SPARC_VERSION(ic) < 9) \ ! 317: ? _TME_SPARC32_PRIV(ic) \ ! 318: : _TME_SPARC64_PRIV(ic)) ! 319: #define TME_SPARC_ASI_DATA(ic) \ ! 320: ((TME_SPARC_VERSION(ic) < 9) \ ! 321: ? (_TME_SPARC32_PRIV(ic) \ ! 322: ? TME_SPARC32_ASI_SD \ ! 323: : TME_SPARC32_ASI_UD) \ ! 324: : ((ic->tme_sparc64_ireg_pstate & TME_SPARC64_PSTATE_CLE)\ ! 325: ? TME_SPARC64_ASI_PRIMARY_LITTLE \ ! 326: : TME_SPARC64_ASI_PRIMARY)) ! 327: ! 328: /* structures: */ ! 329: struct tme_sparc; ! 330: ! 331: /* format 3 instruction functions: */ ! 332: typedef TME_SPARC_FORMAT3_DECL((*_tme_sparc32_format3), tme_uint32_t); ! 333: ! 334: /* a sparc deferred-trap queue: */ ! 335: struct tme_sparc_trapqueue { ! 336: #ifdef TME_HAVE_INT64_T ! 337: tme_uint64_t tme_sparc_trapqueue_address; ! 338: #else /* !TME_HAVE_INT64_T */ ! 339: tme_uint32_t tme_sparc_trapqueue_address; ! 340: #endif /* !TME_HAVE_INT64_T */ ! 341: tme_uint32_t tme_sparc_trapqueue_insn; ! 342: }; ! 343: ! 344: /* the sparc state: */ ! 345: struct tme_sparc { ! 346: ! 347: /* the IC data structure. it is beneficial to have this structure ! 348: first, since register numbers can often simply be scaled and ! 349: added without an offset to the struct tme_sparc pointer to get ! 350: to their contents: */ ! 351: struct tme_ic tme_sparc_ic; ! 352: ! 353: /* the current window pointer register offset: */ ! 354: unsigned int tme_sparc_cwp_offset; ! 355: ! 356: /* the architecture version, and number of windows: */ ! 357: unsigned int tme_sparc_version; ! 358: unsigned int tme_sparc_nwindows; ! 359: ! 360: /* the backpointer to our element: */ ! 361: struct tme_element *tme_sparc_element; ! 362: ! 363: /* our bus connection. if both are defined, the sparc bus connection ! 364: is an adaptation layer for the generic bus connection: */ ! 365: struct tme_sparc_bus_connection *_tme_sparc_bus_connection; ! 366: struct tme_bus_connection *_tme_sparc_bus_generic; ! 367: ! 368: /* a jmp_buf back to the dispatcher: */ ! 369: jmp_buf _tme_sparc_dispatcher; ! 370: ! 371: /* the current mode of the CPU: */ ! 372: int _tme_sparc_mode; ! 373: ! 374: /* address space identifiers and masks: */ ! 375: tme_uint32_t tme_sparc_asi_mask_insn; ! 376: tme_uint32_t tme_sparc_asi_mask_data; ! 377: ! 378: /* the implementation-dependent functions: */ ! 379: void (*_tme_sparc_execute) _TME_P((struct tme_sparc *)); ! 380: tme_uint32_t (*_tme_sparc_bus_fault) _TME_P((struct tme_sparc *, const struct tme_bus_cycle *, unsigned int, int)); ! 381: tme_uint32_t (*_tme_sparc_fetch_slow) _TME_P((struct tme_sparc *, int)); ! 382: tme_uint32_t (*_tme_sparc_fpu_ver) _TME_P((struct tme_sparc *, const char *, char **)); ! 383: ! 384: /* the instruction burst count, and the remaining burst: */ ! 385: unsigned int _tme_sparc_instruction_burst; ! 386: unsigned int _tme_sparc_instruction_burst_remaining; ! 387: ! 388: /* any currently busy instruction TLB entry: */ ! 389: struct tme_sparc_tlb *_tme_sparc_itlb_busy; ! 390: ! 391: /* instruction information: */ ! 392: tme_uint32_t _tme_sparc_insn; ! 393: ! 394: /* the data and instruction TLB entry sets: */ ! 395: union { ! 396: struct tme_sparc_tlb * tme_shared _tme_sparc_dtlb_array_u_sparc; ! 397: struct tme_bus_tlb * tme_shared _tme_sparc_dtlb_array_u_bus; ! 398: } _tme_sparc_dtlb_array_u; ! 399: #define _tme_sparc_dtlb_array _tme_sparc_dtlb_array_u._tme_sparc_dtlb_array_u_sparc ! 400: #define _tme_sparc_dtlb_array_bus _tme_sparc_dtlb_array_u._tme_sparc_dtlb_array_u_bus ! 401: union { ! 402: struct tme_sparc_tlb * tme_shared _tme_sparc_itlb_array_u_sparc; ! 403: struct tme_bus_tlb * tme_shared _tme_sparc_itlb_array_u_bus; ! 404: } _tme_sparc_itlb_array_u; ! 405: #define _tme_sparc_itlb_array _tme_sparc_itlb_array_u._tme_sparc_itlb_array_u_sparc ! 406: #define _tme_sparc_itlb_array_bus _tme_sparc_itlb_array_u._tme_sparc_itlb_array_u_bus ! 407: tme_rwlock_t _tme_sparc_tlb_rwlock; ! 408: ! 409: /* the external request lines: */ ! 410: tme_mutex_t tme_sparc_external_mutex; ! 411: tme_cond_t tme_sparc_external_cond; ! 412: unsigned int tme_sparc_external_reset; ! 413: unsigned int tme_sparc_external_halt; ! 414: unsigned int tme_sparc_external_ipl; ! 415: ! 416: /* the slow load/store buffer: */ ! 417: tme_uint8_t tme_sparc_memory_buffer[sizeof(tme_uint32_t) * 2]; ! 418: ! 419: /* any FPU state: */ ! 420: struct tme_ieee754_ctl tme_sparc_fpu_ieee754_ctl; ! 421: _tme_const struct tme_ieee754_ops *tme_sparc_fpu_ieee754_ops; ! 422: _tme_const struct tme_ieee754_ops *tme_sparc_fpu_ieee754_ops_user; ! 423: _tme_const struct tme_ieee754_ops *tme_sparc_fpu_ieee754_ops_strict; ! 424: struct tme_float tme_sparc_fpu_fpregs[32]; ! 425: unsigned int tme_sparc_fpu_fpreg_sizes[32]; ! 426: tme_uint32_t tme_sparc_fpu_fsr; ! 427: struct tme_sparc_trapqueue tme_sparc_fpu_fq[1]; ! 428: unsigned int tme_sparc_fpu_mode; ! 429: unsigned int tme_sparc_fpu_flags; ! 430: int tme_sparc_fpu_incomplete_abort; ! 431: ! 432: /* any idle type, and idle type state: */ ! 433: unsigned int tme_sparc_idle_type; ! 434: tme_uint32_t tme_sparc_idle_type_pc32; ! 435: tme_uint32_t tme_sparc_idle_type_pc64; ! 436: ! 437: #ifdef _TME_SPARC_STATS ! 438: /* statistics: */ ! 439: struct { ! 440: ! 441: /* the total number of instructions executed: */ ! 442: tme_uint64_t tme_sparc_stats_insns_total; ! 443: ! 444: /* the total number of instructions fetched slowly: */ ! 445: tme_uint64_t tme_sparc_stats_fetch_slow; ! 446: ! 447: /* the total number of redispatches: */ ! 448: tme_uint64_t tme_sparc_stats_redispatches; ! 449: ! 450: /* the total number of data memory operations: */ ! 451: tme_uint64_t tme_sparc_stats_memory_total; ! 452: ! 453: /* the total number of ITLB fills: */ ! 454: tme_uint64_t tme_sparc_stats_itlb_fill; ! 455: ! 456: /* the total number of DTLB fills: */ ! 457: tme_uint64_t tme_sparc_stats_dtlb_fill; ! 458: ! 459: } tme_sparc_stats; ! 460: #endif /* _TME_SPARC_STATS */ ! 461: }; ! 462: ! 463: /* globals: */ ! 464: extern const tme_uint8_t _tme_sparc_conds_icc[16]; ! 465: extern const tme_uint8_t _tme_sparc_conds_fcc[4]; ! 466: ! 467: /* prototypes: */ ! 468: int tme_sparc_new _TME_P((struct tme_sparc *, const char * const *, const void *, char **)); ! 469: void tme_sparc_redispatch _TME_P((struct tme_sparc *)); ! 470: void tme_sparc_do_reset _TME_P((struct tme_sparc *)); ! 471: void tme_sparc_do_idle _TME_P((struct tme_sparc *)); ! 472: void tme_sparc32_external_check _TME_P((struct tme_sparc *)); ! 473: tme_uint32_t tme_sparc32_fetch_slow _TME_P((struct tme_sparc *, int)); ! 474: tme_uint32_t tme_sparc_fetch_nearby _TME_P((struct tme_sparc *, long)); ! 475: void tme_sparc_callout_unlock _TME_P((struct tme_sparc *)); ! 476: void tme_sparc_callout_relock _TME_P((struct tme_sparc *)); ! 477: ! 478: /* trap support: */ ! 479: void tme_sparc32_trap_preinstruction _TME_P((struct tme_sparc *, unsigned int)); ! 480: void tme_sparc32_trap _TME_P((struct tme_sparc *, tme_uint32_t)); ! 481: tme_uint32_t tme_sparc32_bus_fault _TME_P((struct tme_sparc *, const struct tme_bus_cycle *, unsigned int, int)); ! 482: void tme_sparc64_trap _TME_P((struct tme_sparc *, tme_uint32_t)); ! 483: ! 484: /* FPU support: */ ! 485: int tme_sparc_fpu_new _TME_P((struct tme_sparc *, const char * const *, int *, int *, char **)); ! 486: void tme_sparc_fpu_reset _TME_P((struct tme_sparc *)); ! 487: void tme_sparc_fpu_usage _TME_P((struct tme_sparc *, char **)); ! 488: void tme_sparc_fpu_strict _TME_P((struct tme_sparc_bus_connection *, unsigned int)); ! 489: void tme_sparc_fpu_exception_check _TME_P((struct tme_sparc *)); ! 490: int tme_sparc_fpu_fpreg_aligned _TME_P((struct tme_sparc *, unsigned int, unsigned int)); ! 491: void tme_sparc_fpu_fpreg_format _TME_P((struct tme_sparc *, unsigned int, unsigned int)); ! 492: void tme_sparc_fpu_fpop1 _TME_P((struct tme_sparc *)); ! 493: void tme_sparc_fpu_fpop2 _TME_P((struct tme_sparc *)); ! 494: ! 495: /* verification: */ ! 496: void tme_sparc_verify_hook _TME_P((void)); ! 497: #ifdef _TME_SPARC_VERIFY ! 498: void tme_sparc_verify_init _TME_P((void)); ! 499: void tme_sparc_verify_begin _TME_P((const struct tme_sparc *, const tme_uint8_t *)); ! 500: void tme_sparc_verify_mem_any _TME_P((const struct tme_sparc *, ! 501: unsigned int, tme_uint32_t, ! 502: tme_uint8_t *, int, int)); ! 503: void tme_sparc_verify_end_branch _TME_P((const struct tme_sparc *, tme_uint32_t)); ! 504: void tme_sparc_verify_end _TME_P((const struct tme_sparc *, ! 505: void (*)(struct tme_sparc *, void *, void *))); ! 506: #else /* _TME_SPARC_VERIFY */ ! 507: #define tme_sparc_verify_init() do { } while (/* CONSTCOND */ 0) ! 508: #define tme_sparc_verify_begin(ic, s) do { } while (/* CONSTCOND */ 0) ! 509: #define tme_sparc_verify_mem_any(ic, fc, a, v, c, rw) do { } while (/* CONSTCOND */ 0) ! 510: #define tme_sparc_verify_end_branch(ic, pc) do { } while (/* CONSTCOND */ 0) ! 511: #define tme_sparc_verify_end(ic, f) do { } while (/* CONSTCOND */ 0) ! 512: #define tme_sparc_verify_hook() do { } while (/* CONSTCOND */ 0) ! 513: #endif /* _TME_SPARC_VERIFY */ ! 514: #define tme_sparc_verify_mem8(ic, fc, a, v, rw) tme_sparc_verify_mem_any(ic, fc, a, (tme_uint8_t *) &(v), -sizeof(tme_uint8_t), rw) ! 515: #define tme_sparc_verify_mem16(ic, fc, a, v, rw) tme_sparc_verify_mem_any(ic, fc, a, (tme_uint8_t *) &(v), -sizeof(tme_uint16_t), rw) ! 516: #define tme_sparc_verify_mem32(ic, fc, a, v, rw) tme_sparc_verify_mem_any(ic, fc, a, (tme_uint8_t *) &(v), -sizeof(tme_uint32_t), rw) ! 517: ! 518: /* instruction functions: */ ! 519: TME_SPARC_FORMAT3_DECL(tme_sparc32_illegal, tme_uint32_t); ! 520: TME_SPARC_FORMAT3_DECL(tme_sparc32_cpop1, tme_uint32_t); ! 521: TME_SPARC_FORMAT3_DECL(tme_sparc32_cpop2, tme_uint32_t); ! 522: TME_SPARC_FORMAT3_DECL(tme_sparc32_ldc, tme_uint32_t); ! 523: TME_SPARC_FORMAT3_DECL(tme_sparc32_ldcsr, tme_uint32_t); ! 524: TME_SPARC_FORMAT3_DECL(tme_sparc32_lddc, tme_uint32_t); ! 525: TME_SPARC_FORMAT3_DECL(tme_sparc32_stc, tme_uint32_t); ! 526: TME_SPARC_FORMAT3_DECL(tme_sparc32_stcsr, tme_uint32_t); ! 527: TME_SPARC_FORMAT3_DECL(tme_sparc32_stdc, tme_uint32_t); ! 528: TME_SPARC_FORMAT3_DECL(tme_sparc32_stdcq, tme_uint32_t); ! 529: TME_SPARC_FORMAT3_DECL(tme_sparc32_rdasr, tme_uint32_t); ! 530: TME_SPARC_FORMAT3_DECL(tme_sparc32_rdpsr, tme_uint32_t); ! 531: TME_SPARC_FORMAT3_DECL(tme_sparc32_rdwim, tme_uint32_t); ! 532: TME_SPARC_FORMAT3_DECL(tme_sparc32_rdtbr, tme_uint32_t); ! 533: TME_SPARC_FORMAT3_DECL(tme_sparc32_wrasr, tme_uint32_t); ! 534: TME_SPARC_FORMAT3_DECL(tme_sparc32_wrpsr, tme_uint32_t); ! 535: TME_SPARC_FORMAT3_DECL(tme_sparc32_wrwim, tme_uint32_t); ! 536: TME_SPARC_FORMAT3_DECL(tme_sparc32_wrtbr, tme_uint32_t); ! 537: TME_SPARC_FORMAT3_DECL(tme_sparc32_flush, tme_uint32_t); ! 538: TME_SPARC_FORMAT3_DECL(tme_sparc32_rett, tme_uint32_t); ! 539: TME_SPARC_FORMAT3_DECL(tme_sparc32_save_restore, tme_uint32_t); ! 540: TME_SPARC_FORMAT3_DECL(tme_sparc32_ticc, tme_uint32_t); ! 541: TME_SPARC_FORMAT3_DECL(tme_sparc32_stdfq, tme_uint32_t); ! 542: TME_SPARC_FORMAT3_DECL(tme_sparc32_fpop1, tme_uint32_t); ! 543: TME_SPARC_FORMAT3_DECL(tme_sparc32_fpop2, tme_uint32_t); ! 544: ! 545: /* the automatically-generated header information: */ ! 546: #include <sparc-auto.h> ! 547: ! 548: #endif /* !_IC_SPARC_IMPL_H */
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