--- tme/ic/sparc/sparc-misc-auto.sh	2018/04/24 16:42:00	1.1
+++ tme/ic/sparc/sparc-misc-auto.sh	2018/04/24 16:43:56	1.1.1.2
@@ -1,6 +1,6 @@
 #! /bin/sh
 
-# $Id: sparc-misc-auto.sh,v 1.1 2018/04/24 16:42:00 root Exp $
+# $Id: sparc-misc-auto.sh,v 1.1.1.2 2018/04/24 16:43:56 root Exp $
 
 # ic/sparc/sparc-misc-auto.sh - automatically generates C code 
 # for miscellaneous SPARC emulation support:
@@ -66,10 +66,16 @@ if $header; then
     done
 
     # all other registers start after the last register in the last
-    # possible register window, plus the eight sparc64 alternate
-    # globals:
+    # possible register window:
     #
-    ireg_base='((TME_SPARC_WINDOWS_MAX * 16) + 8)'
+    ireg_base='(TME_SPARC_WINDOWS_MAX * 16)'
+
+    # the sparc64 alternate, MMU, and interrupt globals:
+    #
+    echo "#define TME_SPARC64_IREG_AG_G0	(${ireg_base} + ${ireg_next} + (8 * 0))"
+    echo "#define TME_SPARC64_IREG_MG_G0	(${ireg_base} + ${ireg_next} + (8 * 1))"
+    echo "#define TME_SPARC64_IREG_IG_G0	(${ireg_base} + ${ireg_next} + (8 * 2))"
+    ireg_next=`expr ${ireg_next} + 24`
 
     # the current, next, and next-next program counter:
     #
@@ -80,9 +86,14 @@ if $header; then
     echo "#define TME_SPARC_IREG_PC_NEXT_NEXT		(${ireg_base} + ${ireg_next})"
     ireg_next=`expr ${ireg_next} + 1`
 
-    # the immediate register:
+    # the instruction register:
+    #
+    echo "#define TME_SPARC_IREG_INSN		(${ireg_base} + ${ireg_next})"
+    ireg_next=`expr ${ireg_next} + 1`
+
+    # some temporary registers:
     #
-    echo "#define TME_SPARC_IREG_IMM		(${ireg_base} + ${ireg_next})"
+    echo "#define TME_SPARC_IREG_TMP(x)		(${ireg_base} + ${ireg_next} + (x))"
     ireg_next=`expr ${ireg_next} + 3`
 
     # the Y multiply/divide register:
@@ -99,11 +110,26 @@ if $header; then
     echo "#define TME_SPARC_IREG_FPX		(${ireg_base} + ${ireg_next})"
     ireg_next=`expr ${ireg_next} + 4`
     
-    # the sparc32 PSR and WIM:
+    # the sparc32 PSR, and the sparc64 PSTATE:
     #
-    echo "#define tme_sparc32_ireg_psr		tme_sparc_ireg_uint32(${ireg_base} + ${ireg_next})"
+    echo "#define TME_SPARC32_IREG_PSR		(${ireg_base} + ${ireg_next})"
+    echo "#define tme_sparc32_ireg_psr		tme_sparc_ireg_uint32(TME_SPARC32_IREG_PSR)"
+    echo "#define tme_sparc64_ireg_pstate	tme_sparc_ireg_uint32((${ireg_base} + ${ireg_next}) << 1)"
     ireg_next=`expr ${ireg_next} + 1`
+
+    # the sparc32 WIM, and the common sparc64 register-window state registers:
+    #
     echo "#define tme_sparc32_ireg_wim		tme_sparc_ireg_uint32(${ireg_base} + ${ireg_next})"
+    echo "#define tme_sparc64_ireg_winstates	tme_sparc_ireg_uint32(((${ireg_base} + ${ireg_next}) << 1) + 0)"
+    echo "#define TME_SPARC64_WINSTATES_CWP(x)		(((x) & 0x3f) << (8 * 0))"
+    echo "#define tme_sparc64_ireg_cwp		tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 0)"
+    echo "#define TME_SPARC64_WINSTATES_CANRESTORE(x)	(((x) & 0x3f) << (8 * 1))"
+    echo "#define tme_sparc64_ireg_canrestore	tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 1)"
+    echo "#define TME_SPARC64_WINSTATES_CANSAVE(x)	(((x) & 0x3f) << (8 * 2))"
+    echo "#define tme_sparc64_ireg_cansave	tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 2)"
+    echo "#define TME_SPARC64_WINSTATES_OTHERWIN(x)	(((x) & 0x3f) << (8 * 3))"
+    echo "#define tme_sparc64_ireg_otherwin	tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 3)"
+    echo "#define tme_sparc64_ireg_winstates_mask tme_sparc_ireg_uint32(((${ireg_base} + ${ireg_next}) << 1) + 1)"
     ireg_next=`expr ${ireg_next} + 1`
 
     # the sparc32 TBR register, and the sparc64 TBA register:
@@ -112,15 +138,56 @@ if $header; then
     echo "#define tme_sparc64_ireg_tba		tme_sparc_ireg_uint64(${ireg_base} + ${ireg_next})"
     ireg_next=`expr ${ireg_next} + 1`
 
-    # the sparc64 PSTATE register:
+    # the sparc64 trap PC, NPC, state, and type registers:
+    #
+    echo "#define tme_sparc64_ireg_tpc(tl)	tme_sparc_ireg_uint64(${ireg_base} + (TME_SPARC_TL_MAX * 0) + ${ireg_next} + ((tl) - 1))"
+    echo "#define tme_sparc64_ireg_tnpc(tl)	tme_sparc_ireg_uint64(${ireg_base} + (TME_SPARC_TL_MAX * 1) + ${ireg_next} + ((tl) - 1))"
+    echo "#define TME_SPARC64_IREG_TSTATE(tl)	(${ireg_base} + (TME_SPARC_TL_MAX * 2) + ${ireg_next} + ((tl) - 1))"
+    echo "#define tme_sparc64_ireg_tstate(tl)	tme_sparc_ireg_uint64(TME_SPARC64_IREG_TSTATE(tl))"
+    echo "#define tme_sparc64_ireg_tstate_ccr(tl) tme_sparc_ireg_uint8((TME_SPARC64_IREG_TSTATE(tl) << 3) + sizeof(tme_uint32_t))"
+    echo "#if TME_SPARC_TL_MAX > 8"
+    echo "#error \"TME_SPARC_TL_MAX changed\""
+    echo "#endif"
+    echo "#define tme_sparc64_ireg_tt(tl)	tme_sparc_ireg_uint8(((${ireg_base} + (TME_SPARC_TL_MAX * 3) + ${ireg_next}) << 3) + ((tl) - 1))"
+    ireg_base="(${ireg_base} + (TME_SPARC_TL_MAX * 3) + 1)"
+
+    # the sparc64 TL, PIL, ASI, FPRS, remaining register-window state registers, and TICK.NPT:
+    #
+    echo "#define tme_sparc64_ireg_tl		tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 0)"
+    echo "#define tme_sparc64_ireg_pil		tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 1)"
+    echo "#define tme_sparc64_ireg_asi		tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 2)"
+    echo "#define tme_sparc64_ireg_fprs		tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 3)"
+    echo "#define tme_sparc64_ireg_wstate	tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 4)"
+    echo "#define tme_sparc64_ireg_cleanwin	tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 5)"
+    echo "#define tme_sparc64_ireg_tick_npt	tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 6)"
+    ireg_next=`expr ${ireg_next} + 1`
+
+    # the sparc64 TICK (offset) register:
+    #
+    echo "#define tme_sparc64_ireg_tick_offset	tme_sparc_ireg_uint64(${ireg_base} + ${ireg_next})"
+    ireg_next=`expr ${ireg_next} + 1`
+
+    # the sparc64 version register:
+    #
+    echo "#define tme_sparc64_ireg_ver		tme_sparc_ireg_uint64(${ireg_base} + ${ireg_next})"
+    ireg_next=`expr ${ireg_next} + 1`
+
+    # the sparc64 CCR:
+    # NB: this is a separate register for recode; can it maybe be combined
+    # with the block of 8-bit registers above, as the first byte?
+    #
+    echo "#define TME_SPARC64_IREG_CCR		(${ireg_base} + ${ireg_next})"
+    echo "#define tme_sparc64_ireg_ccr		tme_sparc_ireg_uint8(TME_SPARC64_IREG_CCR << 3)"
+    ireg_next=`expr ${ireg_next} + 1`
+
+    # our internal sparc64 RCC register:
     #
-    echo "#define tme_sparc64_ireg_pstate		tme_sparc_ireg_uint32((${ireg_base} + ${ireg_next}) << 1)"
+    echo "#define TME_SPARC64_IREG_RCC		(${ireg_base} + ${ireg_next})"
     ireg_next=`expr ${ireg_next} + 1`
 
-    # the sparc64 CCR and ASI registers:
+    # our internal virtual address hole start:
     #
-    echo "#define tme_sparc64_ireg_ccr		tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 0)"
-    echo "#define tme_sparc64_ireg_asi		tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 1)"
+    echo "#define tme_sparc64_ireg_va_hole_start tme_sparc_ireg_uint64(${ireg_base} + ${ireg_next})"
     ireg_next=`expr ${ireg_next} + 1`
 fi