![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to sparc-misc-auto.sh CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [The Machine Emulator] / tme / ic / sparc|
Return to sparc-misc-auto.sh CVS log | Up to [The Machine Emulator] / tme / ic / sparc |
1.1 root 1: #! /bin/sh
2:
1.1.1.2 ! root 3: # $Id: sparc-misc-auto.sh,v 1.4 2010/02/14 00:29:48 fredette Exp $
1.1 root 4:
5: # ic/sparc/sparc-misc-auto.sh - automatically generates C code
6: # for miscellaneous SPARC emulation support:
7:
8: #
9: # Copyright (c) 2005 Matt Fredette
10: # All rights reserved.
11: #
12: # Redistribution and use in source and binary forms, with or without
13: # modification, are permitted provided that the following conditions
14: # are met:
15: # 1. Redistributions of source code must retain the above copyright
16: # notice, this list of conditions and the following disclaimer.
17: # 2. Redistributions in binary form must reproduce the above copyright
18: # notice, this list of conditions and the following disclaimer in the
19: # documentation and/or other materials provided with the distribution.
20: # 3. All advertising materials mentioning features or use of this software
21: # must display the following acknowledgement:
22: # This product includes software developed by Matt Fredette.
23: # 4. The name of the author may not be used to endorse or promote products
24: # derived from this software without specific prior written permission.
25: #
26: # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
27: # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28: # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29: # DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
30: # INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31: # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32: # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33: # HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
34: # STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
35: # ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36: # POSSIBILITY OF SUCH DAMAGE.
37: #
38:
39: header=false
40:
41: for option
42: do
43: case $option in
44: --header) header=true ;;
45: esac
46: done
47:
48: PROG=`basename $0`
49: cat <<EOF
50: /* automatically generated by $PROG, do not edit! */
51: EOF
52:
53: # emit the register mapping macros:
54: if $header; then
55:
56: echo ""
57: echo "/* the register mapping: */"
58: echo "#define TME_SPARC_IREG_UNDEF (-1)"
59: ireg_next=0
60:
61: # all integer registers start from register number zero:
62: #
63: for regnum in 0 1 2 3 4 5 6 7; do
64: echo "#define TME_SPARC_IREG_G${regnum} (${ireg_next})"
65: ireg_next=`expr ${ireg_next} + 1`
66: done
67:
68: # all other registers start after the last register in the last
1.1.1.2 ! root 69: # possible register window:
1.1 root 70: #
1.1.1.2 ! root 71: ireg_base='(TME_SPARC_WINDOWS_MAX * 16)'
! 72:
! 73: # the sparc64 alternate, MMU, and interrupt globals:
! 74: #
! 75: echo "#define TME_SPARC64_IREG_AG_G0 (${ireg_base} + ${ireg_next} + (8 * 0))"
! 76: echo "#define TME_SPARC64_IREG_MG_G0 (${ireg_base} + ${ireg_next} + (8 * 1))"
! 77: echo "#define TME_SPARC64_IREG_IG_G0 (${ireg_base} + ${ireg_next} + (8 * 2))"
! 78: ireg_next=`expr ${ireg_next} + 24`
1.1 root 79:
80: # the current, next, and next-next program counter:
81: #
82: echo "#define TME_SPARC_IREG_PC (${ireg_base} + ${ireg_next})"
83: ireg_next=`expr ${ireg_next} + 1`
84: echo "#define TME_SPARC_IREG_PC_NEXT (${ireg_base} + ${ireg_next})"
85: ireg_next=`expr ${ireg_next} + 1`
86: echo "#define TME_SPARC_IREG_PC_NEXT_NEXT (${ireg_base} + ${ireg_next})"
87: ireg_next=`expr ${ireg_next} + 1`
88:
1.1.1.2 ! root 89: # the instruction register:
! 90: #
! 91: echo "#define TME_SPARC_IREG_INSN (${ireg_base} + ${ireg_next})"
! 92: ireg_next=`expr ${ireg_next} + 1`
! 93:
! 94: # some temporary registers:
1.1 root 95: #
1.1.1.2 ! root 96: echo "#define TME_SPARC_IREG_TMP(x) (${ireg_base} + ${ireg_next} + (x))"
1.1 root 97: ireg_next=`expr ${ireg_next} + 3`
98:
99: # the Y multiply/divide register:
100: #
101: echo "#define TME_SPARC_IREG_Y (${ireg_base} + ${ireg_next})"
102: ireg_next=`expr ${ireg_next} + 1`
103:
104: # the floating-point transfer registers. since these are often
105: # treated as 32-bit parts used to transfer 64- and 128-bit values,
106: # this block of registers must be aligned to four. NB that we
107: # assume that ${ireg_base} is aligned to at least four:
108: #
109: while test `expr ${ireg_next} % 4` != 0; do ireg_next=`expr ${ireg_next} + 1`; done
110: echo "#define TME_SPARC_IREG_FPX (${ireg_base} + ${ireg_next})"
111: ireg_next=`expr ${ireg_next} + 4`
112:
1.1.1.2 ! root 113: # the sparc32 PSR, and the sparc64 PSTATE:
1.1 root 114: #
1.1.1.2 ! root 115: echo "#define TME_SPARC32_IREG_PSR (${ireg_base} + ${ireg_next})"
! 116: echo "#define tme_sparc32_ireg_psr tme_sparc_ireg_uint32(TME_SPARC32_IREG_PSR)"
! 117: echo "#define tme_sparc64_ireg_pstate tme_sparc_ireg_uint32((${ireg_base} + ${ireg_next}) << 1)"
1.1 root 118: ireg_next=`expr ${ireg_next} + 1`
1.1.1.2 ! root 119:
! 120: # the sparc32 WIM, and the common sparc64 register-window state registers:
! 121: #
1.1 root 122: echo "#define tme_sparc32_ireg_wim tme_sparc_ireg_uint32(${ireg_base} + ${ireg_next})"
1.1.1.2 ! root 123: echo "#define tme_sparc64_ireg_winstates tme_sparc_ireg_uint32(((${ireg_base} + ${ireg_next}) << 1) + 0)"
! 124: echo "#define TME_SPARC64_WINSTATES_CWP(x) (((x) & 0x3f) << (8 * 0))"
! 125: echo "#define tme_sparc64_ireg_cwp tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 0)"
! 126: echo "#define TME_SPARC64_WINSTATES_CANRESTORE(x) (((x) & 0x3f) << (8 * 1))"
! 127: echo "#define tme_sparc64_ireg_canrestore tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 1)"
! 128: echo "#define TME_SPARC64_WINSTATES_CANSAVE(x) (((x) & 0x3f) << (8 * 2))"
! 129: echo "#define tme_sparc64_ireg_cansave tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 2)"
! 130: echo "#define TME_SPARC64_WINSTATES_OTHERWIN(x) (((x) & 0x3f) << (8 * 3))"
! 131: echo "#define tme_sparc64_ireg_otherwin tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 3)"
! 132: echo "#define tme_sparc64_ireg_winstates_mask tme_sparc_ireg_uint32(((${ireg_base} + ${ireg_next}) << 1) + 1)"
1.1 root 133: ireg_next=`expr ${ireg_next} + 1`
134:
135: # the sparc32 TBR register, and the sparc64 TBA register:
136: #
137: echo "#define tme_sparc32_ireg_tbr tme_sparc_ireg_uint32(${ireg_base} + ${ireg_next})"
138: echo "#define tme_sparc64_ireg_tba tme_sparc_ireg_uint64(${ireg_base} + ${ireg_next})"
139: ireg_next=`expr ${ireg_next} + 1`
140:
1.1.1.2 ! root 141: # the sparc64 trap PC, NPC, state, and type registers:
! 142: #
! 143: echo "#define tme_sparc64_ireg_tpc(tl) tme_sparc_ireg_uint64(${ireg_base} + (TME_SPARC_TL_MAX * 0) + ${ireg_next} + ((tl) - 1))"
! 144: echo "#define tme_sparc64_ireg_tnpc(tl) tme_sparc_ireg_uint64(${ireg_base} + (TME_SPARC_TL_MAX * 1) + ${ireg_next} + ((tl) - 1))"
! 145: echo "#define TME_SPARC64_IREG_TSTATE(tl) (${ireg_base} + (TME_SPARC_TL_MAX * 2) + ${ireg_next} + ((tl) - 1))"
! 146: echo "#define tme_sparc64_ireg_tstate(tl) tme_sparc_ireg_uint64(TME_SPARC64_IREG_TSTATE(tl))"
! 147: echo "#define tme_sparc64_ireg_tstate_ccr(tl) tme_sparc_ireg_uint8((TME_SPARC64_IREG_TSTATE(tl) << 3) + sizeof(tme_uint32_t))"
! 148: echo "#if TME_SPARC_TL_MAX > 8"
! 149: echo "#error \"TME_SPARC_TL_MAX changed\""
! 150: echo "#endif"
! 151: echo "#define tme_sparc64_ireg_tt(tl) tme_sparc_ireg_uint8(((${ireg_base} + (TME_SPARC_TL_MAX * 3) + ${ireg_next}) << 3) + ((tl) - 1))"
! 152: ireg_base="(${ireg_base} + (TME_SPARC_TL_MAX * 3) + 1)"
! 153:
! 154: # the sparc64 TL, PIL, ASI, FPRS, remaining register-window state registers, and TICK.NPT:
! 155: #
! 156: echo "#define tme_sparc64_ireg_tl tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 0)"
! 157: echo "#define tme_sparc64_ireg_pil tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 1)"
! 158: echo "#define tme_sparc64_ireg_asi tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 2)"
! 159: echo "#define tme_sparc64_ireg_fprs tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 3)"
! 160: echo "#define tme_sparc64_ireg_wstate tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 4)"
! 161: echo "#define tme_sparc64_ireg_cleanwin tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 5)"
! 162: echo "#define tme_sparc64_ireg_tick_npt tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 6)"
! 163: ireg_next=`expr ${ireg_next} + 1`
! 164:
! 165: # the sparc64 TICK (offset) register:
! 166: #
! 167: echo "#define tme_sparc64_ireg_tick_offset tme_sparc_ireg_uint64(${ireg_base} + ${ireg_next})"
! 168: ireg_next=`expr ${ireg_next} + 1`
! 169:
! 170: # the sparc64 version register:
! 171: #
! 172: echo "#define tme_sparc64_ireg_ver tme_sparc_ireg_uint64(${ireg_base} + ${ireg_next})"
! 173: ireg_next=`expr ${ireg_next} + 1`
! 174:
! 175: # the sparc64 CCR:
! 176: # NB: this is a separate register for recode; can it maybe be combined
! 177: # with the block of 8-bit registers above, as the first byte?
! 178: #
! 179: echo "#define TME_SPARC64_IREG_CCR (${ireg_base} + ${ireg_next})"
! 180: echo "#define tme_sparc64_ireg_ccr tme_sparc_ireg_uint8(TME_SPARC64_IREG_CCR << 3)"
! 181: ireg_next=`expr ${ireg_next} + 1`
! 182:
! 183: # our internal sparc64 RCC register:
1.1 root 184: #
1.1.1.2 ! root 185: echo "#define TME_SPARC64_IREG_RCC (${ireg_base} + ${ireg_next})"
1.1 root 186: ireg_next=`expr ${ireg_next} + 1`
187:
1.1.1.2 ! root 188: # our internal virtual address hole start:
1.1 root 189: #
1.1.1.2 ! root 190: echo "#define tme_sparc64_ireg_va_hole_start tme_sparc_ireg_uint64(${ireg_base} + ${ireg_next})"
1.1 root 191: ireg_next=`expr ${ireg_next} + 1`
192: fi
193:
194: # emit the integer condition codes->conditions mapping. note that the
195: # nesting of the flag variables is deliberate, to make this array
196: # indexable with the condition codes value:
197: #
198: if $header; then :; else
199: echo ""
200: echo "/* the icc->conditions mapping: */"
201: echo "const tme_uint8_t _tme_sparc_conds_icc[16] = {"
202: for nflag in 0 1; do
203: for zflag in 0 1; do
204: for vflag in 0 1; do
205: for cflag in 0 1; do
206:
207: # the Never condition:
208: #
209: echo -n " 0"
210:
211: # the Equal condition:
212: #
213: if test $zflag = 1; then
214: echo -n " | TME_BIT(1)"
215: fi
216:
217: # the Less or Equal condition:
218: #
219: if test $zflag = 1 || test $nflag != $vflag; then
220: echo -n " | TME_BIT(2)"
221: fi
222:
223: # the Less condition:
224: #
225: if test $nflag != $vflag; then
226: echo -n " | TME_BIT(3)"
227: fi
228:
229: # the Less or Equal Unsigned condition:
230: #
231: if test $cflag = 1 || test $zflag = 1; then
232: echo -n " | TME_BIT(4)"
233: fi
234:
235: # the Carry Set condition:
236: #
237: if test $cflag = 1; then
238: echo -n " | TME_BIT(5)"
239: fi
240:
241: # the Negative condition:
242: #
243: if test $nflag = 1; then
244: echo -n " | TME_BIT(6)"
245: fi
246:
247: # the Overflow Set condition:
248: #
249: if test $vflag = 1; then
250: echo -n " | TME_BIT(7)"
251: fi
252:
253: echo ","
254: done
255: done
256: done
257: done
258: echo "};"
259: fi
260:
261: # done:
262: #
263: exit 0
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.