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Annotation of tme/machine/sun3/sun3-impl.h, revision 1.1

1.1     ! root        1: /* $Id: sun3-impl.h,v 1.2 2005/02/18 04:07:52 fredette Exp $ */
        !             2: 
        !             3: /* machine/sun3/sun3-impl.h - implementation header file for Sun 3 emulation: */
        !             4: 
        !             5: /*
        !             6:  * Copyright (c) 2003, 2004 Matt Fredette
        !             7:  * All rights reserved.
        !             8:  *
        !             9:  * Redistribution and use in source and binary forms, with or without
        !            10:  * modification, are permitted provided that the following conditions
        !            11:  * are met:
        !            12:  * 1. Redistributions of source code must retain the above copyright
        !            13:  *    notice, this list of conditions and the following disclaimer.
        !            14:  * 2. Redistributions in binary form must reproduce the above copyright
        !            15:  *    notice, this list of conditions and the following disclaimer in the
        !            16:  *    documentation and/or other materials provided with the distribution.
        !            17:  * 3. All advertising materials mentioning features or use of this software
        !            18:  *    must display the following acknowledgement:
        !            19:  *      This product includes software developed by Matt Fredette.
        !            20:  * 4. The name of the author may not be used to endorse or promote products
        !            21:  *    derived from this software without specific prior written permission.
        !            22:  *
        !            23:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
        !            24:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
        !            25:  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
        !            26:  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
        !            27:  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
        !            28:  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
        !            29:  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
        !            30:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
        !            31:  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
        !            32:  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
        !            33:  * POSSIBILITY OF SUCH DAMAGE.
        !            34:  */
        !            35: 
        !            36: #ifndef _MACHINE_SUN3_IMPL_H
        !            37: #define _MACHINE_SUN3_IMPL_H
        !            38: 
        !            39: #include <tme/common.h>
        !            40: _TME_RCSID("$Id: sun3-impl.h,v 1.2 2005/02/18 04:07:52 fredette Exp $");
        !            41: 
        !            42: /* includes: */
        !            43: #include <tme/generic/bus.h>
        !            44: #include <tme/machine/sun.h>
        !            45: #include <tme/ic/m68k.h>
        !            46: #include <tme/element.h>
        !            47: 
        !            48: /* macros: */
        !            49: 
        !            50: /* real sun3 control space addresses: */
        !            51: #define TME_SUN3_CONTROL_IDPROM                (0x00000000)    /* the IDPROM */
        !            52: #define TME_SUN3_CONTROL_PGMAP         (0x10000000)    /* the page map */
        !            53: #define TME_SUN3_CONTROL_SEGMAP                (0x20000000)    /* the segment map */
        !            54: #define TME_SUN3_CONTROL_CONTEXT       (0x30000000)    /* the context register */
        !            55: #define TME_SUN3_CONTROL_ENABLE                (0x40000000)    /* the enable register */
        !            56: #define TME_SUN3_CONTROL_UDVMA         (0x50000000)    /* the user DVMA enable register */
        !            57: #define TME_SUN3_CONTROL_BUSERR                (0x60000000)    /* the bus error register */
        !            58: #define TME_SUN3_CONTROL_DIAG          (0x70000000)    /* the diagnostic register */
        !            59: #define TME_SUN3_CONTROL_VAC_TAGS      (0x80000000)    /* the VAC tags */
        !            60: #define TME_SUN3_CONTROL_VAC_DATA      (0x90000000)    /* the VAC data */
        !            61: #define TME_SUN3_CONTROL_VAC_FLUSH     (0xa0000000)    /* the VAC flush address */
        !            62: #define TME_SUN3_CONTROL_COPY          (0xb0000000)    /* the block copy hardware */
        !            63:                                        /* 0xc0000000 unused */
        !            64:                                        /* 0xd0000000 unused */
        !            65:                                        /* 0xe0000000 unused */
        !            66: #define TME_SUN3_CONTROL_UART_BYPASS   (0xf0000000)    /* the special UART bypass */
        !            67: 
        !            68: /* this converts a sun3 control space address into the register number: */
        !            69: #define TME_SUN3_CONTROL_REG(address)  ((address) >> 28)
        !            70: 
        !            71: /* this masks a sun3 control space address into a virtual address: */
        !            72: #define TME_SUN3_CONTROL_MASK_ADDRESS  (0x0ffffffc)
        !            73: 
        !            74: /* real sun3 enable register bits: */
        !            75: #define TME_SUN3_ENA_DIAG              (0x01)  /* diagnostic switch (read-only) */
        !            76: #define TME_SUN3_ENA_FPA               (0x02)  /* enable FPA */
        !            77: #define TME_SUN3_ENA_COPY              (0x04)  /* enable copy update mode */
        !            78: #define TME_SUN3_ENA_VIDEO             (0x08)  /* enable video display */
        !            79: #define TME_SUN3_ENA_CACHE             (0x10)  /* enable external cache */
        !            80: #define TME_SUN3_ENA_SDVMA             (0x20)  /* enable system DVMA */
        !            81: #define TME_SUN3_ENA_FPP               (0x40)  /* enable 6888x */
        !            82: #define TME_SUN3_ENA_NOTBOOT           (0x80)  /* non-boot state */
        !            83: 
        !            84: /* real sun3 interrupt register bits: */
        !            85: #define TME_SUN3_IREG_INTS_ENAB                (0x01)  /* enable interrupts */
        !            86: #define TME_SUN3_IREG_SOFT_INT_1       (0x02)  /* enable level 1 soft interrupts */
        !            87: #define TME_SUN3_IREG_SOFT_INT_2       (0x04)  /* enable level 2 soft interrupts */
        !            88: #define TME_SUN3_IREG_SOFT_INT_3       (0x08)  /* enable level 3 soft interrupts */
        !            89: #define TME_SUN3_IREG_VIDEO_ENAB       (0x10)  /* enable video */
        !            90: #define TME_SUN3_IREG_CLOCK_ENAB_5     (0x20)  /* enable clock interrupts */
        !            91:                                        /* 0x40 unused */
        !            92: #define TME_SUN3_IREG_CLOCK_ENAB_7     (0x80)  /* enable clock NMI interrupts */
        !            93: 
        !            94: /* real sun3 memory error register parts: */
        !            95: #define TME_SUN3_MEMERR_REG_CSR                (0)
        !            96: #define TME_SUN3_MEMERR_SIZ_CSR                (sizeof(tme_uint8_t))
        !            97: #define TME_SUN3_MEMERR_REG_VADDR      (4)
        !            98: #define TME_SUN3_MEMERR_SIZ_VADDR      (sizeof(tme_uint32_t))
        !            99: #define TME_SUN3_MEMERR_SIZ_REG                (TME_SUN3_MEMERR_REG_VADDR + TME_SUN3_MEMERR_SIZ_VADDR)
        !           100: 
        !           101: /* real sun3 memory error control register bits: */
        !           102: #define TME_SUN3_MEMERR_X_INT_ACTIVE   (0x80)  /* interrupt is active */
        !           103: #define TME_SUN3_MEMERR_X_ENABLE_INT   (0x40)  /* enable memory error interrupts */
        !           104: #define TME_SUN3_MEMERR_PAR_TEST       (0x20)  /* write inverse parity */
        !           105: #define TME_SUN3_MEMERR_PAR_ENABLE     (0x10)  /* enable parity checking */
        !           106: #define TME_SUN3_MEMERR_PAR_ERR_BL3    (0x08)  /* parity error in D24..D31 */
        !           107: #define TME_SUN3_MEMERR_PAR_ERR_BL2    (0x04)  /* parity error in D16..D23 */
        !           108: #define TME_SUN3_MEMERR_PAR_ERR_BL1    (0x02)  /* parity error in D8..D15 */
        !           109: #define TME_SUN3_MEMERR_PAR_ERR_BL0    (0x01)  /* parity error in D0..D7 */
        !           110: 
        !           111: /* the page size: */
        !           112: #define TME_SUN3_PAGE_SIZE_LOG2                (13)
        !           113: #define TME_SUN3_PAGE_SIZE             (1 << TME_SUN3_PAGE_SIZE_LOG2)
        !           114: 
        !           115: /* the number of PMEGs: */
        !           116: #define TME_SUN3_PMEGS                 (256)
        !           117: 
        !           118: /* the PROM location: */
        !           119: #define TME_SUN3_PROM_BASE             (0x0FEF0000)
        !           120: #define TME_SUN3_PROM_SIZE             (0x00010000)
        !           121: 
        !           122: /* the obio addresses of zs0 and the PROM: */
        !           123: #define TME_SUN3_OBIO_ZS0              (0x00020000)
        !           124: #define TME_SUN3_OBIO_PROM             (0x00100000)
        !           125: 
        !           126: /* identifiers for the different mainbus connections.  the buses are
        !           127:    together at the beginning of the value space: */
        !           128: #define TME_SUN3_CONN_BUS_OBIO         (0)
        !           129: #define TME_SUN3_CONN_BUS_OBMEM                (1)
        !           130: #define TME_SUN3_CONN_BUS_VME          (2)
        !           131: #define  TME_SUN3_CONN_BUS_COUNT       (3)
        !           132: #define TME_SUN3_CONN_OBIO_MASTER      (3)
        !           133: #define TME_SUN3_CONN_REG_MEMERR       (4)
        !           134: #define TME_SUN3_CONN_REG_INTREG       (5)
        !           135: 
        !           136: /* the DVMA sizes: */
        !           137: #define TME_SUN3_DVMA_SIZE_OBIO                (0x01000000)
        !           138: #define TME_SUN3_DVMA_SIZE_VME         (0x00100000)
        !           139: 
        !           140: #define TME_SUN3_LOG_HANDLE(sun3) (&(sun3)->tme_sun3_element->tme_element_log_handle)
        !           141: 
        !           142: /* types: */
        !           143: 
        !           144: /* a sun3 mainbus connection: */
        !           145: struct tme_sun3_bus_connection {
        !           146: 
        !           147:   /* the generic bus connection: */
        !           148:   struct tme_bus_connection tme_sun3_bus_connection;
        !           149: 
        !           150:   /* what kind of connection this is: */
        !           151:   unsigned int tme_sun3_bus_connection_which;
        !           152: };
        !           153: 
        !           154: /* a sun3: */
        !           155: struct tme_sun3 {
        !           156: 
        !           157:   /* backpointer to our element: */
        !           158:   struct tme_element *tme_sun3_element;
        !           159: 
        !           160:   /* the IDPROM: */
        !           161:   tme_uint8_t tme_sun3_idprom_contents[TME_SUN_IDPROM_SIZE];
        !           162: 
        !           163:   /* the MMU: */
        !           164:   void *tme_sun3_mmu;
        !           165: 
        !           166:   /* the CPU: */
        !           167:   struct tme_m68k_bus_connection *tme_sun3_m68k;
        !           168: 
        !           169:   /* the different buses: */
        !           170:   struct tme_bus_connection *tme_sun3_buses[TME_SUN3_CONN_BUS_COUNT];
        !           171: #define tme_sun3_obio tme_sun3_buses[TME_SUN3_CONN_BUS_OBIO]
        !           172: #define tme_sun3_obmem tme_sun3_buses[TME_SUN3_CONN_BUS_OBMEM]
        !           173: #define tme_sun3_vmebus tme_sun3_buses[TME_SUN3_CONN_BUS_VME]
        !           174: 
        !           175:   /* the context register: */
        !           176:   tme_uint8_t tme_sun3_context;
        !           177: 
        !           178:   /* the enable register: */
        !           179:   tme_uint8_t tme_sun3_enable;
        !           180: 
        !           181:   /* the UDVMA register: */
        !           182:   tme_uint8_t tme_sun3_udvma;
        !           183: 
        !           184:   /* the bus error register: */
        !           185:   tme_uint8_t tme_sun3_buserr;
        !           186: 
        !           187:   /* the diagnostic register: */
        !           188:   tme_uint8_t tme_sun3_diag;
        !           189: 
        !           190:   /* the interrupt register: */
        !           191:   tme_uint8_t tme_sun3_ints;
        !           192: 
        !           193:   /* the memory error register: */
        !           194:   tme_uint8_t tme_sun3_memerr_csr;
        !           195:   tme_uint32_t tme_sun3_memerr_vaddr;
        !           196:   unsigned int tme_sun3_memerr_int_asserted;
        !           197:   struct tme_bus_connection *tme_sun3_memerr_bus;
        !           198: 
        !           199:   /* memory error register test state: */
        !           200:   struct tme_bus_tlb *tme_sun3_memerr_tlb;
        !           201:   void *tme_sun3_memerr_cycle_private;
        !           202:   tme_bus_cycle_handler tme_sun3_memerr_cycle;
        !           203:   tme_uint8_t tme_sun3_memerr_pending_csr;
        !           204:   tme_uint32_t tme_sun3_memerr_pending_vaddr;
        !           205: 
        !           206:   /* the interrupt lines that are being asserted: */
        !           207:   tme_uint8_t tme_sun3_int_signals[(TME_M68K_IPL_MAX + 1 + 7) >> 3];
        !           208: 
        !           209:   /* the last ipl we gave to the CPU: */
        !           210:   unsigned int tme_sun3_int_ipl_last;
        !           211: 
        !           212:   /* the last clock interrupt bus signal: */
        !           213:   unsigned int tme_sun3_int_signal_clock_last;
        !           214: 
        !           215:   /* the set of active boot state TLB entries: */
        !           216:   unsigned int tme_sun3_boot_state_tlb_next;
        !           217: #define TME_SUN3_BOOT_STATE_TLBS       (8)
        !           218:   struct tme_bus_tlb *tme_sun3_boot_state_tlbs[TME_SUN3_BOOT_STATE_TLBS];
        !           219: 
        !           220:   /* the set of active SDVMA TLB entries: */
        !           221:   unsigned int tme_sun3_sdvma_tlb_next;
        !           222: #define TME_SUN3_SDVMA_TLBS            (16)
        !           223:   struct tme_bus_tlb *tme_sun3_sdvma_tlbs[TME_SUN3_SDVMA_TLBS];
        !           224: };
        !           225: 
        !           226: /* prototypes: */
        !           227: void _tme_sun3_mmu_new _TME_P((struct tme_sun3 *));
        !           228: int _tme_sun3_m68k_tlb_fill _TME_P((struct tme_m68k_bus_connection *, struct tme_m68k_tlb *,
        !           229:                                    unsigned int, tme_uint32_t, unsigned int));
        !           230: int _tme_sun3_bus_tlb_fill _TME_P((struct tme_bus_connection *, struct tme_bus_tlb *,
        !           231:                                   tme_uint32_t, unsigned int));
        !           232: int _tme_sun3_mmu_tlb_set_allocate _TME_P((struct tme_bus_connection *,
        !           233:                                           unsigned int, unsigned int, 
        !           234:                                           TME_ATOMIC_POINTER_TYPE(struct tme_bus_tlb *)));
        !           235: int _tme_sun3_mmu_pte_get _TME_P((struct tme_sun3 *, tme_uint32_t, tme_uint32_t *));
        !           236: int _tme_sun3_mmu_pte_set _TME_P((struct tme_sun3 *, tme_uint32_t, tme_uint32_t));
        !           237: void _tme_sun3_mmu_sdvma_change _TME_P((struct tme_sun3 *));
        !           238: void _tme_sun3_mmu_context_set _TME_P((struct tme_sun3 *));
        !           239: 
        !           240: int _tme_sun3_control_cycle_handler _TME_P((void *, struct tme_bus_cycle *));
        !           241: int _tme_sun3_intreg_cycle_handler _TME_P((void *, struct tme_bus_cycle *));
        !           242: int _tme_sun3_memerr_cycle_handler _TME_P((void *, struct tme_bus_cycle *));
        !           243: int _tme_sun3_memerr_test_cycle_handler _TME_P((void *, struct tme_bus_cycle *));
        !           244: int _tme_sun3_ipl_check _TME_P((struct tme_sun3 *));
        !           245: 
        !           246: #endif /* !_MACHINE_SUN3_IMPL_H */

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