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1.1 root 1: /*
2: * UAE - The Un*x Amiga Emulator
3: *
4: * memory management
5: *
6: * (c) 1995 Bernd Schmidt
7: */
8:
9: #define chipmem_size 0x200000
1.1.1.2 ! root 10: #define bogomem_size 0x100000 /* C00000 crap mem */
! 11: #define kickmem_size 0x080000
1.1 root 12:
1.1.1.2 ! root 13: #define chipmem_start 0x000000
1.1 root 14: #define bogomem_start 0xC00000
15: #define kickmem_start 0xF80000
16:
1.1.1.2 ! root 17: extern int ersatzkickfile;
! 18:
1.1 root 19: typedef ULONG (*lget_func)(CPTR) REGPARAM;
20: typedef UWORD (*wget_func)(CPTR) REGPARAM;
21: typedef UBYTE (*bget_func)(CPTR) REGPARAM;
22: typedef void (*lput_func)(CPTR,ULONG) REGPARAM;
23: typedef void (*wput_func)(CPTR,UWORD) REGPARAM;
24: typedef void (*bput_func)(CPTR,UBYTE) REGPARAM;
25: typedef UWORD *(*xlate_func)(CPTR) REGPARAM;
1.1.1.2 ! root 26: typedef int (*check_func)(CPTR, ULONG) REGPARAM;
1.1 root 27:
28: typedef struct {
29: lget_func lget;
30: wget_func wget;
31: bget_func bget;
32: lput_func lput;
33: wput_func wput;
34: bput_func bput;
35: xlate_func xlateaddr;
36: check_func check;
37: } addrbank;
38:
39: extern addrbank chipmem_bank;
40: extern addrbank kickmem_bank;
41: extern addrbank custom_bank;
42: extern addrbank clock_bank;
43: extern addrbank cia_bank;
44: extern addrbank rtarea_bank;
1.1.1.2 ! root 45: extern addrbank expamem_bank;
! 46: extern addrbank fastmem_bank;
1.1 root 47:
48: extern void rtarea_init (void);
1.1.1.2 ! root 49: extern void expamem_init (void);
! 50: extern void expamem_reset (void);
! 51:
! 52: extern ULONG fastmem_size;
! 53:
1.1 root 54:
55: /* Default memory access functions */
56:
1.1.1.2 ! root 57: extern int default_check(CPTR addr, ULONG size) REGPARAM;
1.1 root 58: extern UWORD *default_xlate(CPTR addr) REGPARAM;
59:
1.1.1.2 ! root 60: extern addrbank membanks[65536];
! 61: static __inline__ unsigned int bankindex(CPTR a)
1.1 root 62: {
63: return a>>16;
64: }
65:
66: static __inline__ ULONG longget(CPTR addr)
67: {
1.1.1.2 ! root 68: return membanks[bankindex(addr)].lget(addr);
1.1 root 69: }
70: static __inline__ UWORD wordget(CPTR addr)
71: {
1.1.1.2 ! root 72: return membanks[bankindex(addr)].wget(addr);
1.1 root 73: }
74: static __inline__ UBYTE byteget(CPTR addr)
75: {
1.1.1.2 ! root 76: return membanks[bankindex(addr)].bget(addr);
1.1 root 77: }
78: static __inline__ void longput(CPTR addr, ULONG l)
79: {
1.1.1.2 ! root 80: membanks[bankindex(addr)].lput(addr, l);
1.1 root 81: }
82: static __inline__ void wordput(CPTR addr, UWORD w)
83: {
1.1.1.2 ! root 84: membanks[bankindex(addr)].wput(addr, w);
1.1 root 85: }
86: static __inline__ void byteput(CPTR addr, UBYTE b)
87: {
1.1.1.2 ! root 88: membanks[bankindex(addr)].bput(addr, b);
1.1 root 89: }
90:
1.1.1.2 ! root 91: static __inline__ int check_addr(CPTR a)
1.1 root 92: {
93: #ifdef NO_EXCEPTION_3
1.1.1.2 ! root 94: return 1;
1.1 root 95: #else
96: return (a & 1) == 0;
97: #endif
98: }
1.1.1.2 ! root 99: extern int buserr;
1.1 root 100:
101: extern void memory_init(void);
102: extern void map_banks(addrbank bank, int first, int count);
103:
104: static __inline__ ULONG get_long(CPTR addr)
105: {
106: if (check_addr(addr))
107: return longget(addr);
1.1.1.2 ! root 108: buserr = 1;
1.1 root 109: return 0;
110: }
111: static __inline__ UWORD get_word(CPTR addr)
112: {
113: if (check_addr(addr))
114: return wordget(addr);
1.1.1.2 ! root 115: buserr = 1;
1.1 root 116: return 0;
117: }
118: static __inline__ UBYTE get_byte(CPTR addr)
119: {
120: return byteget(addr);
121: }
122: static __inline__ void put_long(CPTR addr, ULONG l)
123: {
124: if (!check_addr(addr))
1.1.1.2 ! root 125: buserr = 1;
1.1 root 126: longput(addr, l);
127: }
128: static __inline__ void put_word(CPTR addr, UWORD w)
129: {
130: if (!check_addr(addr))
1.1.1.2 ! root 131: buserr = 1;
1.1 root 132: wordput(addr, w);
133: }
134: static __inline__ void put_byte(CPTR addr, UBYTE b)
135: {
136: byteput(addr, b);
137: }
138:
139: static __inline__ UWORD *get_real_address(CPTR addr)
140: {
141: if (!check_addr(addr))
1.1.1.2 ! root 142: buserr = 1;
! 143: return membanks[bankindex(addr)].xlateaddr(addr);
1.1 root 144: }
145:
1.1.1.2 ! root 146: static __inline__ int valid_address(CPTR addr, ULONG size)
1.1 root 147: {
148: if (!check_addr(addr))
1.1.1.2 ! root 149: buserr = 1;
! 150: return membanks[bankindex(addr)].check(addr, size);
1.1 root 151: }
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