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1.1 root 1: /*
2: * UAE - The Un*x Amiga Emulator
3: *
4: * Routines for labelling amiga internals.
5: *
6: */
7:
8: #include "sysconfig.h"
9: #include "sysdeps.h"
10: #include "memory.h"
11: #include "identify.h"
12:
13: struct mem_labels int_labels[] =
14: {
15: { "Reset:SSP", 0x0000 },
16: { "EXECBASE", 0x0004 },
17: { "BUS ERROR", 0x0008 },
18: { "ADR ERROR", 0x000C },
19: { "ILLEG OPC", 0x0010 },
20: { "DIV BY 0", 0x0014 },
21: { "CHK", 0x0018 },
22: { "TRAPV", 0x001C },
23: { "PRIVIL VIO", 0x0020 },
24: { "TRACE", 0x0024 },
25: { "LINEA EMU", 0x0028 },
26: { "LINEF EMU", 0x002C },
27: { "INT Uninit", 0x003C },
28: { "INT Unjust", 0x0060 },
29: { "Lvl 1 Int", 0x0064 },
30: { "Lvl 2 Int", 0x0068 },
31: { "Lvl 3 Int", 0x006C },
32: { "Lvl 4 Int", 0x0070 },
33: { "Lvl 5 Int", 0x0074 },
34: { "Lvl 6 Int", 0x0078 },
35: { "NMI", 0x007C },
36: { 0, 0 }
37: };
38:
39: struct mem_labels trap_labels[] =
40: {
41: { "TRAP 01", 0x0080 },
42: { "TRAP 02", 0x0084 },
43: { "TRAP 03", 0x0088 },
44: { "TRAP 04", 0x008C },
45: { "TRAP 05", 0x0090 },
46: { "TRAP 06", 0x0094 },
47: { "TRAP 07", 0x0098 },
48: { "TRAP 08", 0x009C },
49: { "TRAP 09", 0x00A0 },
50: { "TRAP 10", 0x00A4 },
51: { "TRAP 11", 0x00A8 },
52: { "TRAP 12", 0x00AC },
53: { "TRAP 13", 0x00B0 },
54: { "TRAP 14", 0x00B4 },
55: { "TRAP 15", 0x00B8 },
56: { 0, 0 }
57: };
58:
59: struct mem_labels mem_labels[] =
60: {
61: { "CIAB PRA", 0xBFD000 },
62: { "CIAB PRB", 0xBFD100 },
63: { "CIAB DDRA", 0xBFD200 },
64: { "CIAB DDRB", 0xBFD300 },
65: { "CIAB TALO", 0xBFD400 },
66: { "CIAB TAHI", 0xBFD500 },
67: { "CIAB TBLO", 0xBFD600 },
68: { "CIAB TBHI", 0xBFD700 },
69: { "CIAB TDLO", 0xBFD800 },
70: { "CIAB TDMD", 0xBFD900 },
71: { "CIAB TDHI", 0xBFDA00 },
72: { "CIAB SDR", 0xBFDC00 },
73: { "CIAB ICR", 0xBFDD00 },
74: { "CIAB CRA", 0xBFDE00 },
75: { "CIAB CRB", 0xBFDF00 },
76: { "CIAA PRA", 0xBFE001 },
77: { "CIAA PRB", 0xBFE101 },
78: { "CIAA DDRA", 0xBFE201 },
79: { "CIAA DDRB", 0xBFE301 },
80: { "CIAA TALO", 0xBFE401 },
81: { "CIAA TAHI", 0xBFE501 },
82: { "CIAA TBLO", 0xBFE601 },
83: { "CIAA TBHI", 0xBFE701 },
84: { "CIAA TDLO", 0xBFE801 },
85: { "CIAA TDMD", 0xBFE901 },
86: { "CIAA TDHI", 0xBFEA01 },
87: { "CIAA SDR", 0xBFEC01 },
88: { "CIAA ICR", 0xBFED01 },
89: { "CIAA CRA", 0xBFEE01 },
90: { "CIAA CRB", 0xBFEF01 },
91: { "CLK S1", 0xDC0000 },
92: { "CLK S10", 0xDC0004 },
93: { "CLK MI1", 0xDC0008 },
94: { "CLK MI10", 0xDC000C },
95: { "CLK H1", 0xDC0010 },
96: { "CLK H10", 0xDC0014 },
97: { "CLK D1", 0xDC0018 },
98: { "CLK D10", 0xDC001C },
99: { "CLK MO1", 0xDC0020 },
100: { "CLK MO10", 0xDC0024 },
101: { "CLK Y1", 0xDC0028 },
102: { "CLK Y10", 0xDC002E },
103: { "CLK WEEK", 0xDC0030 },
104: { "CLK CD", 0xDC0034 },
105: { "CLK CE", 0xDC0038 },
106: { "CLK CF", 0xDC003C },
107: { NULL, 0 }
108: };
109:
110: /* This table was generated from the list of AGA chip names in
111: * AGA.guide available on aminet. It could well have errors in it. */
112:
113: struct customData custd[] =
114: {
115: { "BLTDDAT", 0xdff000 }, /* Blitter dest. early read (dummy address) */
116: { "DMACONR", 0xdff002 }, /* Dma control (and blitter status) read */
117: { "VPOSR", 0xdff004 }, /* Read vert most sig. bits (and frame flop */
118: { "VHPOSR", 0xdff006 }, /* Read vert and horiz position of beam */
119: { "DSKDATR", 0xdff008 }, /* Disk data early read (dummy address) */
120: { "JOY0DAT", 0xdff00A }, /* Joystick-mouse 0 data (vert,horiz) */
121: { "JOT1DAT", 0xdff00C }, /* Joystick-mouse 1 data (vert,horiz) */
122: { "CLXDAT", 0xdff00E }, /* Collision data reg. (read and clear) */
123: { "ADKCONR", 0xdff010 }, /* Audio,disk control register read */
124: { "POT0DAT", 0xdff012 }, /* Pot counter pair 0 data (vert,horiz) */
125: { "POT1DAT", 0xdff014 }, /* Pot counter pair 1 data (vert,horiz) */
126: { "POTINP", 0xdff016 }, /* Pot pin data read */
127: { "SERDATR", 0xdff018 }, /* Serial port data and status read */
128: { "DSKBYTR", 0xdff01A }, /* Disk data byte and status read */
129: { "INTENAR", 0xdff01C }, /* Interrupt enable bits read */
130: { "INTREQR", 0xdff01E }, /* Interrupt request bits read */
131: { "DSKPTH", 0xdff020 }, /* Disk pointer (high 5 bits) */
132: { "DSKPTL", 0xdff022 }, /* Disk pointer (low 15 bits) */
133: { "DSKLEN", 0xdff024 }, /* Disk lentgh */
134: { "DSKDAT", 0xdff026 }, /* Disk DMA data write */
135: { "REFPTR", 0xdff028 }, /* Refresh pointer */
136: { "VPOSW", 0xdff02A }, /* Write vert most sig. bits(and frame flop) */
137: { "VHPOSW", 0xdff02C }, /* Write vert and horiz pos of beam */
138: { "COPCON", 0xdff02e }, /* Coprocessor control reg (CDANG) */
139: { "SERDAT", 0xdff030 }, /* Serial port data and stop bits write */
140: { "SERPER", 0xdff032 }, /* Serial port period and control */
141: { "POTGO", 0xdff034 }, /* Pot count start,pot pin drive enable data */
142: { "JOYTEST", 0xdff036 }, /* Write to all 4 joystick-mouse counters at once */
143: { "STREQU", 0xdff038 }, /* Strobe for horiz sync with VB and EQU */
144: { "STRVBL", 0xdff03A }, /* Strobe for horiz sync with VB (vert blank) */
145: { "STRHOR", 0xdff03C }, /* Strobe for horiz sync */
146: { "STRLONG", 0xdff03E }, /* Strobe for identification of long horiz line */
147: { "BLTCON0", 0xdff040 }, /* Blitter control reg 0 */
148: { "BLTCON1", 0xdff042 }, /* Blitter control reg 1 */
149: { "BLTAFWM", 0xdff044 }, /* Blitter first word mask for source A */
150: { "BLTALWM", 0xdff046 }, /* Blitter last word mask for source A */
151: { "BLTCPTH", 0xdff048 }, /* Blitter pointer to source C (high 5 bits) */
152: { "BLTCPTL", 0xdff04A }, /* Blitter pointer to source C (low 15 bits) */
153: { "BLTBPTH", 0xdff04C }, /* Blitter pointer to source B (high 5 bits) */
154: { "BLTBPTL", 0xdff04E }, /* Blitter pointer to source B (low 15 bits) */
155: { "BLTAPTH", 0xdff050 }, /* Blitter pointer to source A (high 5 bits) */
156: { "BLTAPTL", 0xdff052 }, /* Blitter pointer to source A (low 15 bits) */
157: { "BPTDPTH", 0xdff054 }, /* Blitter pointer to destn D (high 5 bits) */
158: { "BLTDPTL", 0xdff056 }, /* Blitter pointer to destn D (low 15 bits) */
159: { "BLTSIZE", 0xdff058 }, /* Blitter start and size (win/width,height) */
160: { "BLTCON0L", 0xdff05A }, /* Blitter control 0 lower 8 bits (minterms) */
161: { "BLTSIZV", 0xdff05C }, /* Blitter V size (for 15 bit vert size) */
162: { "BLTSIZH", 0xdff05E }, /* Blitter H size & start (for 11 bit H size) */
163: { "BLTCMOD", 0xdff060 }, /* Blitter modulo for source C */
164: { "BLTBMOD", 0xdff062 }, /* Blitter modulo for source B */
165: { "BLTAMOD", 0xdff064 }, /* Blitter modulo for source A */
166: { "BLTDMOD", 0xdff066 }, /* Blitter modulo for destn D */
167: { "Unknown", 0xdff068 }, /* Unknown or Unused */
168: { "Unknown", 0xdff06a }, /* Unknown or Unused */
169: { "Unknown", 0xdff06c }, /* Unknown or Unused */
170: { "Unknown", 0xdff06e }, /* Unknown or Unused */
171: { "BLTCDAT", 0xdff070 }, /* Blitter source C data reg */
172: { "BLTBDAT", 0xdff072 }, /* Blitter source B data reg */
173: { "BLTADAT", 0xdff074 }, /* Blitter source A data reg */
174: { "BLTDDAT", 0xdff076 }, /* Blitter destination reg */
175: { "SPRHDAT", 0xdff078 }, /* Ext logic UHRES sprite pointer and data identifier */
176: { "BPLHDAT", 0xdff07A }, /* Ext logic UHRES bit plane identifier */
177: { "LISAID", 0xdff07C }, /* Chip revision level for Denise/Lisa */
178: { "DSKSYNC", 0xdff07E }, /* Disk sync pattern reg for disk read */
179: { "COP1LCH", 0xdff080 }, /* Coprocessor first location reg (high 5 bits) */
180: { "COP1LCL", 0xdff082 }, /* Coprocessor first location reg (low 15 bits) */
181: { "COP2LCH", 0xdff084 }, /* Coprocessor second reg (high 5 bits) */
182: { "COP2LCL", 0xdff086 }, /* Coprocessor second reg (low 15 bits) */
183: { "COPJMP1", 0xdff088 }, /* Coprocessor restart at first location */
184: { "COPJMP2", 0xdff08A }, /* Coprocessor restart at second location */
185: { "COPINS", 0xdff08C }, /* Coprocessor inst fetch identify */
186: { "DIWSTRT", 0xdff08E }, /* Display window start (upper left vert-hor pos) */
187: { "DIWSTOP", 0xdff090 }, /* Display window stop (lower right vert-hor pos) */
188: { "DDFSTRT", 0xdff092 }, /* Display bit plane data fetch start.hor pos */
189: { "DDFSTOP", 0xdff094 }, /* Display bit plane data fetch stop.hor pos */
190: { "DMACON", 0xdff096 }, /* DMA control write (clear or set) */
191: { "CLXCON", 0xdff098 }, /* Collision control */
192: { "INTENA", 0xdff09A }, /* Interrupt enable bits (clear or set bits) */
193: { "INTREQ", 0xdff09C }, /* Interrupt request bits (clear or set bits) */
194: { "ADKCON", 0xdff09E }, /* Audio,disk,UART,control */
195: { "AUD0LCH", 0xdff0A0 }, /* Audio channel 0 location (high 5 bits) */
196: { "AUD0LCL", 0xdff0A2 }, /* Audio channel 0 location (low 15 bits) */
197: { "AUD0LEN", 0xdff0A4 }, /* Audio channel 0 lentgh */
198: { "AUD0PER", 0xdff0A6 }, /* Audio channel 0 period */
199: { "AUD0VOL", 0xdff0A8 }, /* Audio channel 0 volume */
200: { "AUD0DAT", 0xdff0AA }, /* Audio channel 0 data */
201: { "Unknown", 0xdff0AC }, /* Unknown or Unused */
202: { "Unknown", 0xdff0AE }, /* Unknown or Unused */
203: { "AUD1LCH", 0xdff0B0 }, /* Audio channel 1 location (high 5 bits) */
204: { "AUD1LCL", 0xdff0B2 }, /* Audio channel 1 location (low 15 bits) */
205: { "AUD1LEN", 0xdff0B4 }, /* Audio channel 1 lentgh */
206: { "AUD1PER", 0xdff0B6 }, /* Audio channel 1 period */
207: { "AUD1VOL", 0xdff0B8 }, /* Audio channel 1 volume */
208: { "AUD1DAT", 0xdff0BA }, /* Audio channel 1 data */
209: { "Unknown", 0xdff0BC }, /* Unknown or Unused */
210: { "Unknown", 0xdff0BE }, /* Unknown or Unused */
211: { "AUD2LCH", 0xdff0C0 }, /* Audio channel 2 location (high 5 bits) */
212: { "AUD2LCL", 0xdff0C2 }, /* Audio channel 2 location (low 15 bits) */
213: { "AUD2LEN", 0xdff0C4 }, /* Audio channel 2 lentgh */
214: { "AUD2PER", 0xdff0C6 }, /* Audio channel 2 period */
215: { "AUD2VOL", 0xdff0C8 }, /* Audio channel 2 volume */
216: { "AUD2DAT", 0xdff0CA }, /* Audio channel 2 data */
217: { "Unknown", 0xdff0CC }, /* Unknown or Unused */
218: { "Unknown", 0xdff0CE }, /* Unknown or Unused */
219: { "AUD3LCH", 0xdff0D0 }, /* Audio channel 3 location (high 5 bits) */
220: { "AUD3LCL", 0xdff0D2 }, /* Audio channel 3 location (low 15 bits) */
221: { "AUD3LEN", 0xdff0D4 }, /* Audio channel 3 lentgh */
222: { "AUD3PER", 0xdff0D6 }, /* Audio channel 3 period */
223: { "AUD3VOL", 0xdff0D8 }, /* Audio channel 3 volume */
224: { "AUD3DAT", 0xdff0DA }, /* Audio channel 3 data */
225: { "Unknown", 0xdff0DC }, /* Unknown or Unused */
226: { "Unknown", 0xdff0DE }, /* Unknown or Unused */
227: { "BPL1PTH", 0xdff0E0 }, /* Bit plane pointer 1 (high 5 bits) */
228: { "BPL1PTL", 0xdff0E2 }, /* Bit plane pointer 1 (low 15 bits) */
229: { "BPL2PTH", 0xdff0E4 }, /* Bit plane pointer 2 (high 5 bits) */
230: { "BPL2PTL", 0xdff0E6 }, /* Bit plane pointer 2 (low 15 bits) */
231: { "BPL3PTH", 0xdff0E8 }, /* Bit plane pointer 3 (high 5 bits) */
232: { "BPL3PTL", 0xdff0EA }, /* Bit plane pointer 3 (low 15 bits) */
233: { "BPL4PTH", 0xdff0EC }, /* Bit plane pointer 4 (high 5 bits) */
234: { "BPL4PTL", 0xdff0EE }, /* Bit plane pointer 4 (low 15 bits) */
235: { "BPL5PTH", 0xdff0F0 }, /* Bit plane pointer 5 (high 5 bits) */
236: { "BPL5PTL", 0xdff0F2 }, /* Bit plane pointer 5 (low 15 bits) */
237: { "BPL6PTH", 0xdff0F4 }, /* Bit plane pointer 6 (high 5 bits) */
238: { "BPL6PTL", 0xdff0F6 }, /* Bit plane pointer 6 (low 15 bits) */
239: { "BPL7PTH", 0xdff0F8 }, /* Bit plane pointer 7 (high 5 bits) */
240: { "BPL7PTL", 0xdff0FA }, /* Bit plane pointer 7 (low 15 bits) */
241: { "BPL8PTH", 0xdff0FC }, /* Bit plane pointer 8 (high 5 bits) */
242: { "BPL8PTL", 0xdff0FE }, /* Bit plane pointer 8 (low 15 bits) */
243: { "BPLCON0", 0xdff100 }, /* Bit plane control reg (misc control bits) */
244: { "BPLCON1", 0xdff102 }, /* Bit plane control reg (scroll val PF1,PF2) */
245: { "BPLCON2", 0xdff104 }, /* Bit plane control reg (priority control) */
246: { "BPLCON3", 0xdff106 }, /* Bit plane control reg (enhanced features) */
247: { "BPL1MOD", 0xdff108 }, /* Bit plane modulo (odd planes,or active- fetch lines if bitplane scan-doubling is enabled */
248: { "BPL2MOD", 0xdff10A }, /* Bit plane modulo (even planes or inactive- fetch lines if bitplane scan-doubling is enabled */
249: { "BPLCON4", 0xdff10C }, /* Bit plane control reg (bitplane and sprite masks) */
250: { "CLXCON2", 0xdff10e }, /* Extended collision control reg */
251: { "BPL1DAT", 0xdff110 }, /* Bit plane 1 data (parallel to serial con- vert) */
252: { "BPL2DAT", 0xdff112 }, /* Bit plane 2 data (parallel to serial con- vert) */
253: { "BPL3DAT", 0xdff114 }, /* Bit plane 3 data (parallel to serial con- vert) */
254: { "BPL4DAT", 0xdff116 }, /* Bit plane 4 data (parallel to serial con- vert) */
255: { "BPL5DAT", 0xdff118 }, /* Bit plane 5 data (parallel to serial con- vert) */
256: { "BPL6DAT", 0xdff11a }, /* Bit plane 6 data (parallel to serial con- vert) */
257: { "BPL7DAT", 0xdff11c }, /* Bit plane 7 data (parallel to serial con- vert) */
258: { "BPL8DAT", 0xdff11e }, /* Bit plane 8 data (parallel to serial con- vert) */
259: { "SPR0PTH", 0xdff120 }, /* Sprite 0 pointer (high 5 bits) */
260: { "SPR0PTL", 0xdff122 }, /* Sprite 0 pointer (low 15 bits) */
261: { "SPR1PTH", 0xdff124 }, /* Sprite 1 pointer (high 5 bits) */
262: { "SPR1PTL", 0xdff126 }, /* Sprite 1 pointer (low 15 bits) */
263: { "SPR2PTH", 0xdff128 }, /* Sprite 2 pointer (high 5 bits) */
264: { "SPR2PTL", 0xdff12A }, /* Sprite 2 pointer (low 15 bits) */
265: { "SPR3PTH", 0xdff12C }, /* Sprite 3 pointer (high 5 bits) */
266: { "SPR3PTL", 0xdff12E }, /* Sprite 3 pointer (low 15 bits) */
267: { "SPR4PTH", 0xdff130 }, /* Sprite 4 pointer (high 5 bits) */
268: { "SPR4PTL", 0xdff132 }, /* Sprite 4 pointer (low 15 bits) */
269: { "SPR5PTH", 0xdff134 }, /* Sprite 5 pointer (high 5 bits) */
270: { "SPR5PTL", 0xdff136 }, /* Sprite 5 pointer (low 15 bits) */
271: { "SPR6PTH", 0xdff138 }, /* Sprite 6 pointer (high 5 bits) */
272: { "SPR6PTL", 0xdff13A }, /* Sprite 6 pointer (low 15 bits) */
273: { "SPR7PTH", 0xdff13C }, /* Sprite 7 pointer (high 5 bits) */
274: { "SPR7PTL", 0xdff13E }, /* Sprite 7 pointer (low 15 bits) */
275: { "SPR0POS", 0xdff140 }, /* Sprite 0 vert-horiz start pos data */
276: { "SPR0CTL", 0xdff142 }, /* Sprite 0 position and control data */
277: { "SPR0DATA", 0xdff144 }, /* Sprite 0 image data register A */
278: { "SPR0DATB", 0xdff146 }, /* Sprite 0 image data register B */
279: { "SPR1POS", 0xdff148 }, /* Sprite 1 vert-horiz start pos data */
280: { "SPR1CTL", 0xdff14A }, /* Sprite 1 position and control data */
281: { "SPR1DATA", 0xdff14C }, /* Sprite 1 image data register A */
282: { "SPR1DATB", 0xdff14E }, /* Sprite 1 image data register B */
283: { "SPR2POS", 0xdff150 }, /* Sprite 2 vert-horiz start pos data */
284: { "SPR2CTL", 0xdff152 }, /* Sprite 2 position and control data */
285: { "SPR2DATA", 0xdff154 }, /* Sprite 2 image data register A */
286: { "SPR2DATB", 0xdff156 }, /* Sprite 2 image data register B */
287: { "SPR3POS", 0xdff158 }, /* Sprite 3 vert-horiz start pos data */
288: { "SPR3CTL", 0xdff15A }, /* Sprite 3 position and control data */
289: { "SPR3DATA", 0xdff15C }, /* Sprite 3 image data register A */
290: { "SPR3DATB", 0xdff15E }, /* Sprite 3 image data register B */
291: { "SPR4POS", 0xdff160 }, /* Sprite 4 vert-horiz start pos data */
292: { "SPR4CTL", 0xdff162 }, /* Sprite 4 position and control data */
293: { "SPR4DATA", 0xdff164 }, /* Sprite 4 image data register A */
294: { "SPR4DATB", 0xdff166 }, /* Sprite 4 image data register B */
295: { "SPR5POS", 0xdff168 }, /* Sprite 5 vert-horiz start pos data */
296: { "SPR5CTL", 0xdff16A }, /* Sprite 5 position and control data */
297: { "SPR5DATA", 0xdff16C }, /* Sprite 5 image data register A */
298: { "SPR5DATB", 0xdff16E }, /* Sprite 5 image data register B */
299: { "SPR6POS", 0xdff170 }, /* Sprite 6 vert-horiz start pos data */
300: { "SPR6CTL", 0xdff172 }, /* Sprite 6 position and control data */
301: { "SPR6DATA", 0xdff174 }, /* Sprite 6 image data register A */
302: { "SPR6DATB", 0xdff176 }, /* Sprite 6 image data register B */
303: { "SPR7POS", 0xdff178 }, /* Sprite 7 vert-horiz start pos data */
304: { "SPR7CTL", 0xdff17A }, /* Sprite 7 position and control data */
305: { "SPR7DATA", 0xdff17C }, /* Sprite 7 image data register A */
306: { "SPR7DATB", 0xdff17E }, /* Sprite 7 image data register B */
307: { "COLOR00", 0xdff180 }, /* Color table 00 */
308: { "COLOR01", 0xdff182 }, /* Color table 01 */
309: { "COLOR02", 0xdff184 }, /* Color table 02 */
310: { "COLOR03", 0xdff186 }, /* Color table 03 */
311: { "COLOR04", 0xdff188 }, /* Color table 04 */
312: { "COLOR05", 0xdff18A }, /* Color table 05 */
313: { "COLOR06", 0xdff18C }, /* Color table 06 */
314: { "COLOR07", 0xdff18E }, /* Color table 07 */
315: { "COLOR08", 0xdff190 }, /* Color table 08 */
316: { "COLOR09", 0xdff192 }, /* Color table 09 */
317: { "COLOR10", 0xdff194 }, /* Color table 10 */
318: { "COLOR11", 0xdff196 }, /* Color table 11 */
319: { "COLOR12", 0xdff198 }, /* Color table 12 */
320: { "COLOR13", 0xdff19A }, /* Color table 13 */
321: { "COLOR14", 0xdff19C }, /* Color table 14 */
322: { "COLOR15", 0xdff19E }, /* Color table 15 */
323: { "COLOR16", 0xdff1A0 }, /* Color table 16 */
324: { "COLOR17", 0xdff1A2 }, /* Color table 17 */
325: { "COLOR18", 0xdff1A4 }, /* Color table 18 */
326: { "COLOR19", 0xdff1A6 }, /* Color table 19 */
327: { "COLOR20", 0xdff1A8 }, /* Color table 20 */
328: { "COLOR21", 0xdff1AA }, /* Color table 21 */
329: { "COLOR22", 0xdff1AC }, /* Color table 22 */
330: { "COLOR23", 0xdff1AE }, /* Color table 23 */
331: { "COLOR24", 0xdff1B0 }, /* Color table 24 */
332: { "COLOR25", 0xdff1B2 }, /* Color table 25 */
333: { "COLOR26", 0xdff1B4 }, /* Color table 26 */
334: { "COLOR27", 0xdff1B6 }, /* Color table 27 */
335: { "COLOR28", 0xdff1B8 }, /* Color table 28 */
336: { "COLOR29", 0xdff1BA }, /* Color table 29 */
337: { "COLOR30", 0xdff1BC }, /* Color table 30 */
338: { "COLOR31", 0xdff1BE }, /* Color table 31 */
339: { "HTOTAL", 0xdff1C0 }, /* Highest number count in horiz line (VARBEAMEN = 1) */
340: { "HSSTOP", 0xdff1C2 }, /* Horiz line pos for HSYNC stop */
341: { "HBSTRT", 0xdff1C4 }, /* Horiz line pos for HBLANK start */
342: { "HBSTOP", 0xdff1C6 }, /* Horiz line pos for HBLANK stop */
343: { "VTOTAL", 0xdff1C8 }, /* Highest numbered vertical line (VARBEAMEN = 1) */
344: { "VSSTOP", 0xdff1CA }, /* Vert line for VBLANK start */
345: { "VBSTRT", 0xdff1CC }, /* Vert line for VBLANK start */
346: { "VBSTOP", 0xdff1CE }, /* Vert line for VBLANK stop */
347: { "SPRHSTRT", 0xdff1D0 }, /* UHRES sprite vertical start */
348: { "SPRHSTOP", 0xdff1D2 }, /* UHRES sprite vertical stop */
349: { "BPLHSTRT", 0xdff1D4 }, /* UHRES bit plane vertical stop */
350: { "BPLHSTOP", 0xdff1D6 }, /* UHRES bit plane vertical stop */
351: { "HHPOSW", 0xdff1D8 }, /* DUAL mode hires H beam counter write */
352: { "HHPOSR", 0xdff1DA }, /* DUAL mode hires H beam counter read */
353: { "BEAMCON0", 0xdff1DC }, /* Beam counter control register (SHRES,UHRES,PAL) */
354: { "HSSTRT", 0xdff1DE }, /* Horizontal sync start (VARHSY) */
355: { "VSSTRT", 0xdff1E0 }, /* Vertical sync start (VARVSY) */
356: { "HCENTER", 0xdff1E2 }, /* Horizontal pos for vsync on interlace */
357: { "DIWHIGH", 0xdff1E4 }, /* Display window upper bits for start/stop */
358: { "BPLHMOD", 0xdff1E6 }, /* UHRES bit plane modulo */
359: { "SPRHPTH", 0xdff1E8 }, /* UHRES sprite pointer (high 5 bits) */
360: { "SPRHPTL", 0xdff1EA }, /* UHRES sprite pointer (low 15 bits) */
361: { "BPLHPTH", 0xdff1EC }, /* VRam (UHRES) bitplane pointer (hi 5 bits) */
362: { "BPLHPTL", 0xdff1EE }, /* VRam (UHRES) bitplane pointer (lo 15 bits) */
363: { "RESERVED", 0xdff1F0 }, /* Reserved (forever i guess!) */
364: { "RESERVED", 0xdff1F2 }, /* Reserved (forever i guess!) */
365: { "RESERVED", 0xdff1F4 }, /* Reserved (forever i guess!) */
366: { "RESERVED", 0xdff1F6 }, /* Reserved (forever i guess!) */
367: { "RESERVED", 0xdff1F8 }, /* Reserved (forever i guess!) */
368: { "RESERVED", 0xdff1Fa }, /* Reserved (forever i guess!) */
369: { "FMODE", 0xdff1FC }, /* Fetch mode register */
370: { "NO-OP(NULL)", 0xdff1FE }, /* Can also indicate last 2 or 3 refresh
371: cycles or the restart of the COPPER after lockup.*/
372: };
373:
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