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1.1 root 1: /*
2: * UAE - The Un*x Amiga Emulator
3: *
1.1.1.3 ! root 4: * Routines for labelling amiga internals.
1.1 root 5: *
6: */
7:
8: #include "sysconfig.h"
9: #include "sysdeps.h"
1.1.1.2 root 10:
1.1 root 11: #include "memory.h"
12: #include "identify.h"
13:
14: struct mem_labels int_labels[] =
15: {
16: { "Reset:SSP", 0x0000 },
17: { "EXECBASE", 0x0004 },
18: { "BUS ERROR", 0x0008 },
19: { "ADR ERROR", 0x000C },
20: { "ILLEG OPC", 0x0010 },
21: { "DIV BY 0", 0x0014 },
22: { "CHK", 0x0018 },
23: { "TRAPV", 0x001C },
24: { "PRIVIL VIO", 0x0020 },
25: { "TRACE", 0x0024 },
26: { "LINEA EMU", 0x0028 },
27: { "LINEF EMU", 0x002C },
28: { "INT Uninit", 0x003C },
29: { "INT Unjust", 0x0060 },
30: { "Lvl 1 Int", 0x0064 },
31: { "Lvl 2 Int", 0x0068 },
32: { "Lvl 3 Int", 0x006C },
33: { "Lvl 4 Int", 0x0070 },
34: { "Lvl 5 Int", 0x0074 },
35: { "Lvl 6 Int", 0x0078 },
36: { "NMI", 0x007C },
37: { 0, 0 }
38: };
39:
40: struct mem_labels trap_labels[] =
41: {
1.1.1.2 root 42: { "TRAP 00", 0x0080 },
43: { "TRAP 01", 0x0084 },
44: { "TRAP 02", 0x0088 },
45: { "TRAP 03", 0x008C },
46: { "TRAP 04", 0x0090 },
47: { "TRAP 05", 0x0094 },
48: { "TRAP 06", 0x0098 },
49: { "TRAP 07", 0x009C },
50: { "TRAP 08", 0x00A0 },
51: { "TRAP 09", 0x00A4 },
52: { "TRAP 10", 0x00A8 },
53: { "TRAP 11", 0x00AC },
54: { "TRAP 12", 0x00B0 },
55: { "TRAP 13", 0x00B4 },
56: { "TRAP 14", 0x00B8 },
57: { "TRAP 15", 0x00BC },
1.1 root 58: { 0, 0 }
59: };
60:
61: struct mem_labels mem_labels[] =
62: {
63: { "CIAB PRA", 0xBFD000 },
64: { "CIAB PRB", 0xBFD100 },
65: { "CIAB DDRA", 0xBFD200 },
66: { "CIAB DDRB", 0xBFD300 },
67: { "CIAB TALO", 0xBFD400 },
68: { "CIAB TAHI", 0xBFD500 },
69: { "CIAB TBLO", 0xBFD600 },
70: { "CIAB TBHI", 0xBFD700 },
71: { "CIAB TDLO", 0xBFD800 },
72: { "CIAB TDMD", 0xBFD900 },
73: { "CIAB TDHI", 0xBFDA00 },
74: { "CIAB SDR", 0xBFDC00 },
75: { "CIAB ICR", 0xBFDD00 },
76: { "CIAB CRA", 0xBFDE00 },
77: { "CIAB CRB", 0xBFDF00 },
78: { "CIAA PRA", 0xBFE001 },
79: { "CIAA PRB", 0xBFE101 },
80: { "CIAA DDRA", 0xBFE201 },
81: { "CIAA DDRB", 0xBFE301 },
82: { "CIAA TALO", 0xBFE401 },
83: { "CIAA TAHI", 0xBFE501 },
84: { "CIAA TBLO", 0xBFE601 },
85: { "CIAA TBHI", 0xBFE701 },
86: { "CIAA TDLO", 0xBFE801 },
87: { "CIAA TDMD", 0xBFE901 },
88: { "CIAA TDHI", 0xBFEA01 },
89: { "CIAA SDR", 0xBFEC01 },
90: { "CIAA ICR", 0xBFED01 },
91: { "CIAA CRA", 0xBFEE01 },
92: { "CIAA CRB", 0xBFEF01 },
93: { "CLK S1", 0xDC0000 },
94: { "CLK S10", 0xDC0004 },
95: { "CLK MI1", 0xDC0008 },
96: { "CLK MI10", 0xDC000C },
97: { "CLK H1", 0xDC0010 },
98: { "CLK H10", 0xDC0014 },
99: { "CLK D1", 0xDC0018 },
100: { "CLK D10", 0xDC001C },
101: { "CLK MO1", 0xDC0020 },
102: { "CLK MO10", 0xDC0024 },
103: { "CLK Y1", 0xDC0028 },
104: { "CLK Y10", 0xDC002E },
105: { "CLK WEEK", 0xDC0030 },
106: { "CLK CD", 0xDC0034 },
107: { "CLK CE", 0xDC0038 },
108: { "CLK CF", 0xDC003C },
109: { NULL, 0 }
110: };
111:
1.1.1.3 ! root 112: /* This table was generated from the list of AGA chip names in
1.1 root 113: * AGA.guide available on aminet. It could well have errors in it. */
114:
115: struct customData custd[] =
116: {
1.1.1.2 root 117: #if 0
1.1 root 118: { "BLTDDAT", 0xdff000 }, /* Blitter dest. early read (dummy address) */
1.1.1.2 root 119: #endif
120: { "DMACONR", 0xdff002, 1, 0 }, /* Dma control (and blitter status) read */
121: { "VPOSR", 0xdff004, 1, 0 }, /* Read vert most sig. bits (and frame flop */
122: { "VHPOSR", 0xdff006, 1, 0 }, /* Read vert and horiz position of beam */
123: #if 0
1.1 root 124: { "DSKDATR", 0xdff008 }, /* Disk data early read (dummy address) */
1.1.1.2 root 125: #endif
126: { "JOY0DAT", 0xdff00A, 1, 0 }, /* Joystick-mouse 0 data (vert,horiz) */
127: { "JOT1DAT", 0xdff00C, 1, 0 }, /* Joystick-mouse 1 data (vert,horiz) */
128: { "CLXDAT", 0xdff00E, 1, 0 }, /* Collision data reg. (read and clear) */
129: { "ADKCONR", 0xdff010, 1, 0 }, /* Audio,disk control register read */
130: { "POT0DAT", 0xdff012, 1, 0 }, /* Pot counter pair 0 data (vert,horiz) */
131: { "POT1DAT", 0xdff014, 1, 0 }, /* Pot counter pair 1 data (vert,horiz) */
132: { "POTGOR", 0xdff016, 1, 0 }, /* Pot pin data read */
133: { "SERDATR", 0xdff018, 1, 0 }, /* Serial port data and status read */
134: { "DSKBYTR", 0xdff01A, 1, 0 }, /* Disk data byte and status read */
135: { "INTENAR", 0xdff01C, 1, 0 }, /* Interrupt enable bits read */
136: { "INTREQR", 0xdff01E, 1, 0 }, /* Interrupt request bits read */
137: { "DSKPTH", 0xdff020, 2, 1 }, /* Disk pointer (high 5 bits) */
138: { "DSKPTL", 0xdff022, 2, 2 }, /* Disk pointer (low 15 bits) */
139: { "DSKLEN", 0xdff024, 2, 0 }, /* Disk lentgh */
140: #if 0
1.1 root 141: { "DSKDAT", 0xdff026 }, /* Disk DMA data write */
142: { "REFPTR", 0xdff028 }, /* Refresh pointer */
1.1.1.2 root 143: #endif
144: { "VPOSW", 0xdff02A, 2, 0 }, /* Write vert most sig. bits(and frame flop) */
145: { "VHPOSW", 0xdff02C, 2, 0 }, /* Write vert and horiz pos of beam */
146: { "COPCON", 0xdff02e, 2, 0 }, /* Coprocessor control reg (CDANG) */
147: { "SERDAT", 0xdff030, 2, 0 }, /* Serial port data and stop bits write */
148: { "SERPER", 0xdff032, 2, 0 }, /* Serial port period and control */
149: { "POTGO", 0xdff034, 2, 0 }, /* Pot count start,pot pin drive enable data */
150: { "JOYTEST", 0xdff036, 2, 0 }, /* Write to all 4 joystick-mouse counters at once */
151: { "STREQU", 0xdff038, 2, 0 }, /* Strobe for horiz sync with VB and EQU */
152: { "STRVBL", 0xdff03A, 2, 0 }, /* Strobe for horiz sync with VB (vert blank) */
153: { "STRHOR", 0xdff03C, 2, 0 }, /* Strobe for horiz sync */
154: { "STRLONG", 0xdff03E, 2, 0 }, /* Strobe for identification of long horiz line */
155: { "BLTCON0", 0xdff040, 2, 0 }, /* Blitter control reg 0 */
156: { "BLTCON1", 0xdff042, 2, 0 }, /* Blitter control reg 1 */
157: { "BLTAFWM", 0xdff044, 2, 0 }, /* Blitter first word mask for source A */
158: { "BLTALWM", 0xdff046, 2, 0 }, /* Blitter last word mask for source A */
159: { "BLTCPTH", 0xdff048, 2, 1 }, /* Blitter pointer to source C (high 5 bits) */
160: { "BLTCPTL", 0xdff04A, 2, 2 }, /* Blitter pointer to source C (low 15 bits) */
161: { "BLTBPTH", 0xdff04C, 2, 1 }, /* Blitter pointer to source B (high 5 bits) */
162: { "BLTBPTL", 0xdff04E, 2, 2 }, /* Blitter pointer to source B (low 15 bits) */
163: { "BLTAPTH", 0xdff050, 2, 1 }, /* Blitter pointer to source A (high 5 bits) */
164: { "BLTAPTL", 0xdff052, 2, 2 }, /* Blitter pointer to source A (low 15 bits) */
165: { "BPTDPTH", 0xdff054, 2, 1 }, /* Blitter pointer to destn D (high 5 bits) */
166: { "BLTDPTL", 0xdff056, 2, 2 }, /* Blitter pointer to destn D (low 15 bits) */
167: { "BLTSIZE", 0xdff058, 2, 0 }, /* Blitter start and size (win/width,height) */
168: { "BLTCON0L", 0xdff05A, 2, 0 }, /* Blitter control 0 lower 8 bits (minterms) */
169: { "BLTSIZV", 0xdff05C, 2, 0 }, /* Blitter V size (for 15 bit vert size) */
170: { "BLTSIZH", 0xdff05E, 2, 0 }, /* Blitter H size & start (for 11 bit H size) */
171: { "BLTCMOD", 0xdff060, 2, 0 }, /* Blitter modulo for source C */
172: { "BLTBMOD", 0xdff062, 2, 0 }, /* Blitter modulo for source B */
173: { "BLTAMOD", 0xdff064, 2, 0 }, /* Blitter modulo for source A */
174: { "BLTDMOD", 0xdff066, 2, 0 }, /* Blitter modulo for destn D */
175: #if 0
1.1 root 176: { "Unknown", 0xdff068 }, /* Unknown or Unused */
177: { "Unknown", 0xdff06a }, /* Unknown or Unused */
178: { "Unknown", 0xdff06c }, /* Unknown or Unused */
179: { "Unknown", 0xdff06e }, /* Unknown or Unused */
1.1.1.2 root 180: #endif
181: { "BLTCDAT", 0xdff070, 2, 0 }, /* Blitter source C data reg */
182: { "BLTBDAT", 0xdff072, 2, 0 }, /* Blitter source B data reg */
183: { "BLTADAT", 0xdff074, 2, 0 }, /* Blitter source A data reg */
184: { "BLTDDAT", 0xdff076, 2, 0 }, /* Blitter destination reg */
185: #if 0
1.1 root 186: { "SPRHDAT", 0xdff078 }, /* Ext logic UHRES sprite pointer and data identifier */
187: { "BPLHDAT", 0xdff07A }, /* Ext logic UHRES bit plane identifier */
1.1.1.2 root 188: #endif
189: { "LISAID", 0xdff07C, 1, 0 }, /* Chip revision level for Denise/Lisa */
190: { "DSKSYNC", 0xdff07E, 2, 0 }, /* Disk sync pattern reg for disk read */
191: { "COP1LCH", 0xdff080, 2, 1 }, /* Coprocessor first location reg (high 5 bits) */
192: { "COP1LCL", 0xdff082, 2, 2 }, /* Coprocessor first location reg (low 15 bits) */
193: { "COP2LCH", 0xdff084, 2, 1 }, /* Coprocessor second reg (high 5 bits) */
194: { "COP2LCL", 0xdff086, 2, 2 }, /* Coprocessor second reg (low 15 bits) */
195: { "COPJMP1", 0xdff088, 2, 0 }, /* Coprocessor restart at first location */
196: { "COPJMP2", 0xdff08A, 2, 0 }, /* Coprocessor restart at second location */
197: #if 0
1.1 root 198: { "COPINS", 0xdff08C }, /* Coprocessor inst fetch identify */
1.1.1.2 root 199: #endif
200: { "DIWSTRT", 0xdff08E, 2, 0 }, /* Display window start (upper left vert-hor pos) */
201: { "DIWSTOP", 0xdff090, 2, 0 }, /* Display window stop (lower right vert-hor pos) */
202: { "DDFSTRT", 0xdff092, 2, 0 }, /* Display bit plane data fetch start.hor pos */
203: { "DDFSTOP", 0xdff094, 2, 0 }, /* Display bit plane data fetch stop.hor pos */
204: { "DMACON", 0xdff096, 2, 0 }, /* DMA control write (clear or set) */
205: { "CLXCON", 0xdff098, 2, 0 }, /* Collision control */
206: { "INTENA", 0xdff09A, 2, 0 }, /* Interrupt enable bits (clear or set bits) */
207: { "INTREQ", 0xdff09C, 2, 0 }, /* Interrupt request bits (clear or set bits) */
208: { "ADKCON", 0xdff09E, 2, 0 }, /* Audio,disk,UART,control */
209: { "AUD0LCH", 0xdff0A0, 2, 1 }, /* Audio channel 0 location (high 5 bits) */
210: { "AUD0LCL", 0xdff0A2, 2, 2 }, /* Audio channel 0 location (low 15 bits) */
211: { "AUD0LEN", 0xdff0A4, 2, 0 }, /* Audio channel 0 lentgh */
212: { "AUD0PER", 0xdff0A6, 2, 0 }, /* Audio channel 0 period */
213: { "AUD0VOL", 0xdff0A8, 2, 0 }, /* Audio channel 0 volume */
214: { "AUD0DAT", 0xdff0AA, 2, 0 }, /* Audio channel 0 data */
215: #if 0
1.1 root 216: { "Unknown", 0xdff0AC }, /* Unknown or Unused */
217: { "Unknown", 0xdff0AE }, /* Unknown or Unused */
1.1.1.2 root 218: #endif
219: { "AUD1LCH", 0xdff0B0, 2, 0 }, /* Audio channel 1 location (high 5 bits) */
220: { "AUD1LCL", 0xdff0B2, 2, 0 }, /* Audio channel 1 location (low 15 bits) */
221: { "AUD1LEN", 0xdff0B4, 2, 0 }, /* Audio channel 1 lentgh */
222: { "AUD1PER", 0xdff0B6, 2, 0 }, /* Audio channel 1 period */
223: { "AUD1VOL", 0xdff0B8, 2, 0 }, /* Audio channel 1 volume */
224: { "AUD1DAT", 0xdff0BA, 2, 0 }, /* Audio channel 1 data */
225: #if 0
1.1 root 226: { "Unknown", 0xdff0BC }, /* Unknown or Unused */
227: { "Unknown", 0xdff0BE }, /* Unknown or Unused */
1.1.1.2 root 228: #endif
229: { "AUD2LCH", 0xdff0C0, 2, 0 }, /* Audio channel 2 location (high 5 bits) */
230: { "AUD2LCL", 0xdff0C2, 2, 0 }, /* Audio channel 2 location (low 15 bits) */
231: { "AUD2LEN", 0xdff0C4, 2, 0 }, /* Audio channel 2 lentgh */
232: { "AUD2PER", 0xdff0C6, 2, 0 }, /* Audio channel 2 period */
233: { "AUD2VOL", 0xdff0C8, 2, 0 }, /* Audio channel 2 volume */
234: { "AUD2DAT", 0xdff0CA, 2, 0 }, /* Audio channel 2 data */
235: #if 0
1.1 root 236: { "Unknown", 0xdff0CC }, /* Unknown or Unused */
237: { "Unknown", 0xdff0CE }, /* Unknown or Unused */
1.1.1.2 root 238: #endif
239: { "AUD3LCH", 0xdff0D0, 2, 0 }, /* Audio channel 3 location (high 5 bits) */
240: { "AUD3LCL", 0xdff0D2, 2, 0 }, /* Audio channel 3 location (low 15 bits) */
241: { "AUD3LEN", 0xdff0D4, 2, 0 }, /* Audio channel 3 lentgh */
242: { "AUD3PER", 0xdff0D6, 2, 0 }, /* Audio channel 3 period */
243: { "AUD3VOL", 0xdff0D8, 2, 0 }, /* Audio channel 3 volume */
244: { "AUD3DAT", 0xdff0DA, 2, 0 }, /* Audio channel 3 data */
245: #if 0
1.1 root 246: { "Unknown", 0xdff0DC }, /* Unknown or Unused */
247: { "Unknown", 0xdff0DE }, /* Unknown or Unused */
1.1.1.2 root 248: #endif
249: { "BPL1PTH", 0xdff0E0, 2 }, /* Bit plane pointer 1 (high 5 bits) */
250: { "BPL1PTL", 0xdff0E2, 2 }, /* Bit plane pointer 1 (low 15 bits) */
251: { "BPL2PTH", 0xdff0E4, 2 }, /* Bit plane pointer 2 (high 5 bits) */
252: { "BPL2PTL", 0xdff0E6, 2 }, /* Bit plane pointer 2 (low 15 bits) */
253: { "BPL3PTH", 0xdff0E8, 2 }, /* Bit plane pointer 3 (high 5 bits) */
254: { "BPL3PTL", 0xdff0EA, 2 }, /* Bit plane pointer 3 (low 15 bits) */
255: { "BPL4PTH", 0xdff0EC, 2 }, /* Bit plane pointer 4 (high 5 bits) */
256: { "BPL4PTL", 0xdff0EE, 2 }, /* Bit plane pointer 4 (low 15 bits) */
257: { "BPL5PTH", 0xdff0F0, 2 }, /* Bit plane pointer 5 (high 5 bits) */
258: { "BPL5PTL", 0xdff0F2, 2 }, /* Bit plane pointer 5 (low 15 bits) */
259: { "BPL6PTH", 0xdff0F4, 2 }, /* Bit plane pointer 6 (high 5 bits) */
260: { "BPL6PTL", 0xdff0F6, 2 }, /* Bit plane pointer 6 (low 15 bits) */
261: { "BPL7PTH", 0xdff0F8, 2 }, /* Bit plane pointer 7 (high 5 bits) */
262: { "BPL7PTL", 0xdff0FA, 2 }, /* Bit plane pointer 7 (low 15 bits) */
263: { "BPL8PTH", 0xdff0FC, 2 }, /* Bit plane pointer 8 (high 5 bits) */
264: { "BPL8PTL", 0xdff0FE, 2 }, /* Bit plane pointer 8 (low 15 bits) */
265: { "BPLCON0", 0xdff100, 2 }, /* Bit plane control reg (misc control bits) */
266: { "BPLCON1", 0xdff102, 2 }, /* Bit plane control reg (scroll val PF1,PF2) */
267: { "BPLCON2", 0xdff104, 2 }, /* Bit plane control reg (priority control) */
268: { "BPLCON3", 0xdff106, 2 }, /* Bit plane control reg (enhanced features) */
269: { "BPL1MOD", 0xdff108, 2 }, /* Bit plane modulo (odd planes,or active- fetch lines if bitplane scan-doubling is enabled */
270: { "BPL2MOD", 0xdff10A, 2 }, /* Bit plane modulo (even planes or inactive- fetch lines if bitplane scan-doubling is enabled */
271: { "BPLCON4", 0xdff10C, 2 }, /* Bit plane control reg (bitplane and sprite masks) */
272: { "CLXCON2", 0xdff10e, 2 }, /* Extended collision control reg */
273: { "BPL1DAT", 0xdff110, 2 }, /* Bit plane 1 data (parallel to serial con- vert) */
274: { "BPL2DAT", 0xdff112, 2 }, /* Bit plane 2 data (parallel to serial con- vert) */
275: { "BPL3DAT", 0xdff114, 2 }, /* Bit plane 3 data (parallel to serial con- vert) */
276: { "BPL4DAT", 0xdff116, 2 }, /* Bit plane 4 data (parallel to serial con- vert) */
277: { "BPL5DAT", 0xdff118, 2 }, /* Bit plane 5 data (parallel to serial con- vert) */
278: { "BPL6DAT", 0xdff11a, 2 }, /* Bit plane 6 data (parallel to serial con- vert) */
279: { "BPL7DAT", 0xdff11c, 2 }, /* Bit plane 7 data (parallel to serial con- vert) */
280: { "BPL8DAT", 0xdff11e, 2 }, /* Bit plane 8 data (parallel to serial con- vert) */
281: { "SPR0PTH", 0xdff120, 2 }, /* Sprite 0 pointer (high 5 bits) */
282: { "SPR0PTL", 0xdff122, 2 }, /* Sprite 0 pointer (low 15 bits) */
283: { "SPR1PTH", 0xdff124, 2 }, /* Sprite 1 pointer (high 5 bits) */
284: { "SPR1PTL", 0xdff126, 2 }, /* Sprite 1 pointer (low 15 bits) */
285: { "SPR2PTH", 0xdff128, 2 }, /* Sprite 2 pointer (high 5 bits) */
286: { "SPR2PTL", 0xdff12A, 2 }, /* Sprite 2 pointer (low 15 bits) */
287: { "SPR3PTH", 0xdff12C, 2 }, /* Sprite 3 pointer (high 5 bits) */
288: { "SPR3PTL", 0xdff12E, 2 }, /* Sprite 3 pointer (low 15 bits) */
289: { "SPR4PTH", 0xdff130, 2 }, /* Sprite 4 pointer (high 5 bits) */
290: { "SPR4PTL", 0xdff132, 2 }, /* Sprite 4 pointer (low 15 bits) */
291: { "SPR5PTH", 0xdff134, 2 }, /* Sprite 5 pointer (high 5 bits) */
292: { "SPR5PTL", 0xdff136, 2 }, /* Sprite 5 pointer (low 15 bits) */
293: { "SPR6PTH", 0xdff138, 2 }, /* Sprite 6 pointer (high 5 bits) */
294: { "SPR6PTL", 0xdff13A, 2 }, /* Sprite 6 pointer (low 15 bits) */
295: { "SPR7PTH", 0xdff13C, 2 }, /* Sprite 7 pointer (high 5 bits) */
296: { "SPR7PTL", 0xdff13E, 2 }, /* Sprite 7 pointer (low 15 bits) */
297: { "SPR0POS", 0xdff140, 2 }, /* Sprite 0 vert-horiz start pos data */
298: { "SPR0CTL", 0xdff142, 2 }, /* Sprite 0 position and control data */
299: { "SPR0DATA", 0xdff144, 2 }, /* Sprite 0 image data register A */
300: { "SPR0DATB", 0xdff146, 2 }, /* Sprite 0 image data register B */
301: { "SPR1POS", 0xdff148, 2 }, /* Sprite 1 vert-horiz start pos data */
302: { "SPR1CTL", 0xdff14A, 2 }, /* Sprite 1 position and control data */
303: { "SPR1DATA", 0xdff14C, 2 }, /* Sprite 1 image data register A */
304: { "SPR1DATB", 0xdff14E, 2 }, /* Sprite 1 image data register B */
305: { "SPR2POS", 0xdff150, 2 }, /* Sprite 2 vert-horiz start pos data */
306: { "SPR2CTL", 0xdff152, 2 }, /* Sprite 2 position and control data */
307: { "SPR2DATA", 0xdff154, 2 }, /* Sprite 2 image data register A */
308: { "SPR2DATB", 0xdff156, 2 }, /* Sprite 2 image data register B */
309: { "SPR3POS", 0xdff158, 2 }, /* Sprite 3 vert-horiz start pos data */
310: { "SPR3CTL", 0xdff15A, 2 }, /* Sprite 3 position and control data */
311: { "SPR3DATA", 0xdff15C, 2 }, /* Sprite 3 image data register A */
312: { "SPR3DATB", 0xdff15E, 2 }, /* Sprite 3 image data register B */
313: { "SPR4POS", 0xdff160, 2 }, /* Sprite 4 vert-horiz start pos data */
314: { "SPR4CTL", 0xdff162, 2 }, /* Sprite 4 position and control data */
315: { "SPR4DATA", 0xdff164, 2 }, /* Sprite 4 image data register A */
316: { "SPR4DATB", 0xdff166, 2 }, /* Sprite 4 image data register B */
317: { "SPR5POS", 0xdff168, 2 }, /* Sprite 5 vert-horiz start pos data */
318: { "SPR5CTL", 0xdff16A, 2 }, /* Sprite 5 position and control data */
319: { "SPR5DATA", 0xdff16C, 2 }, /* Sprite 5 image data register A */
320: { "SPR5DATB", 0xdff16E, 2 }, /* Sprite 5 image data register B */
321: { "SPR6POS", 0xdff170, 2 }, /* Sprite 6 vert-horiz start pos data */
322: { "SPR6CTL", 0xdff172, 2 }, /* Sprite 6 position and control data */
323: { "SPR6DATA", 0xdff174, 2 }, /* Sprite 6 image data register A */
324: { "SPR6DATB", 0xdff176, 2 }, /* Sprite 6 image data register B */
325: { "SPR7POS", 0xdff178, 2 }, /* Sprite 7 vert-horiz start pos data */
326: { "SPR7CTL", 0xdff17A, 2 }, /* Sprite 7 position and control data */
327: { "SPR7DATA", 0xdff17C, 2 }, /* Sprite 7 image data register A */
328: { "SPR7DATB", 0xdff17E, 2 }, /* Sprite 7 image data register B */
329: { "COLOR00", 0xdff180, 2 }, /* Color table 00 */
330: { "COLOR01", 0xdff182, 2 }, /* Color table 01 */
331: { "COLOR02", 0xdff184, 2 }, /* Color table 02 */
332: { "COLOR03", 0xdff186, 2 }, /* Color table 03 */
333: { "COLOR04", 0xdff188, 2 }, /* Color table 04 */
334: { "COLOR05", 0xdff18A, 2 }, /* Color table 05 */
335: { "COLOR06", 0xdff18C, 2 }, /* Color table 06 */
336: { "COLOR07", 0xdff18E, 2 }, /* Color table 07 */
337: { "COLOR08", 0xdff190, 2 }, /* Color table 08 */
338: { "COLOR09", 0xdff192, 2 }, /* Color table 09 */
339: { "COLOR10", 0xdff194, 2 }, /* Color table 10 */
340: { "COLOR11", 0xdff196, 2 }, /* Color table 11 */
341: { "COLOR12", 0xdff198, 2 }, /* Color table 12 */
342: { "COLOR13", 0xdff19A, 2 }, /* Color table 13 */
343: { "COLOR14", 0xdff19C, 2 }, /* Color table 14 */
344: { "COLOR15", 0xdff19E, 2 }, /* Color table 15 */
345: { "COLOR16", 0xdff1A0, 2 }, /* Color table 16 */
346: { "COLOR17", 0xdff1A2, 2 }, /* Color table 17 */
347: { "COLOR18", 0xdff1A4, 2 }, /* Color table 18 */
348: { "COLOR19", 0xdff1A6, 2 }, /* Color table 19 */
349: { "COLOR20", 0xdff1A8, 2 }, /* Color table 20 */
350: { "COLOR21", 0xdff1AA, 2 }, /* Color table 21 */
351: { "COLOR22", 0xdff1AC, 2 }, /* Color table 22 */
352: { "COLOR23", 0xdff1AE, 2 }, /* Color table 23 */
353: { "COLOR24", 0xdff1B0, 2 }, /* Color table 24 */
354: { "COLOR25", 0xdff1B2, 2 }, /* Color table 25 */
355: { "COLOR26", 0xdff1B4, 2 }, /* Color table 26 */
356: { "COLOR27", 0xdff1B6, 2 }, /* Color table 27 */
357: { "COLOR28", 0xdff1B8, 2 }, /* Color table 28 */
358: { "COLOR29", 0xdff1BA, 2 }, /* Color table 29 */
359: { "COLOR30", 0xdff1BC, 2 }, /* Color table 30 */
360: { "COLOR31", 0xdff1BE, 2 }, /* Color table 31 */
361: { "HTOTAL", 0xdff1C0, 2 }, /* Highest number count in horiz line (VARBEAMEN = 1) */
362: { "HSSTOP", 0xdff1C2, 2 }, /* Horiz line pos for HSYNC stop */
363: { "HBSTRT", 0xdff1C4, 2 }, /* Horiz line pos for HBLANK start */
364: { "HBSTOP", 0xdff1C6, 2 }, /* Horiz line pos for HBLANK stop */
365: { "VTOTAL", 0xdff1C8, 2 }, /* Highest numbered vertical line (VARBEAMEN = 1) */
366: { "VSSTOP", 0xdff1CA, 2 }, /* Vert line for VBLANK start */
367: { "VBSTRT", 0xdff1CC, 2 }, /* Vert line for VBLANK start */
368: { "VBSTOP", 0xdff1CE, 2 }, /* Vert line for VBLANK stop */
369: #if 0
1.1 root 370: { "SPRHSTRT", 0xdff1D0 }, /* UHRES sprite vertical start */
371: { "SPRHSTOP", 0xdff1D2 }, /* UHRES sprite vertical stop */
372: { "BPLHSTRT", 0xdff1D4 }, /* UHRES bit plane vertical stop */
373: { "BPLHSTOP", 0xdff1D6 }, /* UHRES bit plane vertical stop */
374: { "HHPOSW", 0xdff1D8 }, /* DUAL mode hires H beam counter write */
375: { "HHPOSR", 0xdff1DA }, /* DUAL mode hires H beam counter read */
1.1.1.2 root 376: #endif
377: { "BEAMCON0", 0xdff1DC, 2 }, /* Beam counter control register (SHRES,UHRES,PAL) */
378: { "HSSTRT", 0xdff1DE, 2 }, /* Horizontal sync start (VARHSY) */
379: { "VSSTRT", 0xdff1E0, 2 }, /* Vertical sync start (VARVSY) */
380: { "HCENTER", 0xdff1E2, 2 }, /* Horizontal pos for vsync on interlace */
381: { "DIWHIGH", 0xdff1E4, 2 }, /* Display window upper bits for start/stop */
382: #if 0
1.1 root 383: { "BPLHMOD", 0xdff1E6 }, /* UHRES bit plane modulo */
384: { "SPRHPTH", 0xdff1E8 }, /* UHRES sprite pointer (high 5 bits) */
385: { "SPRHPTL", 0xdff1EA }, /* UHRES sprite pointer (low 15 bits) */
386: { "BPLHPTH", 0xdff1EC }, /* VRam (UHRES) bitplane pointer (hi 5 bits) */
387: { "BPLHPTL", 0xdff1EE }, /* VRam (UHRES) bitplane pointer (lo 15 bits) */
388: { "RESERVED", 0xdff1F0 }, /* Reserved (forever i guess!) */
389: { "RESERVED", 0xdff1F2 }, /* Reserved (forever i guess!) */
390: { "RESERVED", 0xdff1F4 }, /* Reserved (forever i guess!) */
391: { "RESERVED", 0xdff1F6 }, /* Reserved (forever i guess!) */
392: { "RESERVED", 0xdff1F8 }, /* Reserved (forever i guess!) */
393: { "RESERVED", 0xdff1Fa }, /* Reserved (forever i guess!) */
1.1.1.2 root 394: #endif
395: { "FMODE", 0xdff1FC, 2 }, /* Fetch mode register */
396: #if 0
1.1 root 397: { "NO-OP(NULL)", 0xdff1FE }, /* Can also indicate last 2 or 3 refresh
398: cycles or the restart of the COPPER after lockup.*/
1.1.1.2 root 399: #endif
1.1 root 400: };
401:
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