--- uae/src/newcpu.c	2018/04/24 16:42:08	1.1.1.4
+++ uae/src/newcpu.c	2018/04/24 16:44:48	1.1.1.5
@@ -220,7 +220,27 @@ void init_m68k (void)
 	}
     }
 #endif
-    write_log ("Building CPU table... ");
+    write_log ("Building CPU table for configuration: 68");
+    if (currprefs.address_space_24 && currprefs.cpu_level > 1)
+        write_log ("EC");
+    switch (currprefs.cpu_level) {
+     case 1:
+        write_log ("010");
+        break;
+     case 2:
+        write_log ("020");
+        break;
+     case 3:
+        write_log ("020/881");
+        break;
+     default:
+        write_log ("000");
+        break;
+    }
+    if (currprefs.cpu_compatible)
+        write_log (" (compatible mode)");
+    write_log ("\n");
+    
     read_table68k ();
     do_merges ();
 
@@ -537,6 +557,58 @@ static int verify_ea (int reg, amodes mo
     return 0;
 }
 
+uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
+{
+    int reg = (dp >> 12) & 15;
+    uae_s32 regd = regs.regs[reg];
+    if ((dp & 0x800) == 0)
+	regd = (uae_s32)(uae_s16)regd;
+    regd <<= (dp >> 9) & 3;
+    if (dp & 0x100) {
+	uae_s32 outer = 0;
+	if (dp & 0x80) base = 0;
+	if (dp & 0x40) regd = 0;
+
+	if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
+	if ((dp & 0x30) == 0x30) base += next_ilong();
+
+	if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
+	if ((dp & 0x3) == 0x3) outer = next_ilong();
+
+	if ((dp & 0x4) == 0) base += regd;
+	if (dp & 0x3) base = get_long (base);
+	if (dp & 0x4) base += regd;
+
+	return base + outer;
+    } else {
+	return base + (uae_s32)((uae_s8)dp) + regd;
+    }
+}
+
+uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
+{
+    int reg = (dp >> 12) & 15;
+    uae_s32 regd = regs.regs[reg];
+#if 1
+    if ((dp & 0x800) == 0)
+	regd = (uae_s32)(uae_s16)regd;
+    return base + (uae_s8)dp + regd;
+#else
+    /* Branch-free code... benchmark this again now that
+     * things are no longer inline.  */
+    uae_s32 regd16;
+    uae_u32 mask;
+    mask = ((dp & 0x800) >> 11) - 1;
+    regd16 = (uae_s32)(uae_s16)regd;
+    regd16 &= mask;
+    mask = ~mask;
+    base += (uae_s8)dp;
+    regd &= mask;
+    regd |= regd16;
+    return base + regd;
+#endif
+}
+
 void MakeSR (void)
 {
 #if 0