--- uae/src/newcpu.c 2018/04/24 16:42:08 1.1.1.4 +++ uae/src/newcpu.c 2018/04/24 16:50:04 1.1.1.9 @@ -13,7 +13,6 @@ #include "options.h" #include "events.h" #include "uae.h" -#include "machdep/m68k.h" #include "memory.h" #include "custom.h" #include "readcpu.h" @@ -98,20 +97,11 @@ void dump_counts (void) int broken_in; -static __inline__ unsigned int cft_map (unsigned int f) -{ -#ifndef HAVE_GET_WORD_UNSWAPPED - return f; -#else - return ((f >> 8) & 255) | ((f & 255) << 8); -#endif -} - static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM; static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode) { - op_illg (cft_map (opcode)); + op_illg (opcode); return 4; } @@ -129,10 +119,10 @@ static void build_cpufunctbl (void) currprefs.cpu_level, currprefs.cpu_compatible, currprefs.address_space_24); for (opcode = 0; opcode < 65536; opcode++) - cpufunctbl[cft_map (opcode)] = op_illg_1; + cpufunctbl[opcode] = op_illg_1; for (i = 0; tbl[i].handler != NULL; i++) { if (! tbl[i].specific) - cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler; + cpufunctbl[tbl[i].opcode] = tbl[i].handler; } for (opcode = 0; opcode < 65536; opcode++) { cpuop_func *f; @@ -141,15 +131,15 @@ static void build_cpufunctbl (void) continue; if (table68k[opcode].handler != -1) { - f = cpufunctbl[cft_map (table68k[opcode].handler)]; + f = cpufunctbl[table68k[opcode].handler]; if (f == op_illg_1) abort(); - cpufunctbl[cft_map (opcode)] = f; + cpufunctbl[opcode] = f; } } for (i = 0; tbl[i].handler != NULL; i++) { if (tbl[i].specific) - cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler; + cpufunctbl[tbl[i].opcode] = tbl[i].handler; } } @@ -200,8 +190,8 @@ void init_m68k (void) for (j = 7 ; j >= 0 ; j--) { if (i & (1 << j)) break; } - fpp_movem_index1[i] = j; - fpp_movem_index2[i] = 7-j; + fpp_movem_index1[i] = 7-j; + fpp_movem_index2[i] = j; fpp_movem_next[i] = i & (~(1 << j)); } #if COUNT_INSTRS @@ -220,7 +210,27 @@ void init_m68k (void) } } #endif - write_log ("Building CPU table... "); + write_log ("Building CPU table for configuration: 68"); + if (currprefs.address_space_24 && currprefs.cpu_level > 1) + write_log ("EC"); + switch (currprefs.cpu_level) { + case 1: + write_log ("010"); + break; + case 2: + write_log ("020"); + break; + case 3: + write_log ("020/881"); + break; + default: + write_log ("000"); + break; + } + if (currprefs.cpu_compatible) + write_log (" (compatible mode)"); + write_log ("\n"); + read_table68k (); do_merges (); @@ -270,7 +280,7 @@ uae_s32 ShowEA (int reg, amodes mode, wo disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; addr = m68k_areg(regs,reg) + (uae_s16)disp16; sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff, - (long unsigned int)addr); + (unsigned long)addr); break; case Ad8r: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; @@ -303,20 +313,20 @@ uae_s32 ShowEA (int reg, amodes mode, wo dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3), disp,outer, - (long unsigned int)addr); + (unsigned long)addr); } else { addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg; sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg, dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3), disp8, - (long unsigned int)addr); + (unsigned long)addr); } break; case PC16: addr = m68k_getpc () + m68kpc_offset; disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; addr += (uae_s16)disp16; - sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(long unsigned int)addr); + sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr); break; case PC8r: addr = m68k_getpc () + m68kpc_offset; @@ -350,20 +360,20 @@ uae_s32 ShowEA (int reg, amodes mode, wo dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3), disp,outer, - (long unsigned int)addr); + (unsigned long)addr); } else { addr += (uae_s32)((uae_s8)disp8) + dispreg; sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3), - disp8, (long unsigned int)addr); + disp8, (unsigned long)addr); } break; case absw: - sprintf (buffer,"$%08lx", (long unsigned int)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset)); + sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset)); m68kpc_offset += 2; break; case absl: - sprintf (buffer,"$%08lx", (long unsigned int)get_ilong_1 (m68kpc_offset)); + sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset)); m68kpc_offset += 4; break; case imm: @@ -377,7 +387,7 @@ uae_s32 ShowEA (int reg, amodes mode, wo m68kpc_offset += 2; break; case sz_long: - sprintf (buffer,"#$%08lx", (long unsigned int)(get_ilong_1 (m68kpc_offset))); + sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset))); m68kpc_offset += 4; break; default: @@ -397,11 +407,11 @@ uae_s32 ShowEA (int reg, amodes mode, wo case imm2: offset = (uae_s32)get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; - sprintf (buffer,"#$%08lx", (long unsigned int)offset); + sprintf (buffer,"#$%08lx", (unsigned long)offset); break; case immi: offset = (uae_s32)(uae_s8)(reg & 0xff); - sprintf (buffer,"#$%08lx", (long unsigned int)offset); + sprintf (buffer,"#$%08lx", (unsigned long)offset); break; default: break; @@ -537,6 +547,58 @@ static int verify_ea (int reg, amodes mo return 0; } +uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp) +{ + int reg = (dp >> 12) & 15; + uae_s32 regd = regs.regs[reg]; + if ((dp & 0x800) == 0) + regd = (uae_s32)(uae_s16)regd; + regd <<= (dp >> 9) & 3; + if (dp & 0x100) { + uae_s32 outer = 0; + if (dp & 0x80) base = 0; + if (dp & 0x40) regd = 0; + + if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword(); + if ((dp & 0x30) == 0x30) base += next_ilong(); + + if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword(); + if ((dp & 0x3) == 0x3) outer = next_ilong(); + + if ((dp & 0x4) == 0) base += regd; + if (dp & 0x3) base = get_long (base); + if (dp & 0x4) base += regd; + + return base + outer; + } else { + return base + (uae_s32)((uae_s8)dp) + regd; + } +} + +uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp) +{ + int reg = (dp >> 12) & 15; + uae_s32 regd = regs.regs[reg]; +#if 1 + if ((dp & 0x800) == 0) + regd = (uae_s32)(uae_s16)regd; + return base + (uae_s8)dp + regd; +#else + /* Branch-free code... benchmark this again now that + * things are no longer inline. */ + uae_s32 regd16; + uae_u32 mask; + mask = ((dp & 0x800) >> 11) - 1; + regd16 = (uae_s32)(uae_s16)regd; + regd16 &= mask; + mask = ~mask; + base += (uae_s8)dp; + regd &= mask; + regd |= regd16; + return base + regd; +#endif +} + void MakeSR (void) { #if 0 @@ -552,8 +614,8 @@ void MakeSR (void) #endif regs.sr = ((regs.t1 << 15) | (regs.t0 << 14) | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8) - | (XFLG << 4) | (NFLG << 3) | (ZFLG << 2) | (VFLG << 1) - | CFLG); + | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1) + | GET_CFLG); } void MakeFromSR (void) @@ -566,11 +628,11 @@ void MakeFromSR (void) regs.s = (regs.sr >> 13) & 1; regs.m = (regs.sr >> 12) & 1; regs.intmask = (regs.sr >> 8) & 7; - XFLG = (regs.sr >> 4) & 1; - NFLG = (regs.sr >> 3) & 1; - ZFLG = (regs.sr >> 2) & 1; - VFLG = (regs.sr >> 1) & 1; - CFLG = regs.sr & 1; + SET_XFLG ((regs.sr >> 4) & 1); + SET_NFLG ((regs.sr >> 3) & 1); + SET_ZFLG ((regs.sr >> 2) & 1); + SET_VFLG ((regs.sr >> 1) & 1); + SET_CFLG (regs.sr & 1); if (currprefs.cpu_level >= 2) { if (olds != regs.s) { if (olds) { @@ -691,11 +753,12 @@ static void Interrupt(int nr) static int caar, cacr; -void m68k_move2c (int regno, uae_u32 *regp) +int m68k_move2c (int regno, uae_u32 *regp) { - if (currprefs.cpu_level == 1 && (regno & 0x7FF) > 1) + if (currprefs.cpu_level == 1 && (regno & 0x7FF) > 1) { op_illg (0x4E7B); - else + return 0; + } else switch (regno) { case 0: regs.sfc = *regp & 7; break; case 1: regs.dfc = *regp & 7; break; @@ -707,15 +770,17 @@ void m68k_move2c (int regno, uae_u32 *re case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break; default: op_illg (0x4E7B); - break; + return 0; } + return 1; } -void m68k_movec2 (int regno, uae_u32 *regp) +int m68k_movec2 (int regno, uae_u32 *regp) { - if (currprefs.cpu_level == 1 && (regno & 0x7FF) > 1) + if (currprefs.cpu_level == 1 && (regno & 0x7FF) > 1) { op_illg (0x4E7A); - else + return 0; + } else switch (regno) { case 0: *regp = regs.sfc; break; case 1: *regp = regs.dfc; break; @@ -727,11 +792,12 @@ void m68k_movec2 (int regno, uae_u32 *re case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break; default: op_illg (0x4E7A); - break; + return 0; } + return 1; } -static __inline__ int +STATIC_INLINE int div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 div, uae_u32 *quot, uae_u32 *rem) { uae_u32 q = 0, cbit = 0; @@ -777,13 +843,15 @@ void m68k_divl (uae_u32 opcode, uae_u32 if ((quot & UVAL64(0xffffffff80000000)) != 0 && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000)) { - VFLG = NFLG = 1; - CFLG = 0; + SET_VFLG (1); + SET_NFLG (1); + SET_CFLG (0); } else { if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem; - VFLG = CFLG = 0; - ZFLG = ((uae_s32)quot) == 0; - NFLG = ((uae_s32)quot) < 0; + SET_VFLG (0); + SET_CFLG (0); + SET_ZFLG (((uae_s32)quot) == 0); + SET_NFLG (((uae_s32)quot) < 0); m68k_dreg(regs, extra & 7) = rem; m68k_dreg(regs, (extra >> 12) & 7) = quot; } @@ -799,12 +867,14 @@ void m68k_divl (uae_u32 opcode, uae_u32 rem = a % (uae_u64)src; quot = a / (uae_u64)src; if (quot > 0xffffffffu) { - VFLG = NFLG = 1; - CFLG = 0; + SET_VFLG (1); + SET_NFLG (1); + SET_CFLG (0); } else { - VFLG = CFLG = 0; - ZFLG = ((uae_s32)quot) == 0; - NFLG = ((uae_s32)quot) < 0; + SET_VFLG (0); + SET_CFLG (0); + SET_ZFLG (((uae_s32)quot) == 0); + SET_NFLG (((uae_s32)quot) < 0); m68k_dreg(regs, extra & 7) = rem; m68k_dreg(regs, (extra >> 12) & 7) = quot; } @@ -835,14 +905,16 @@ void m68k_divl (uae_u32 opcode, uae_u32 if ((uae_s32)src < 0) src = -src; if (div_unsigned(hi, lo, src, ", &rem) || (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) { - VFLG = NFLG = 1; - CFLG = 0; + SET_VFLG (1); + SET_NFLG (1); + SET_CFLG (0); } else { if (sign & 0x80000000) quot = -quot; if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem; - VFLG = CFLG = 0; - ZFLG = ((uae_s32)quot) == 0; - NFLG = ((uae_s32)quot) < 0; + SET_VFLG (0); + SET_CFLG (0); + SET_ZFLG (((uae_s32)quot) == 0); + SET_NFLG (((uae_s32)quot) < 0); m68k_dreg(regs, extra & 7) = rem; m68k_dreg(regs, (extra >> 12) & 7) = quot; } @@ -856,12 +928,14 @@ void m68k_divl (uae_u32 opcode, uae_u32 hi = (uae_u32)m68k_dreg(regs, extra & 7); } if (div_unsigned(hi, lo, src, ", &rem)) { - VFLG = NFLG = 1; - CFLG = 0; + SET_VFLG (1); + SET_NFLG (1); + SET_CFLG (0); } else { - VFLG = CFLG = 0; - ZFLG = ((uae_s32)quot) == 0; - NFLG = ((uae_s32)quot) < 0; + SET_VFLG (0); + SET_CFLG (0); + SET_ZFLG (((uae_s32)quot) == 0); + SET_NFLG (((uae_s32)quot) < 0); m68k_dreg(regs, extra & 7) = rem; m68k_dreg(regs, (extra >> 12) & 7) = quot; } @@ -869,7 +943,7 @@ void m68k_divl (uae_u32 opcode, uae_u32 #endif } -static __inline__ void +STATIC_INLINE void mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo) { uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff); @@ -896,15 +970,16 @@ void m68k_mull (uae_u32 opcode, uae_u32 uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7); a *= (uae_s64)(uae_s32)src; - VFLG = CFLG = 0; - ZFLG = a == 0; - NFLG = a < 0; + SET_VFLG (0); + SET_CFLG (0); + SET_ZFLG (a == 0); + SET_NFLG (a < 0); if (extra & 0x400) m68k_dreg(regs, extra & 7) = a >> 32; else if ((a & UVAL64(0xffffffff80000000)) != 0 && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000)) { - VFLG = 1; + SET_VFLG (1); } m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a; } else { @@ -912,13 +987,14 @@ void m68k_mull (uae_u32 opcode, uae_u32 uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7); a *= (uae_u64)src; - VFLG = CFLG = 0; - ZFLG = a == 0; - NFLG = ((uae_s64)a) < 0; + SET_VFLG (0); + SET_CFLG (0); + SET_ZFLG (a == 0); + SET_NFLG (((uae_s64)a) < 0); if (extra & 0x400) m68k_dreg(regs, extra & 7) = a >> 32; else if ((a & UVAL64(0xffffffff00000000)) != 0) { - VFLG = 1; + SET_VFLG (1); } m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a; } @@ -940,16 +1016,17 @@ void m68k_mull (uae_u32 opcode, uae_u32 dst_lo = -dst_lo; if (dst_lo == 0) dst_hi++; } - VFLG = CFLG = 0; - ZFLG = dst_hi == 0 && dst_lo == 0; - NFLG = ((uae_s32)dst_hi) < 0; + SET_VFLG (0); + SET_CFLG (0); + SET_ZFLG (dst_hi == 0 && dst_lo == 0); + SET_NFLG (((uae_s32)dst_hi) < 0); if (extra & 0x400) m68k_dreg(regs, extra & 7) = dst_hi; else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0) && ((dst_hi & 0xffffffff) != 0xffffffff || (dst_lo & 0x80000000) != 0x80000000)) { - VFLG = 1; + SET_VFLG (1); } m68k_dreg(regs, (extra >> 12) & 7) = dst_lo; } else { @@ -958,13 +1035,14 @@ void m68k_mull (uae_u32 opcode, uae_u32 mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo); - VFLG = CFLG = 0; - ZFLG = dst_hi == 0 && dst_lo == 0; - NFLG = ((uae_s32)dst_hi) < 0; + SET_VFLG (0); + SET_CFLG (0); + SET_ZFLG (dst_hi == 0 && dst_lo == 0); + SET_NFLG (((uae_s32)dst_hi) < 0); if (extra & 0x400) m68k_dreg(regs, extra & 7) = dst_hi; else if (dst_hi != 0) { - VFLG = 1; + SET_VFLG (1); } m68k_dreg(regs, (extra >> 12) & 7) = dst_lo; } @@ -985,7 +1063,11 @@ void m68k_reset (void) regs.stopped = 0; regs.t1 = 0; regs.t0 = 0; - ZFLG = CFLG = NFLG = VFLG = 0; + SET_ZFLG (0); + SET_XFLG (0); + SET_CFLG (0); + SET_VFLG (0); + SET_NFLG (0); regs.spcflags = 0; regs.intmask = 7; regs.vbr = regs.sfc = regs.dfc = 0; @@ -1064,59 +1146,62 @@ static int n_insns = 0, n_spcinsns = 0; static uaecptr last_trace_ad = 0; -static __inline__ void do_trace (void) +static void do_trace (void) { - if (regs.spcflags & SPCFLAG_TRACE) { /* 6 */ - if (regs.t0) { - uae_u16 opcode; - /* should also include TRAP, CHK, SR modification FPcc */ - /* probably never used so why bother */ - /* We can afford this to be inefficient... */ - m68k_setpc (m68k_getpc ()); - fill_prefetch_0 (); - opcode = get_word (regs.pc); - if (opcode == 0x4e72 /* RTE */ - || opcode == 0x4e74 /* RTD */ - || opcode == 0x4e75 /* RTS */ - || opcode == 0x4e77 /* RTR */ - || opcode == 0x4e76 /* TRAPV */ - || (opcode & 0xffc0) == 0x4e80 /* JSR */ - || (opcode & 0xffc0) == 0x4ec0 /* JMP */ - || (opcode & 0xff00) == 0x6100 /* BSR */ - || ((opcode & 0xf000) == 0x6000 /* Bcc */ - && cctrue((opcode >> 8) & 0xf)) - || ((opcode & 0xf0f0) == 0x5050 /* DBcc */ - && !cctrue((opcode >> 8) & 0xf) - && (uae_s16)m68k_dreg(regs, opcode & 7) != 0)) - { - last_trace_ad = m68k_getpc (); - regs.spcflags &= ~SPCFLAG_TRACE; - regs.spcflags |= SPCFLAG_DOTRACE; - } - } else if (regs.t1) { + if (regs.t0) { + uae_u16 opcode; + /* should also include TRAP, CHK, SR modification FPcc */ + /* probably never used so why bother */ + /* We can afford this to be inefficient... */ + m68k_setpc (m68k_getpc ()); + fill_prefetch_0 (); + opcode = get_word (regs.pc); + if (opcode == 0x4e72 /* RTE */ + || opcode == 0x4e74 /* RTD */ + || opcode == 0x4e75 /* RTS */ + || opcode == 0x4e77 /* RTR */ + || opcode == 0x4e76 /* TRAPV */ + || (opcode & 0xffc0) == 0x4e80 /* JSR */ + || (opcode & 0xffc0) == 0x4ec0 /* JMP */ + || (opcode & 0xff00) == 0x6100 /* BSR */ + || ((opcode & 0xf000) == 0x6000 /* Bcc */ + && cctrue((opcode >> 8) & 0xf)) + || ((opcode & 0xf0f0) == 0x5050 /* DBcc */ + && !cctrue((opcode >> 8) & 0xf) + && (uae_s16)m68k_dreg(regs, opcode & 7) != 0)) + { last_trace_ad = m68k_getpc (); regs.spcflags &= ~SPCFLAG_TRACE; regs.spcflags |= SPCFLAG_DOTRACE; } + } else if (regs.t1) { + last_trace_ad = m68k_getpc (); + regs.spcflags &= ~SPCFLAG_TRACE; + regs.spcflags |= SPCFLAG_DOTRACE; } } + static int do_specialties (void) { + if (regs.spcflags & SPCFLAG_COPPER) + do_copper (); + /*n_spcinsns++;*/ while (regs.spcflags & SPCFLAG_BLTNASTY) { do_cycles (4); - if (regs.spcflags & SPCFLAG_DISK) - do_disk (); + if (regs.spcflags & SPCFLAG_COPPER) + do_copper (); } + run_compiled_code(); if (regs.spcflags & SPCFLAG_DOTRACE) { Exception (9,last_trace_ad); } while (regs.spcflags & SPCFLAG_STOP) { do_cycles (4); - if (regs.spcflags & SPCFLAG_DISK) - do_disk (); + if (regs.spcflags & SPCFLAG_COPPER) + do_copper (); if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)){ int intr = intlev (); regs.spcflags &= ~(SPCFLAG_INT | SPCFLAG_DOINT); @@ -1127,10 +1212,8 @@ static int do_specialties (void) } } } - do_trace (); - - if (regs.spcflags & SPCFLAG_DISK) - do_disk (); + if (regs.spcflags & SPCFLAG_TRACE) + do_trace (); if (regs.spcflags & SPCFLAG_DOINT) { int intr = intlev (); @@ -1151,11 +1234,52 @@ static int do_specialties (void) return 0; } +/* It's really sad to have two almost identical functions for this, but we + do it all for performance... :( */ static void m68k_run_1 (void) { for (;;) { int cycles; - uae_u32 opcode = GET_OPCODE; + uae_u32 opcode = get_iword_prefetch (0); +#if 0 + if (get_ilong (0) != do_get_mem_long (®s.prefetch)) { + debugging = 1; + return; + } +#endif + /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */ +/* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/ +#if COUNT_INSTRS == 2 + if (table68k[opcode].handler != -1) + instrcount[table68k[opcode].handler]++; +#elif COUNT_INSTRS == 1 + instrcount[opcode]++; +#endif +#if defined X86_ASSEMBLY + __asm__ __volatile__("\tcall *%%ebx" + : "=&a" (cycles) : "b" (cpufunctbl[opcode]), "0" (opcode) + : "%edx", "%ecx", + "%esi", "%edi", "%ebp", "memory", "cc"); +#else + cycles = (*cpufunctbl[opcode])(opcode); +#endif + /*n_insns++;*/ + cycles &= cycles_mask; + cycles |= cycles_val; + do_cycles (cycles); + if (regs.spcflags) { + if (do_specialties ()) + return; + } + } +} + +/* Same thing, but don't use prefetch to get opcode. */ +static void m68k_run_2 (void) +{ + for (;;) { + int cycles; + uae_u32 opcode = get_iword (0); #if 0 if (get_ilong (0) != do_get_mem_long (®s.prefetch)) { debugging = 1; @@ -1165,12 +1289,12 @@ static void m68k_run_1 (void) /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */ /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/ #if COUNT_INSTRS == 2 - if (table68k[cft_map (opcode)].handler != -1) - instrcount[table68k[cft_map (opcode)].handler]++; + if (table68k[opcode].handler != -1) + instrcount[table68k[opcode].handler]++; #elif COUNT_INSTRS == 1 instrcount[opcode]++; #endif -#if defined(X86_ASSEMBLY) +#if defined X86_ASSEMBLY __asm__ __volatile__("\tcall *%%ebx" : "=&a" (cycles) : "b" (cpufunctbl[opcode]), "0" (opcode) : "%edx", "%ecx", @@ -1190,13 +1314,14 @@ static void m68k_run_1 (void) } #ifdef X86_ASSEMBLY -static __inline__ void m68k_run1 (void) +STATIC_INLINE void m68k_run1 (void (*func)(void)) { /* Work around compiler bug: GCC doesn't push %ebp in m68k_run_1. */ - __asm__ __volatile__ ("pushl %%ebp\n\tcall *%0\n\tpopl %%ebp" : : "r" (m68k_run_1) : "%eax", "%edx", "%ecx", "memory", "cc"); + __asm__ __volatile__ ("pushl %%ebp\n\tcall *%0\n\tpopl %%ebp" + : : "r" (func) : "%eax", "%edx", "%ecx", "memory", "cc"); } #else -#define m68k_run1 m68k_run_1 +#define m68k_run1(F) F #endif int in_m68k_go = 0; @@ -1223,7 +1348,7 @@ void m68k_go (int may_quit) } if (debugging) debug (); - m68k_run1 (); + m68k_run1 (currprefs.cpu_compatible ? m68k_run_1 : m68k_run_2); } in_m68k_go--; } @@ -1237,7 +1362,7 @@ static void m68k_verify (uaecptr addr, u last_op_for_exception_3 = opcode; m68kpc_offset = 2; - if (cpufunctbl[cft_map (opcode)] == op_illg_1) { + if (cpufunctbl[opcode] == op_illg_1) { opcode = 0x4AFC; } dp = table68k + opcode; @@ -1272,7 +1397,7 @@ void m68k_disasm (uaecptr addr, uaecptr } opcode = get_iword_1 (m68kpc_offset); m68kpc_offset += 2; - if (cpufunctbl[cft_map (opcode)] == op_illg_1) { + if (cpufunctbl[opcode] == op_illg_1) { opcode = 0x4AFC; } dp = table68k + opcode; @@ -1333,7 +1458,7 @@ void m68k_dumpstate (uaecptr *nextpc) regs.usp,regs.isp,regs.msp,regs.vbr); printf ("T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n", regs.t1, regs.t0, regs.s, regs.m, - XFLG, NFLG, ZFLG, VFLG, CFLG, regs.intmask); + GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask); for (i = 0; i < 8; i++){ printf ("FP%d: %g ", i, regs.fp[i]); if ((i & 3) == 3) printf ("\n");