![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to newcpu.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [UNIX Amiga Emulator] / uae / src|
Return to newcpu.c CVS log | Up to [UNIX Amiga Emulator] / uae / src |
1.1.1.3 root 1: /*
1.1 root 2: * UAE - The Un*x Amiga Emulator
1.1.1.3 root 3: *
1.1 root 4: * MC68000 emulation
5: *
6: * (c) 1995 Bernd Schmidt
7: */
8:
9: #include "sysconfig.h"
10: #include "sysdeps.h"
11:
12: #include "config.h"
13: #include "options.h"
14: #include "events.h"
1.1.1.3 root 15: #include "uae.h"
1.1 root 16: #include "memory.h"
17: #include "custom.h"
18: #include "newcpu.h"
19: #include "autoconf.h"
20: #include "ersatz.h"
21: #include "debug.h"
1.1.1.3 root 22: #include "gui.h"
1.1.1.14 root 23: #include "savestate.h"
1.1.1.18 root 24: #include "blitter.h"
1.1.1.3 root 25:
26: /* Opcode of faulting instruction */
1.1.1.20 root 27: static uae_u16 last_op_for_exception_3;
1.1.1.3 root 28: /* PC at fault time */
1.1.1.20 root 29: static uaecptr last_addr_for_exception_3;
1.1.1.3 root 30: /* Address that generated the exception */
1.1.1.20 root 31: static uaecptr last_fault_for_exception_3;
32: /* read (0) or write (1) access */
33: static int last_writeaccess_for_exception_3;
34: /* instruction (1) or data (0) access */
35: static int last_instructionaccess_for_exception_3;
1.1 root 36:
37: int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
38: int imm8_table[] = { 8,1,2,3,4,5,6,7 };
39:
40: int movem_index1[256];
41: int movem_index2[256];
42: int movem_next[256];
43:
44: int fpp_movem_index1[256];
45: int fpp_movem_index2[256];
46: int fpp_movem_next[256];
47:
48: cpuop_func *cpufunctbl[65536];
49:
1.1.1.3 root 50: #define COUNT_INSTRS 0
1.1 root 51:
52: #if COUNT_INSTRS
53: static unsigned long int instrcount[65536];
1.1.1.3 root 54: static uae_u16 opcodenums[65536];
1.1 root 55:
1.1.1.4 root 56: static int compfn (const void *el1, const void *el2)
1.1 root 57: {
1.1.1.3 root 58: return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
59: }
60:
61: static char *icountfilename (void)
62: {
63: char *name = getenv ("INSNCOUNT");
64: if (name)
65: return name;
66: return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
1.1 root 67: }
68:
1.1.1.4 root 69: void dump_counts (void)
1.1 root 70: {
1.1.1.4 root 71: FILE *f = fopen (icountfilename (), "w");
1.1.1.3 root 72: unsigned long int total;
1.1 root 73: int i;
1.1.1.3 root 74:
75: write_log ("Writing instruction count file...\n");
1.1.1.4 root 76: for (i = 0; i < 65536; i++) {
1.1 root 77: opcodenums[i] = i;
1.1.1.3 root 78: total += instrcount[i];
1.1 root 79: }
1.1.1.4 root 80: qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
1.1.1.3 root 81:
82: fprintf (f, "Total: %lu\n", total);
83: for (i=0; i < 65536; i++) {
1.1 root 84: unsigned long int cnt = instrcount[opcodenums[i]];
85: struct instr *dp;
86: struct mnemolookup *lookup;
87: if (!cnt)
88: break;
89: dp = table68k + opcodenums[i];
1.1.1.4 root 90: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
91: ;
1.1.1.3 root 92: fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
1.1 root 93: }
1.1.1.4 root 94: fclose (f);
1.1 root 95: }
96: #else
1.1.1.4 root 97: void dump_counts (void)
1.1 root 98: {
99: }
100: #endif
101:
102: int broken_in;
103:
1.1.1.4 root 104: static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM;
105:
106: static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
107: {
1.1.1.8 root 108: op_illg (opcode);
1.1.1.4 root 109: return 4;
110: }
111:
1.1.1.3 root 112: static void build_cpufunctbl (void)
113: {
114: int i;
115: unsigned long opcode;
1.1.1.12 root 116: struct cputbl *tbl = (currprefs.cpu_level == 4 ? op_smalltbl_0_ff
117: : currprefs.cpu_level == 3 ? op_smalltbl_1_ff
118: : currprefs.cpu_level == 2 ? op_smalltbl_2_ff
119: : currprefs.cpu_level == 1 ? op_smalltbl_3_ff
120: : ! currprefs.cpu_compatible ? op_smalltbl_4_ff
121: : op_smalltbl_5_ff);
1.1.1.3 root 122:
1.1.1.4 root 123: write_log ("Building CPU function table (%d %d %d).\n",
124: currprefs.cpu_level, currprefs.cpu_compatible, currprefs.address_space_24);
1.1.1.3 root 125:
126: for (opcode = 0; opcode < 65536; opcode++)
1.1.1.8 root 127: cpufunctbl[opcode] = op_illg_1;
1.1.1.3 root 128: for (i = 0; tbl[i].handler != NULL; i++) {
129: if (! tbl[i].specific)
1.1.1.8 root 130: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1.1.3 root 131: }
132: for (opcode = 0; opcode < 65536; opcode++) {
133: cpuop_func *f;
134:
135: if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > currprefs.cpu_level)
136: continue;
137:
138: if (table68k[opcode].handler != -1) {
1.1.1.8 root 139: f = cpufunctbl[table68k[opcode].handler];
1.1.1.4 root 140: if (f == op_illg_1)
1.1.1.3 root 141: abort();
1.1.1.8 root 142: cpufunctbl[opcode] = f;
1.1.1.3 root 143: }
144: }
145: for (i = 0; tbl[i].handler != NULL; i++) {
146: if (tbl[i].specific)
1.1.1.8 root 147: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
1.1.1.4 root 148: }
149: }
150:
1.1.1.20 root 151: void fill_prefetch_slow (void)
152: {
153: #ifdef CPUEMU_6
154: if (currprefs.cpu_cycle_exact) {
155: regs.ir = get_word_ce (m68k_getpc ());
156: regs.irc = get_word_ce (m68k_getpc () + 2);
157: } else {
158: #endif
159: regs.ir = get_word (m68k_getpc ());
160: regs.irc = get_word (m68k_getpc () + 2);
161: #ifdef CPUEMU_6
162: }
163: #endif
164: }
165:
1.1.1.4 root 166: unsigned long cycles_mask, cycles_val;
167:
168: static void update_68k_cycles (void)
169: {
170: cycles_mask = 0;
171: cycles_val = currprefs.m68k_speed;
172: if (currprefs.m68k_speed < 1) {
173: cycles_mask = 0xFFFFFFFF;
174: cycles_val = 0;
1.1.1.3 root 175: }
176: }
177:
178: void check_prefs_changed_cpu (void)
179: {
180: if (currprefs.cpu_level != changed_prefs.cpu_level
1.1.1.20 root 181: || currprefs.cpu_compatible != changed_prefs.cpu_compatible)
182: {
183: if (!currprefs.cpu_compatible && changed_prefs.cpu_compatible)
184: fill_prefetch_slow ();
185:
1.1.1.3 root 186: currprefs.cpu_level = changed_prefs.cpu_level;
187: currprefs.cpu_compatible = changed_prefs.cpu_compatible;
188: build_cpufunctbl ();
189: }
1.1.1.4 root 190: if (currprefs.m68k_speed != changed_prefs.m68k_speed) {
191: currprefs.m68k_speed = changed_prefs.m68k_speed;
192: reset_frame_rate_hack ();
193: update_68k_cycles ();
194: }
1.1.1.3 root 195: }
196:
1.1 root 197: void init_m68k (void)
198: {
1.1.1.3 root 199: int i;
200:
1.1.1.4 root 201: update_68k_cycles ();
202:
1.1 root 203: for (i = 0 ; i < 256 ; i++) {
1.1.1.3 root 204: int j;
1.1 root 205: for (j = 0 ; j < 8 ; j++) {
206: if (i & (1 << j)) break;
207: }
208: movem_index1[i] = j;
209: movem_index2[i] = 7-j;
210: movem_next[i] = i & (~(1 << j));
211: }
212: for (i = 0 ; i < 256 ; i++) {
1.1.1.3 root 213: int j;
1.1 root 214: for (j = 7 ; j >= 0 ; j--) {
215: if (i & (1 << j)) break;
216: }
1.1.1.8 root 217: fpp_movem_index1[i] = 7-j;
218: fpp_movem_index2[i] = j;
1.1 root 219: fpp_movem_next[i] = i & (~(1 << j));
220: }
221: #if COUNT_INSTRS
222: {
1.1.1.4 root 223: FILE *f = fopen (icountfilename (), "r");
224: memset (instrcount, 0, sizeof instrcount);
1.1 root 225: if (f) {
1.1.1.3 root 226: uae_u32 opcode, count, total;
1.1 root 227: char name[20];
1.1.1.3 root 228: write_log ("Reading instruction count file...\n");
1.1.1.4 root 229: fscanf (f, "Total: %lu\n", &total);
230: while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
1.1 root 231: instrcount[opcode] = count;
232: }
233: fclose(f);
234: }
235: }
236: #endif
1.1.1.5 root 237: write_log ("Building CPU table for configuration: 68");
1.1.1.20 root 238: regs.address_space_mask = 0xffffffff;
1.1.1.5 root 239: if (currprefs.address_space_24 && currprefs.cpu_level > 1)
1.1.1.21! root 240: write_log ("EC");
1.1.1.5 root 241: switch (currprefs.cpu_level) {
1.1.1.12 root 242: case 1:
1.1.1.21! root 243: write_log ("010");
! 244: break;
1.1.1.12 root 245: case 2:
1.1.1.21! root 246: write_log ("020");
! 247: break;
1.1.1.12 root 248: case 3:
1.1.1.21! root 249: write_log ("020/881");
! 250: break;
1.1.1.12 root 251: case 4:
1.1.1.21! root 252: /* Who is going to miss the MMU anyway...? :-) */
! 253: write_log ("040");
! 254: break;
1.1.1.12 root 255: default:
1.1.1.21! root 256: write_log ("000");
! 257: break;
1.1.1.5 root 258: }
259: if (currprefs.cpu_compatible)
1.1.1.21! root 260: write_log (" (compatible mode)");
1.1.1.20 root 261: if (currprefs.address_space_24) {
262: regs.address_space_mask = 0x00ffffff;
263: write_log (" 24-bit addressing");
264: }
1.1.1.5 root 265: write_log ("\n");
266:
1.1 root 267: read_table68k ();
268: do_merges ();
1.1.1.2 root 269:
1.1.1.4 root 270: write_log ("%d CPU functions\n", nr_cpuop_funcs);
1.1 root 271:
1.1.1.3 root 272: build_cpufunctbl ();
273: }
1.1.1.4 root 274:
1.1 root 275: struct regstruct regs, lastint_regs;
276: static struct regstruct regs_backup[16];
277: static int backup_pointer = 0;
1.1.1.3 root 278: static long int m68kpc_offset;
1.1 root 279: int lastint_no;
280:
1.1.1.3 root 281: #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
282: #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
283: #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
284:
1.1.1.11 root 285: uae_s32 ShowEA (FILE *f, int reg, amodes mode, wordsizes size, char *buf)
1.1.1.3 root 286: {
287: uae_u16 dp;
288: uae_s8 disp8;
289: uae_s16 disp16;
1.1 root 290: int r;
1.1.1.3 root 291: uae_u32 dispreg;
292: uaecptr addr;
293: uae_s32 offset = 0;
1.1.1.2 root 294: char buffer[80];
1.1.1.3 root 295:
296: switch (mode){
1.1 root 297: case Dreg:
1.1.1.3 root 298: sprintf (buffer,"D%d", reg);
1.1 root 299: break;
300: case Areg:
1.1.1.3 root 301: sprintf (buffer,"A%d", reg);
1.1 root 302: break;
303: case Aind:
1.1.1.3 root 304: sprintf (buffer,"(A%d)", reg);
1.1 root 305: break;
306: case Aipi:
1.1.1.3 root 307: sprintf (buffer,"(A%d)+", reg);
1.1 root 308: break;
309: case Apdi:
1.1.1.3 root 310: sprintf (buffer,"-(A%d)", reg);
1.1 root 311: break;
312: case Ad16:
1.1.1.4 root 313: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
1.1.1.3 root 314: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
315: sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
1.1.1.8 root 316: (unsigned long)addr);
1.1 root 317: break;
318: case Ad8r:
1.1.1.4 root 319: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
1.1 root 320: disp8 = dp & 0xFF;
321: r = (dp & 0x7000) >> 12;
1.1.1.3 root 322: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
323: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
1.1 root 324: dispreg <<= (dp >> 9) & 3;
1.1.1.3 root 325:
1.1 root 326: if (dp & 0x100) {
1.1.1.3 root 327: uae_s32 outer = 0, disp = 0;
328: uae_s32 base = m68k_areg(regs,reg);
329: char name[10];
330: sprintf (name,"A%d, ",reg);
331: if (dp & 0x80) { base = 0; name[0] = 0; }
332: if (dp & 0x40) dispreg = 0;
1.1.1.4 root 333: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
334: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
1.1.1.3 root 335: base += disp;
336:
1.1.1.4 root 337: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
338: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
1.1.1.3 root 339:
340: if (!(dp & 4)) base += dispreg;
341: if (dp & 3) base = get_long (base);
342: if (dp & 4) base += dispreg;
343:
344: addr = base + outer;
345: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
346: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
347: 1 << ((dp >> 9) & 3),
348: disp,outer,
1.1.1.8 root 349: (unsigned long)addr);
1.1.1.3 root 350: } else {
351: addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
352: sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
1.1 root 353: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
354: 1 << ((dp >> 9) & 3), disp8,
1.1.1.8 root 355: (unsigned long)addr);
1.1 root 356: }
357: break;
358: case PC16:
1.1.1.4 root 359: addr = m68k_getpc () + m68kpc_offset;
360: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
1.1.1.3 root 361: addr += (uae_s16)disp16;
1.1.1.8 root 362: sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
1.1 root 363: break;
364: case PC8r:
1.1.1.4 root 365: addr = m68k_getpc () + m68kpc_offset;
366: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
1.1 root 367: disp8 = dp & 0xFF;
368: r = (dp & 0x7000) >> 12;
1.1.1.2 root 369: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
1.1.1.3 root 370: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
1.1 root 371: dispreg <<= (dp >> 9) & 3;
1.1.1.3 root 372:
1.1 root 373: if (dp & 0x100) {
1.1.1.3 root 374: uae_s32 outer = 0,disp = 0;
375: uae_s32 base = addr;
376: char name[10];
377: sprintf (name,"PC, ");
378: if (dp & 0x80) { base = 0; name[0] = 0; }
379: if (dp & 0x40) dispreg = 0;
1.1.1.4 root 380: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
381: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
1.1.1.3 root 382: base += disp;
383:
1.1.1.4 root 384: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
385: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
1.1.1.3 root 386:
387: if (!(dp & 4)) base += dispreg;
388: if (dp & 3) base = get_long (base);
389: if (dp & 4) base += dispreg;
390:
391: addr = base + outer;
392: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
393: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
394: 1 << ((dp >> 9) & 3),
395: disp,outer,
1.1.1.8 root 396: (unsigned long)addr);
1.1.1.2 root 397: } else {
1.1.1.3 root 398: addr += (uae_s32)((uae_s8)disp8) + dispreg;
399: sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
1.1 root 400: (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
1.1.1.8 root 401: disp8, (unsigned long)addr);
1.1 root 402: }
403: break;
404: case absw:
1.1.1.8 root 405: sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
1.1.1.3 root 406: m68kpc_offset += 2;
1.1 root 407: break;
408: case absl:
1.1.1.8 root 409: sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
1.1.1.3 root 410: m68kpc_offset += 4;
1.1 root 411: break;
412: case imm:
1.1.1.3 root 413: switch (size){
1.1 root 414: case sz_byte:
1.1.1.4 root 415: sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
1.1.1.3 root 416: m68kpc_offset += 2;
417: break;
1.1 root 418: case sz_word:
1.1.1.4 root 419: sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
1.1.1.3 root 420: m68kpc_offset += 2;
421: break;
1.1 root 422: case sz_long:
1.1.1.8 root 423: sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
1.1.1.3 root 424: m68kpc_offset += 4;
425: break;
1.1 root 426: default:
427: break;
428: }
429: break;
430: case imm0:
1.1.1.4 root 431: offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
1.1.1.3 root 432: m68kpc_offset += 2;
433: sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
1.1 root 434: break;
435: case imm1:
1.1.1.4 root 436: offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
1.1.1.3 root 437: m68kpc_offset += 2;
438: sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
1.1 root 439: break;
440: case imm2:
1.1.1.4 root 441: offset = (uae_s32)get_ilong_1 (m68kpc_offset);
1.1.1.3 root 442: m68kpc_offset += 4;
1.1.1.8 root 443: sprintf (buffer,"#$%08lx", (unsigned long)offset);
1.1 root 444: break;
445: case immi:
1.1.1.3 root 446: offset = (uae_s32)(uae_s8)(reg & 0xff);
1.1.1.8 root 447: sprintf (buffer,"#$%08lx", (unsigned long)offset);
1.1 root 448: break;
449: default:
450: break;
451: }
1.1.1.2 root 452: if (buf == 0)
1.1.1.11 root 453: fprintf (f, "%s", buffer);
1.1.1.2 root 454: else
1.1.1.4 root 455: strcat (buf, buffer);
1.1.1.2 root 456: return offset;
1.1 root 457: }
458:
1.1.1.3 root 459: /* The plan is that this will take over the job of exception 3 handling -
460: * the CPU emulation functions will just do a longjmp to m68k_go whenever
461: * they hit an odd address. */
1.1.1.4 root 462: static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
1.1.1.3 root 463: {
464: uae_u16 dp;
465: uae_s8 disp8;
466: uae_s16 disp16;
467: int r;
468: uae_u32 dispreg;
469: uaecptr addr;
470: uae_s32 offset = 0;
471:
472: switch (mode){
473: case Dreg:
474: *val = m68k_dreg (regs, reg);
475: return 1;
476: case Areg:
477: *val = m68k_areg (regs, reg);
478: return 1;
479:
480: case Aind:
481: case Aipi:
482: addr = m68k_areg (regs, reg);
483: break;
484: case Apdi:
485: addr = m68k_areg (regs, reg);
486: break;
487: case Ad16:
1.1.1.4 root 488: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
1.1.1.3 root 489: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
490: break;
491: case Ad8r:
492: addr = m68k_areg (regs, reg);
493: d8r_common:
1.1.1.4 root 494: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
1.1.1.3 root 495: disp8 = dp & 0xFF;
496: r = (dp & 0x7000) >> 12;
497: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
498: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
499: dispreg <<= (dp >> 9) & 3;
500:
501: if (dp & 0x100) {
502: uae_s32 outer = 0, disp = 0;
503: uae_s32 base = addr;
504: if (dp & 0x80) base = 0;
505: if (dp & 0x40) dispreg = 0;
1.1.1.4 root 506: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
507: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
1.1.1.3 root 508: base += disp;
509:
1.1.1.4 root 510: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
511: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
1.1.1.3 root 512:
513: if (!(dp & 4)) base += dispreg;
514: if (dp & 3) base = get_long (base);
515: if (dp & 4) base += dispreg;
516:
517: addr = base + outer;
518: } else {
519: addr += (uae_s32)((uae_s8)disp8) + dispreg;
520: }
521: break;
522: case PC16:
1.1.1.4 root 523: addr = m68k_getpc () + m68kpc_offset;
524: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
1.1.1.3 root 525: addr += (uae_s16)disp16;
526: break;
527: case PC8r:
1.1.1.4 root 528: addr = m68k_getpc () + m68kpc_offset;
1.1.1.3 root 529: goto d8r_common;
530: case absw:
1.1.1.4 root 531: addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
1.1.1.3 root 532: m68kpc_offset += 2;
533: break;
534: case absl:
1.1.1.4 root 535: addr = get_ilong_1 (m68kpc_offset);
1.1.1.3 root 536: m68kpc_offset += 4;
537: break;
538: case imm:
539: switch (size){
540: case sz_byte:
1.1.1.4 root 541: *val = get_iword_1 (m68kpc_offset) & 0xff;
1.1.1.3 root 542: m68kpc_offset += 2;
543: break;
544: case sz_word:
1.1.1.4 root 545: *val = get_iword_1 (m68kpc_offset) & 0xffff;
1.1.1.3 root 546: m68kpc_offset += 2;
547: break;
548: case sz_long:
1.1.1.4 root 549: *val = get_ilong_1 (m68kpc_offset);
1.1.1.3 root 550: m68kpc_offset += 4;
551: break;
552: default:
553: break;
554: }
555: return 1;
556: case imm0:
557: *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
558: m68kpc_offset += 2;
559: return 1;
560: case imm1:
561: *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
562: m68kpc_offset += 2;
563: return 1;
564: case imm2:
565: *val = get_ilong_1 (m68kpc_offset);
566: m68kpc_offset += 4;
567: return 1;
568: case immi:
569: *val = (uae_s32)(uae_s8)(reg & 0xff);
570: return 1;
571: default:
572: addr = 0;
573: break;
574: }
575: if ((addr & 1) == 0)
576: return 1;
577:
1.1.1.4 root 578: last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
1.1.1.3 root 579: last_fault_for_exception_3 = addr;
1.1.1.20 root 580: last_writeaccess_for_exception_3 = 0;
581: last_instructionaccess_for_exception_3 = 0;
1.1.1.3 root 582: return 0;
583: }
584:
1.1.1.5 root 585: uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
586: {
587: int reg = (dp >> 12) & 15;
588: uae_s32 regd = regs.regs[reg];
589: if ((dp & 0x800) == 0)
590: regd = (uae_s32)(uae_s16)regd;
591: regd <<= (dp >> 9) & 3;
592: if (dp & 0x100) {
593: uae_s32 outer = 0;
594: if (dp & 0x80) base = 0;
595: if (dp & 0x40) regd = 0;
596:
597: if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
598: if ((dp & 0x30) == 0x30) base += next_ilong();
599:
600: if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
601: if ((dp & 0x3) == 0x3) outer = next_ilong();
602:
603: if ((dp & 0x4) == 0) base += regd;
604: if (dp & 0x3) base = get_long (base);
605: if (dp & 0x4) base += regd;
606:
607: return base + outer;
608: } else {
609: return base + (uae_s32)((uae_s8)dp) + regd;
610: }
611: }
612:
613: uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
614: {
615: int reg = (dp >> 12) & 15;
616: uae_s32 regd = regs.regs[reg];
617: #if 1
618: if ((dp & 0x800) == 0)
619: regd = (uae_s32)(uae_s16)regd;
620: return base + (uae_s8)dp + regd;
621: #else
622: /* Branch-free code... benchmark this again now that
623: * things are no longer inline. */
624: uae_s32 regd16;
625: uae_u32 mask;
626: mask = ((dp & 0x800) >> 11) - 1;
627: regd16 = (uae_s32)(uae_s16)regd;
628: regd16 &= mask;
629: mask = ~mask;
630: base += (uae_s8)dp;
631: regd &= mask;
632: regd |= regd16;
633: return base + regd;
634: #endif
635: }
636:
1.1.1.4 root 637: void MakeSR (void)
1.1 root 638: {
639: #if 0
640: assert((regs.t1 & 1) == regs.t1);
641: assert((regs.t0 & 1) == regs.t0);
642: assert((regs.s & 1) == regs.s);
643: assert((regs.m & 1) == regs.m);
644: assert((XFLG & 1) == XFLG);
645: assert((NFLG & 1) == NFLG);
646: assert((ZFLG & 1) == ZFLG);
647: assert((VFLG & 1) == VFLG);
648: assert((CFLG & 1) == CFLG);
649: #endif
650: regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
651: | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
1.1.1.6 root 652: | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
653: | GET_CFLG);
1.1 root 654: }
655:
1.1.1.4 root 656: void MakeFromSR (void)
1.1 root 657: {
658: int oldm = regs.m;
659: int olds = regs.s;
660:
661: regs.t1 = (regs.sr >> 15) & 1;
662: regs.t0 = (regs.sr >> 14) & 1;
663: regs.s = (regs.sr >> 13) & 1;
664: regs.m = (regs.sr >> 12) & 1;
665: regs.intmask = (regs.sr >> 8) & 7;
1.1.1.6 root 666: SET_XFLG ((regs.sr >> 4) & 1);
667: SET_NFLG ((regs.sr >> 3) & 1);
668: SET_ZFLG ((regs.sr >> 2) & 1);
669: SET_VFLG ((regs.sr >> 1) & 1);
670: SET_CFLG (regs.sr & 1);
1.1.1.3 root 671: if (currprefs.cpu_level >= 2) {
1.1 root 672: if (olds != regs.s) {
1.1.1.3 root 673: if (olds) {
674: if (oldm)
675: regs.msp = m68k_areg(regs, 7);
676: else
677: regs.isp = m68k_areg(regs, 7);
678: m68k_areg(regs, 7) = regs.usp;
679: } else {
680: regs.usp = m68k_areg(regs, 7);
681: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
682: }
1.1 root 683: } else if (olds && oldm != regs.m) {
684: if (oldm) {
1.1.1.2 root 685: regs.msp = m68k_areg(regs, 7);
686: m68k_areg(regs, 7) = regs.isp;
687: } else {
688: regs.isp = m68k_areg(regs, 7);
689: m68k_areg(regs, 7) = regs.msp;
1.1 root 690: }
691: }
692: } else {
693: if (olds != regs.s) {
1.1.1.3 root 694: if (olds) {
695: regs.isp = m68k_areg(regs, 7);
696: m68k_areg(regs, 7) = regs.usp;
697: } else {
698: regs.usp = m68k_areg(regs, 7);
699: m68k_areg(regs, 7) = regs.isp;
700: }
701: }
1.1 root 702: }
1.1.1.3 root 703:
1.1.1.12 root 704: set_special (SPCFLAG_INT);
1.1 root 705: if (regs.t1 || regs.t0)
1.1.1.12 root 706: set_special (SPCFLAG_TRACE);
1.1 root 707: else
1.1.1.16 root 708: /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
709: SR-modifying instructions (including STOP). */
710: unset_special (SPCFLAG_TRACE);
1.1 root 711: }
712:
1.1.1.20 root 713: static void exception_trace (int nr)
1.1 root 714: {
1.1.1.20 root 715: unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
716: if (regs.t1 && !regs.t0) {
717: /* trace stays pending if exception is div by zero, chk,
718: * trapv or trap #x
719: */
720: if (nr == 5 || nr == 6 || nr == 7 || (nr >= 32 && nr <= 47))
721: set_special (SPCFLAG_DOTRACE);
722: }
723: regs.t1 = regs.t0 = regs.m = 0;
724: }
1.1.1.12 root 725:
1.1.1.20 root 726: static void exception_debug (int nr)
727: {
728: #ifdef DEBUGGER
729: if (!exception_debugging)
730: return;
731: console_out ("Exception %d, PC=%08.8X\n", nr, m68k_getpc());
732: #endif
733: }
734:
735: void Exception_normal (int nr, uaecptr oldpc)
736: {
737: uae_u32 currpc = m68k_getpc (), newpc;
738: int sv = regs.s;
739:
740: exception_debug (nr);
1.1 root 741: MakeSR();
1.1.1.12 root 742:
1.1 root 743: if (!regs.s) {
1.1.1.2 root 744: regs.usp = m68k_areg(regs, 7);
1.1.1.3 root 745: if (currprefs.cpu_level >= 2)
746: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
747: else
748: m68k_areg(regs, 7) = regs.isp;
1.1 root 749: regs.s = 1;
750: }
1.1.1.3 root 751: if (currprefs.cpu_level > 0) {
1.1 root 752: if (nr == 2 || nr == 3) {
753: int i;
1.1.1.20 root 754: if (currprefs.cpu_level >= 4) { /* 68040 */
755: if (nr == 2) {
756: for (i = 0 ; i < 18 ; i++) {
757: m68k_areg(regs, 7) -= 2;
758: put_word (m68k_areg(regs, 7), 0);
759: }
760: m68k_areg(regs, 7) -= 4;
761: put_long (m68k_areg(regs, 7), last_fault_for_exception_3);
762: m68k_areg(regs, 7) -= 2;
763: put_word (m68k_areg(regs, 7), 0);
764: m68k_areg(regs, 7) -= 2;
765: put_word (m68k_areg(regs, 7), 0);
766: m68k_areg(regs, 7) -= 2;
767: put_word (m68k_areg(regs, 7), 0);
768: m68k_areg(regs, 7) -= 2;
769: put_word (m68k_areg(regs, 7), 0x0140 | (sv ? 6 : 2)); /* SSW */
770: m68k_areg(regs, 7) -= 4;
771: put_long (m68k_areg(regs, 7), last_addr_for_exception_3);
772: m68k_areg(regs, 7) -= 2;
773: put_word (m68k_areg(regs, 7), 0x7000 + nr * 4);
774: } else {
775: m68k_areg(regs, 7) -= 4;
776: put_long (m68k_areg(regs, 7), last_fault_for_exception_3);
777: m68k_areg(regs, 7) -= 2;
778: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
779: }
780: } else {
781: uae_u16 ssw = (sv ? 4 : 0) | (last_instructionaccess_for_exception_3 ? 2 : 1);
782: ssw |= last_writeaccess_for_exception_3 ? 0 : 0x40;
783: ssw |= 0x20;
784: for (i = 0 ; i < 36; i++) {
785: m68k_areg(regs, 7) -= 2;
786: put_word (m68k_areg(regs, 7), 0);
787: }
1.1.1.21! root 788: m68k_areg(regs, 7) -= 4;
! 789: put_long (m68k_areg(regs, 7), last_fault_for_exception_3);
1.1.1.20 root 790: m68k_areg(regs, 7) -= 2;
791: put_word (m68k_areg(regs, 7), 0);
792: m68k_areg(regs, 7) -= 2;
793: put_word (m68k_areg(regs, 7), 0);
1.1.1.2 root 794: m68k_areg(regs, 7) -= 2;
795: put_word (m68k_areg(regs, 7), 0);
1.1.1.20 root 796: m68k_areg(regs, 7) -= 2;
797: put_word (m68k_areg(regs, 7), ssw);
798: m68k_areg(regs, 7) -= 2;
799: put_word (m68k_areg(regs, 7), 0xb000 + nr * 4);
1.1 root 800: }
1.1.1.20 root 801: write_log ("Exception %d (%x) at %x -> %x!\n", nr, oldpc, currpc, get_long (regs.vbr + 4*nr));
1.1 root 802: } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
1.1.1.3 root 803: m68k_areg(regs, 7) -= 4;
804: put_long (m68k_areg(regs, 7), oldpc);
805: m68k_areg(regs, 7) -= 2;
806: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
1.1.1.20 root 807: } else if (regs.m && nr >= 24 && nr < 32) { /* M + Interrupt */
1.1.1.3 root 808: m68k_areg(regs, 7) -= 2;
809: put_word (m68k_areg(regs, 7), nr * 4);
810: m68k_areg(regs, 7) -= 4;
1.1.1.12 root 811: put_long (m68k_areg(regs, 7), currpc);
1.1.1.3 root 812: m68k_areg(regs, 7) -= 2;
813: put_word (m68k_areg(regs, 7), regs.sr);
814: regs.sr |= (1 << 13);
815: regs.msp = m68k_areg(regs, 7);
816: m68k_areg(regs, 7) = regs.isp;
817: m68k_areg(regs, 7) -= 2;
818: put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
819: } else {
820: m68k_areg(regs, 7) -= 2;
821: put_word (m68k_areg(regs, 7), nr * 4);
822: }
1.1.1.20 root 823: } else if (nr == 2 || nr == 3) {
824: uae_u16 mode = (sv ? 4 : 0) | (last_instructionaccess_for_exception_3 ? 2 : 1);
1.1.1.21! root 825: mode |= last_writeaccess_for_exception_3 ? 0 : 16;
1.1.1.20 root 826: m68k_areg(regs, 7) -= 14;
827: /* fixme: bit3=I/N */
828: put_word (m68k_areg(regs, 7) + 0, mode);
829: put_long (m68k_areg(regs, 7) + 2, last_fault_for_exception_3);
830: put_word (m68k_areg(regs, 7) + 6, last_op_for_exception_3);
831: put_word (m68k_areg(regs, 7) + 8, regs.sr);
832: put_long (m68k_areg(regs, 7) + 10, last_addr_for_exception_3);
1.1.1.21! root 833: write_log ("Exception %d (%x) at %x -> %x!\n", nr, oldpc, currpc, get_long (regs.vbr + 4*nr));
1.1.1.20 root 834: goto kludge_me_do;
1.1 root 835: }
1.1.1.2 root 836: m68k_areg(regs, 7) -= 4;
1.1.1.12 root 837: put_long (m68k_areg(regs, 7), currpc);
1.1.1.2 root 838: m68k_areg(regs, 7) -= 2;
839: put_word (m68k_areg(regs, 7), regs.sr);
1.1.1.20 root 840: kludge_me_do:
841: newpc = get_long (regs.vbr + 4 * nr);
842: if (newpc & 1) {
843: if (nr == 2 || nr == 3)
844: uae_reset (); /* there is nothing else we can do.. */
845: else
846: exception3 (regs.ir, m68k_getpc(), newpc);
847: return;
848: }
849: m68k_setpc (newpc);
850: fill_prefetch_slow ();
851: exception_trace (nr);
852: }
853:
854: void Exception (int nr, uaecptr oldpc)
855: {
856: Exception_normal (nr, oldpc);
1.1 root 857: }
858:
1.1.1.17 root 859: static void Interrupt (int nr)
1.1 root 860: {
1.1.1.20 root 861: regs.stopped = 0;
862: unset_special (SPCFLAG_STOP);
1.1 root 863: assert(nr < 8 && nr >= 0);
864: lastint_regs = regs;
865: lastint_no = nr;
1.1.1.20 root 866: Exception (nr + 24, 0);
1.1.1.3 root 867:
1.1 root 868: regs.intmask = nr;
1.1.1.12 root 869: set_special (SPCFLAG_INT);
1.1 root 870: }
871:
1.1.1.15 root 872: static uae_u32 caar, cacr, itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp;
1.1 root 873:
1.1.1.9 root 874: int m68k_move2c (int regno, uae_u32 *regp)
1.1 root 875: {
1.1.1.12 root 876: if ((currprefs.cpu_level == 1 && (regno & 0x7FF) > 1)
877: || (currprefs.cpu_level < 4 && (regno & 0x7FF) > 2)
878: || (currprefs.cpu_level == 4 && regno == 0x802))
879: {
1.1 root 880: op_illg (0x4E7B);
1.1.1.9 root 881: return 0;
1.1.1.12 root 882: } else {
1.1 root 883: switch (regno) {
1.1.1.12 root 884: case 0: regs.sfc = *regp & 7; break;
885: case 1: regs.dfc = *regp & 7; break;
886: case 2: cacr = *regp & (currprefs.cpu_level < 4 ? 0x3 : 0x80008000); break;
887: case 3: tc = *regp & 0xc000; break;
1.1.1.15 root 888: /* Mask out fields that should be zero. */
1.1.1.12 root 889: case 4: itt0 = *regp & 0xffffe364; break;
890: case 5: itt1 = *regp & 0xffffe364; break;
891: case 6: dtt0 = *regp & 0xffffe364; break;
892: case 7: dtt1 = *regp & 0xffffe364; break;
893:
894: case 0x800: regs.usp = *regp; break;
895: case 0x801: regs.vbr = *regp; break;
896: case 0x802: caar = *regp & 0xfc; break;
897: case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
898: case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
1.1.1.15 root 899: case 0x805: mmusr = *regp; break;
900: case 0x806: urp = *regp; break;
901: case 0x807: srp = *regp; break;
1.1.1.12 root 902: default:
1.1 root 903: op_illg (0x4E7B);
1.1.1.9 root 904: return 0;
1.1 root 905: }
1.1.1.12 root 906: }
1.1.1.9 root 907: return 1;
1.1 root 908: }
909:
1.1.1.9 root 910: int m68k_movec2 (int regno, uae_u32 *regp)
1.1 root 911: {
1.1.1.12 root 912: if ((currprefs.cpu_level == 1 && (regno & 0x7FF) > 1)
913: || (currprefs.cpu_level < 4 && (regno & 0x7FF) > 2)
914: || (currprefs.cpu_level == 4 && regno == 0x802))
915: {
1.1 root 916: op_illg (0x4E7A);
1.1.1.9 root 917: return 0;
1.1.1.12 root 918: } else {
1.1 root 919: switch (regno) {
1.1.1.12 root 920: case 0: *regp = regs.sfc; break;
921: case 1: *regp = regs.dfc; break;
922: case 2: *regp = cacr; break;
923: case 3: *regp = tc; break;
924: case 4: *regp = itt0; break;
925: case 5: *regp = itt1; break;
926: case 6: *regp = dtt0; break;
927: case 7: *regp = dtt1; break;
928: case 0x800: *regp = regs.usp; break;
929: case 0x801: *regp = regs.vbr; break;
930: case 0x802: *regp = caar; break;
931: case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
932: case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
933: case 0x805: *regp = mmusr; break;
1.1.1.15 root 934: case 0x806: *regp = urp; break;
935: case 0x807: *regp = srp; break;
1.1.1.12 root 936: default:
1.1 root 937: op_illg (0x4E7A);
1.1.1.9 root 938: return 0;
1.1 root 939: }
1.1.1.12 root 940: }
1.1.1.9 root 941: return 1;
1.1 root 942: }
943:
1.1.1.8 root 944: STATIC_INLINE int
1.1.1.3 root 945: div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 div, uae_u32 *quot, uae_u32 *rem)
1.1 root 946: {
1.1.1.3 root 947: uae_u32 q = 0, cbit = 0;
1.1 root 948: int i;
949:
950: if (div <= src_hi) {
1.1.1.4 root 951: return 1;
1.1 root 952: }
953: for (i = 0 ; i < 32 ; i++) {
1.1.1.2 root 954: cbit = src_hi & 0x80000000ul;
1.1 root 955: src_hi <<= 1;
1.1.1.2 root 956: if (src_lo & 0x80000000ul) src_hi++;
1.1 root 957: src_lo <<= 1;
958: q = q << 1;
959: if (cbit || div <= src_hi) {
960: q |= 1;
961: src_hi -= div;
962: }
963: }
964: *quot = q;
965: *rem = src_hi;
1.1.1.4 root 966: return 0;
1.1 root 967: }
968:
1.1.1.3 root 969: void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
1.1 root 970: {
1.1.1.3 root 971: #if defined(uae_s64)
1.1 root 972: if (src == 0) {
1.1.1.4 root 973: Exception (5, oldpc);
1.1 root 974: return;
975: }
976: if (extra & 0x800) {
977: /* signed variant */
1.1.1.3 root 978: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
979: uae_s64 quot, rem;
980:
1.1 root 981: if (extra & 0x400) {
1.1.1.3 root 982: a &= 0xffffffffu;
983: a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
1.1 root 984: }
1.1.1.3 root 985: rem = a % (uae_s64)(uae_s32)src;
986: quot = a / (uae_s64)(uae_s32)src;
987: if ((quot & UVAL64(0xffffffff80000000)) != 0
988: && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
989: {
1.1.1.6 root 990: SET_VFLG (1);
991: SET_NFLG (1);
992: SET_CFLG (0);
1.1.1.4 root 993: } else {
1.1.1.3 root 994: if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
1.1.1.6 root 995: SET_VFLG (0);
996: SET_CFLG (0);
997: SET_ZFLG (((uae_s32)quot) == 0);
998: SET_NFLG (((uae_s32)quot) < 0);
1.1.1.2 root 999: m68k_dreg(regs, extra & 7) = rem;
1000: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1.1 root 1001: }
1002: } else {
1003: /* unsigned */
1.1.1.3 root 1004: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1005: uae_u64 quot, rem;
1006:
1.1 root 1007: if (extra & 0x400) {
1.1.1.3 root 1008: a &= 0xffffffffu;
1009: a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
1.1 root 1010: }
1.1.1.3 root 1011: rem = a % (uae_u64)src;
1012: quot = a / (uae_u64)src;
1013: if (quot > 0xffffffffu) {
1.1.1.6 root 1014: SET_VFLG (1);
1015: SET_NFLG (1);
1016: SET_CFLG (0);
1.1.1.4 root 1017: } else {
1.1.1.6 root 1018: SET_VFLG (0);
1019: SET_CFLG (0);
1020: SET_ZFLG (((uae_s32)quot) == 0);
1021: SET_NFLG (((uae_s32)quot) < 0);
1.1.1.2 root 1022: m68k_dreg(regs, extra & 7) = rem;
1023: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1.1 root 1024: }
1025: }
1026: #else
1027: if (src == 0) {
1.1.1.4 root 1028: Exception (5, oldpc);
1.1 root 1029: return;
1030: }
1031: if (extra & 0x800) {
1032: /* signed variant */
1.1.1.3 root 1033: uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1034: uae_s32 hi = lo < 0 ? -1 : 0;
1035: uae_s32 save_high;
1036: uae_u32 quot, rem;
1037: uae_u32 sign;
1038:
1.1 root 1039: if (extra & 0x400) {
1.1.1.3 root 1040: hi = (uae_s32)m68k_dreg(regs, extra & 7);
1.1 root 1041: }
1042: save_high = hi;
1043: sign = (hi ^ src);
1044: if (hi < 0) {
1.1.1.4 root 1045: hi = ~hi;
1046: lo = -lo;
1047: if (lo == 0) hi++;
1.1 root 1048: }
1.1.1.3 root 1049: if ((uae_s32)src < 0) src = -src;
1.1 root 1050: if (div_unsigned(hi, lo, src, ", &rem) ||
1051: (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
1.1.1.6 root 1052: SET_VFLG (1);
1053: SET_NFLG (1);
1054: SET_CFLG (0);
1.1.1.4 root 1055: } else {
1.1 root 1056: if (sign & 0x80000000) quot = -quot;
1.1.1.3 root 1057: if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
1.1.1.6 root 1058: SET_VFLG (0);
1059: SET_CFLG (0);
1060: SET_ZFLG (((uae_s32)quot) == 0);
1061: SET_NFLG (((uae_s32)quot) < 0);
1.1.1.2 root 1062: m68k_dreg(regs, extra & 7) = rem;
1063: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1.1 root 1064: }
1065: } else {
1066: /* unsigned */
1.1.1.3 root 1067: uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1068: uae_u32 hi = 0;
1069: uae_u32 quot, rem;
1070:
1.1 root 1071: if (extra & 0x400) {
1.1.1.3 root 1072: hi = (uae_u32)m68k_dreg(regs, extra & 7);
1.1 root 1073: }
1074: if (div_unsigned(hi, lo, src, ", &rem)) {
1.1.1.6 root 1075: SET_VFLG (1);
1076: SET_NFLG (1);
1077: SET_CFLG (0);
1.1.1.4 root 1078: } else {
1.1.1.6 root 1079: SET_VFLG (0);
1080: SET_CFLG (0);
1081: SET_ZFLG (((uae_s32)quot) == 0);
1082: SET_NFLG (((uae_s32)quot) < 0);
1.1.1.2 root 1083: m68k_dreg(regs, extra & 7) = rem;
1084: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1.1 root 1085: }
1086: }
1087: #endif
1088: }
1089:
1.1.1.8 root 1090: STATIC_INLINE void
1.1.1.3 root 1091: mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1.1 root 1092: {
1.1.1.3 root 1093: uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1094: uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1095: uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1096: uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1097: uae_u32 lo;
1098:
1099: lo = r0 + ((r1 << 16) & 0xffff0000ul);
1100: if (lo < r0) r3++;
1101: r0 = lo;
1102: lo = r0 + ((r2 << 16) & 0xffff0000ul);
1103: if (lo < r0) r3++;
1104: r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1.1 root 1105: *dst_lo = lo;
1106: *dst_hi = r3;
1107: }
1108:
1.1.1.3 root 1109: void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1.1 root 1110: {
1.1.1.3 root 1111: #if defined(uae_s64)
1.1 root 1112: if (extra & 0x800) {
1113: /* signed variant */
1.1.1.3 root 1114: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1.1 root 1115:
1.1.1.3 root 1116: a *= (uae_s64)(uae_s32)src;
1.1.1.6 root 1117: SET_VFLG (0);
1118: SET_CFLG (0);
1119: SET_ZFLG (a == 0);
1120: SET_NFLG (a < 0);
1.1 root 1121: if (extra & 0x400)
1.1.1.2 root 1122: m68k_dreg(regs, extra & 7) = a >> 32;
1.1.1.3 root 1123: else if ((a & UVAL64(0xffffffff80000000)) != 0
1124: && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1125: {
1.1.1.6 root 1126: SET_VFLG (1);
1.1 root 1127: }
1.1.1.3 root 1128: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1.1 root 1129: } else {
1130: /* unsigned */
1.1.1.3 root 1131: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1132:
1133: a *= (uae_u64)src;
1.1.1.6 root 1134: SET_VFLG (0);
1135: SET_CFLG (0);
1136: SET_ZFLG (a == 0);
1137: SET_NFLG (((uae_s64)a) < 0);
1.1 root 1138: if (extra & 0x400)
1.1.1.2 root 1139: m68k_dreg(regs, extra & 7) = a >> 32;
1.1.1.3 root 1140: else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1.1.1.6 root 1141: SET_VFLG (1);
1.1 root 1142: }
1.1.1.3 root 1143: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1.1 root 1144: }
1145: #else
1146: if (extra & 0x800) {
1147: /* signed variant */
1.1.1.3 root 1148: uae_s32 src1,src2;
1149: uae_u32 dst_lo,dst_hi;
1150: uae_u32 sign;
1.1 root 1151:
1.1.1.3 root 1152: src1 = (uae_s32)src;
1153: src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1.1 root 1154: sign = (src1 ^ src2);
1155: if (src1 < 0) src1 = -src1;
1156: if (src2 < 0) src2 = -src2;
1.1.1.3 root 1157: mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1.1 root 1158: if (sign & 0x80000000) {
1159: dst_hi = ~dst_hi;
1160: dst_lo = -dst_lo;
1161: if (dst_lo == 0) dst_hi++;
1162: }
1.1.1.6 root 1163: SET_VFLG (0);
1164: SET_CFLG (0);
1165: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1166: SET_NFLG (((uae_s32)dst_hi) < 0);
1.1 root 1167: if (extra & 0x400)
1.1.1.2 root 1168: m68k_dreg(regs, extra & 7) = dst_hi;
1.1.1.3 root 1169: else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1170: && ((dst_hi & 0xffffffff) != 0xffffffff
1171: || (dst_lo & 0x80000000) != 0x80000000))
1172: {
1.1.1.6 root 1173: SET_VFLG (1);
1.1 root 1174: }
1.1.1.2 root 1175: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1.1 root 1176: } else {
1177: /* unsigned */
1.1.1.3 root 1178: uae_u32 dst_lo,dst_hi;
1179:
1180: mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1.1 root 1181:
1.1.1.6 root 1182: SET_VFLG (0);
1183: SET_CFLG (0);
1184: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1185: SET_NFLG (((uae_s32)dst_hi) < 0);
1.1 root 1186: if (extra & 0x400)
1.1.1.2 root 1187: m68k_dreg(regs, extra & 7) = dst_hi;
1.1 root 1188: else if (dst_hi != 0) {
1.1.1.6 root 1189: SET_VFLG (1);
1.1 root 1190: }
1.1.1.2 root 1191: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1.1 root 1192: }
1193: #endif
1194: }
1195: static char* ccnames[] =
1196: { "T ","F ","HI","LS","CC","CS","NE","EQ",
1197: "VC","VS","PL","MI","GE","LT","GT","LE" };
1198:
1.1.1.4 root 1199: void m68k_reset (void)
1.1 root 1200: {
1.1.1.14 root 1201: regs.kick_mask = 0x00F80000;
1202: regs.spcflags = 0;
1203: if (savestate_state == STATE_RESTORE) {
1.1.1.21! root 1204: m68k_setpc (regs.pc);
1.1.1.14 root 1205: /* MakeFromSR() must not swap stack pointer */
1206: regs.s = (regs.sr >> 13) & 1;
1207: MakeFromSR();
1208: /* set stack pointer */
1209: if (regs.s)
1210: m68k_areg(regs, 7) = regs.isp;
1211: else
1212: m68k_areg(regs, 7) = regs.usp;
1213: return;
1214: }
1215:
1.1.1.3 root 1216: m68k_areg (regs, 7) = get_long (0x00f80000);
1217: m68k_setpc (get_long (0x00f80004));
1.1 root 1218: regs.s = 1;
1219: regs.m = 0;
1220: regs.stopped = 0;
1221: regs.t1 = 0;
1222: regs.t0 = 0;
1.1.1.6 root 1223: SET_ZFLG (0);
1224: SET_XFLG (0);
1225: SET_CFLG (0);
1226: SET_VFLG (0);
1227: SET_NFLG (0);
1.1 root 1228: regs.intmask = 7;
1229: regs.vbr = regs.sfc = regs.dfc = 0;
1230: regs.fpcr = regs.fpsr = regs.fpiar = 0;
1.1.1.20 root 1231: regs.irc = 0xffff;
1232: fill_prefetch_slow ();
1.1 root 1233: }
1234:
1.1.1.4 root 1235: unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1.1 root 1236: {
1.1.1.3 root 1237: uaecptr pc = m68k_getpc ();
1.1.1.4 root 1238:
1.1.1.3 root 1239: if (cloanto_rom && (opcode & 0xF100) == 0x7100) {
1240: m68k_dreg (regs, (opcode >> 9) & 7) = (uae_s8)(opcode & 0xFF);
1241: m68k_incpc (2);
1.1.1.20 root 1242: fill_prefetch_slow ();
1.1.1.4 root 1243: return 4;
1.1.1.3 root 1244: }
1245:
1246: if (opcode == 0x4E7B && get_long (0x10) == 0 && (pc & 0xF80000) == 0xF80000) {
1.1.1.4 root 1247: write_log ("Your Kickstart requires a 68020 CPU. Giving up.\n");
1.1.1.3 root 1248: broken_in = 1;
1.1.1.12 root 1249: set_special (SPCFLAG_BRK);
1.1 root 1250: quit_program = 1;
1251: }
1.1.1.2 root 1252: if (opcode == 0xFF0D) {
1.1.1.3 root 1253: if ((pc & 0xF80000) == 0xF80000) {
1.1.1.2 root 1254: /* This is from the dummy Kickstart replacement */
1.1.1.3 root 1255: uae_u16 arg = get_iword (2);
1256: m68k_incpc (4);
1257: ersatz_perform (arg);
1.1.1.20 root 1258: fill_prefetch_slow ();
1.1.1.4 root 1259: return 4;
1.1.1.17 root 1260: } else if ((pc & 0xFFFF0000) == RTAREA_BASE) {
1.1.1.2 root 1261: /* User-mode STOP replacement */
1.1.1.3 root 1262: m68k_setstopped (1);
1.1.1.4 root 1263: return 4;
1.1.1.2 root 1264: }
1.1 root 1265: }
1.1.1.3 root 1266:
1.1.1.17 root 1267: if ((opcode & 0xF000) == 0xA000 && (pc & 0xFFFF0000) == RTAREA_BASE) {
1.1.1.3 root 1268: /* Calltrap. */
1269: m68k_incpc(2);
1270: call_calltrap (opcode & 0xFFF);
1.1.1.20 root 1271: fill_prefetch_slow ();
1.1.1.4 root 1272: return 4;
1.1.1.3 root 1273: }
1274:
1.1 root 1275: if ((opcode & 0xF000) == 0xF000) {
1276: Exception(0xB,0);
1.1.1.4 root 1277: return 4;
1.1 root 1278: }
1279: if ((opcode & 0xF000) == 0xA000) {
1.1.1.17 root 1280: if ((pc & 0xFFFF0000) == RTAREA_BASE) {
1.1.1.3 root 1281: /* Calltrap. */
1282: call_calltrap (opcode & 0xFFF);
1283: }
1284: Exception(0xA,0);
1.1.1.4 root 1285: return 4;
1.1 root 1286: }
1.1.1.12 root 1287: #if 1
1.1.1.4 root 1288: write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
1.1.1.10 root 1289: #endif
1.1.1.3 root 1290: Exception (4,0);
1.1.1.4 root 1291: return 4;
1.1 root 1292: }
1293:
1.1.1.3 root 1294: void mmu_op(uae_u32 opcode, uae_u16 extra)
1.1 root 1295: {
1.1.1.12 root 1296: if ((opcode & 0xFE0) == 0x0500) {
1297: /* PFLUSH */
1298: mmusr = 0;
1299: write_log ("PFLUSH\n");
1300: } else if ((opcode & 0x0FD8) == 0x548) {
1301: /* PTEST */
1302: write_log ("PTEST\n");
1.1 root 1303: } else
1.1.1.3 root 1304: op_illg (opcode);
1.1 root 1305: }
1306:
1.1.1.4 root 1307: static int n_insns = 0, n_spcinsns = 0;
1.1 root 1308:
1.1.1.3 root 1309: static uaecptr last_trace_ad = 0;
1.1 root 1310:
1.1.1.7 root 1311: static void do_trace (void)
1.1 root 1312: {
1.1.1.11 root 1313: if (regs.t0 && currprefs.cpu_level >= 2) {
1.1.1.7 root 1314: uae_u16 opcode;
1315: /* should also include TRAP, CHK, SR modification FPcc */
1316: /* probably never used so why bother */
1317: /* We can afford this to be inefficient... */
1318: m68k_setpc (m68k_getpc ());
1.1.1.20 root 1319: fill_prefetch_slow ();
1.1.1.7 root 1320: opcode = get_word (regs.pc);
1321: if (opcode == 0x4e72 /* RTE */
1322: || opcode == 0x4e74 /* RTD */
1323: || opcode == 0x4e75 /* RTS */
1324: || opcode == 0x4e77 /* RTR */
1325: || opcode == 0x4e76 /* TRAPV */
1326: || (opcode & 0xffc0) == 0x4e80 /* JSR */
1327: || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1328: || (opcode & 0xff00) == 0x6100 /* BSR */
1329: || ((opcode & 0xf000) == 0x6000 /* Bcc */
1330: && cctrue((opcode >> 8) & 0xf))
1331: || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1332: && !cctrue((opcode >> 8) & 0xf)
1333: && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1334: {
1.1.1.4 root 1335: last_trace_ad = m68k_getpc ();
1.1.1.12 root 1336: unset_special (SPCFLAG_TRACE);
1337: set_special (SPCFLAG_DOTRACE);
1.1 root 1338: }
1.1.1.7 root 1339: } else if (regs.t1) {
1340: last_trace_ad = m68k_getpc ();
1.1.1.12 root 1341: unset_special (SPCFLAG_TRACE);
1342: set_special (SPCFLAG_DOTRACE);
1.1 root 1343: }
1344: }
1345:
1.1.1.19 root 1346: static int do_specialties (int cycles)
1.1 root 1347: {
1.1.1.9 root 1348: if (regs.spcflags & SPCFLAG_COPPER)
1349: do_copper ();
1350:
1.1.1.3 root 1351: /*n_spcinsns++;*/
1.1.1.19 root 1352: while ((regs.spcflags & SPCFLAG_BLTNASTY) && cycles > 0) {
1.1.1.18 root 1353: int c = blitnasty();
1.1.1.19 root 1354: if (!c) {
1355: cycles -= 2 * CYCLE_UNIT;
1356: if (cycles < CYCLE_UNIT)
1357: cycles = 0;
1358: c = 1;
1359: }
1.1.1.18 root 1360: do_cycles (c * CYCLE_UNIT);
1.1.1.9 root 1361: if (regs.spcflags & SPCFLAG_COPPER)
1362: do_copper ();
1.1.1.3 root 1363: }
1.1.1.9 root 1364:
1.1.1.21! root 1365: if (regs.spcflags & SPCFLAG_DOTRACE)
1.1.1.4 root 1366: Exception (9,last_trace_ad);
1.1.1.21! root 1367:
1.1.1.3 root 1368: while (regs.spcflags & SPCFLAG_STOP) {
1.1.1.13 root 1369: do_cycles (4 * CYCLE_UNIT);
1.1.1.9 root 1370: if (regs.spcflags & SPCFLAG_COPPER)
1371: do_copper ();
1.1.1.21! root 1372: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1.1.1.4 root 1373: int intr = intlev ();
1.1.1.12 root 1374: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1.1.1.3 root 1375: if (intr != -1 && intr > regs.intmask) {
1.1.1.4 root 1376: Interrupt (intr);
1.1.1.3 root 1377: regs.stopped = 0;
1.1.1.12 root 1378: unset_special (SPCFLAG_STOP);
1.1.1.2 root 1379: }
1.1.1.3 root 1380: }
1381: }
1.1.1.7 root 1382: if (regs.spcflags & SPCFLAG_TRACE)
1383: do_trace ();
1.1.1.4 root 1384:
1.1.1.3 root 1385: if (regs.spcflags & SPCFLAG_DOINT) {
1.1.1.4 root 1386: int intr = intlev ();
1.1.1.12 root 1387: unset_special (SPCFLAG_DOINT);
1.1.1.3 root 1388: if (intr != -1 && intr > regs.intmask) {
1.1.1.4 root 1389: Interrupt (intr);
1.1.1.3 root 1390: regs.stopped = 0;
1391: }
1392: }
1393: if (regs.spcflags & SPCFLAG_INT) {
1.1.1.12 root 1394: unset_special (SPCFLAG_INT);
1395: set_special (SPCFLAG_DOINT);
1.1.1.3 root 1396: }
1.1.1.4 root 1397: if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1.1.1.12 root 1398: unset_special (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE);
1.1.1.3 root 1399: return 1;
1.1.1.2 root 1400: }
1.1.1.3 root 1401: return 0;
1.1.1.2 root 1402: }
1403:
1.1.1.8 root 1404: /* It's really sad to have two almost identical functions for this, but we
1405: do it all for performance... :( */
1.1.1.4 root 1406: static void m68k_run_1 (void)
1.1.1.2 root 1407: {
1.1.1.3 root 1408: for (;;) {
1.1.1.4 root 1409: int cycles;
1.1.1.20 root 1410: uae_u32 opcode = regs.ir;
1411:
1.1.1.8 root 1412: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1413: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1414: #if COUNT_INSTRS == 2
1415: if (table68k[opcode].handler != -1)
1416: instrcount[table68k[opcode].handler]++;
1417: #elif COUNT_INSTRS == 1
1418: instrcount[opcode]++;
1419: #endif
1420: cycles = (*cpufunctbl[opcode])(opcode);
1421: /*n_insns++;*/
1422: cycles &= cycles_mask;
1423: cycles |= cycles_val;
1424: do_cycles (cycles);
1425: if (regs.spcflags) {
1.1.1.19 root 1426: if (do_specialties (cycles))
1.1.1.8 root 1427: return;
1428: }
1429: }
1430: }
1431:
1.1.1.12 root 1432: #define DEBUG_PREFETCH
1433:
1.1.1.8 root 1434: /* Same thing, but don't use prefetch to get opcode. */
1435: static void m68k_run_2 (void)
1436: {
1437: for (;;) {
1438: int cycles;
1439: uae_u32 opcode = get_iword (0);
1.1.1.12 root 1440:
1.1.1.2 root 1441: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1442: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1.1.1.3 root 1443: #if COUNT_INSTRS == 2
1.1.1.8 root 1444: if (table68k[opcode].handler != -1)
1445: instrcount[table68k[opcode].handler]++;
1.1.1.3 root 1446: #elif COUNT_INSTRS == 1
1.1.1.2 root 1447: instrcount[opcode]++;
1448: #endif
1.1.1.4 root 1449: cycles = (*cpufunctbl[opcode])(opcode);
1.1.1.12 root 1450:
1.1.1.2 root 1451: /*n_insns++;*/
1.1.1.4 root 1452: cycles &= cycles_mask;
1453: cycles |= cycles_val;
1.1.1.21! root 1454: do_cycles (cycles);
1.1.1.2 root 1455: if (regs.spcflags) {
1.1.1.19 root 1456: if (do_specialties (cycles))
1.1 root 1457: return;
1458: }
1459: }
1460: }
1461:
1.1.1.13 root 1462: #define m68k_run1(F) (F) ()
1.1.1.2 root 1463:
1.1.1.3 root 1464: int in_m68k_go = 0;
1.1 root 1465:
1.1.1.20 root 1466: static void exception2_handle (uaecptr addr, uaecptr fault)
1467: {
1468: last_addr_for_exception_3 = addr;
1469: last_fault_for_exception_3 = fault;
1470: last_writeaccess_for_exception_3 = 0;
1471: last_instructionaccess_for_exception_3 = 0;
1472: Exception (2, addr);
1473: }
1474:
1.1.1.4 root 1475: void m68k_go (int may_quit)
1.1 root 1476: {
1.1.1.3 root 1477: if (in_m68k_go || !may_quit) {
1.1.1.4 root 1478: write_log ("Bug! m68k_go is not reentrant.\n");
1479: abort ();
1.1.1.3 root 1480: }
1.1.1.4 root 1481:
1482: reset_frame_rate_hack ();
1483: update_68k_cycles ();
1484:
1.1.1.3 root 1485: in_m68k_go++;
1486: for (;;) {
1487: if (quit_program > 0) {
1488: if (quit_program == 1)
1.1 root 1489: break;
1.1.1.3 root 1490: quit_program = 0;
1.1.1.18 root 1491: if (savestate_state == STATE_RESTORE) {
1492: restore_state (savestate_filename);
1493: #if 0
1494: activate_debugger ();
1495: #endif
1496: }
1.1.1.4 root 1497: m68k_reset ();
1498: reset_all_systems ();
1499: customreset ();
1.1.1.14 root 1500: /* We may have been restoring state, but we're done now. */
1501: savestate_restore_finish ();
1.1.1.20 root 1502: fill_prefetch_slow ();
1.1.1.14 root 1503: handle_active_events ();
1.1.1.18 root 1504: if (regs.spcflags)
1.1.1.19 root 1505: do_specialties (0);
1.1.1.20 root 1506: m68k_setpc (regs.pc);
1.1 root 1507: }
1.1.1.14 root 1508:
1.1.1.3 root 1509: if (debugging)
1.1.1.4 root 1510: debug ();
1.1.1.20 root 1511: if (regs.panic) {
1512: regs.panic = 0;
1513: /* program jumped to non-existing memory and cpu was >= 68020 */
1514: get_real_address (regs.isp); /* stack in no one's land? -> reboot */
1515: if (regs.isp & 1)
1516: regs.panic = 1;
1517: if (!regs.panic)
1518: exception2_handle (regs.panic_pc, regs.panic_addr);
1519: if (regs.panic) {
1520: /* system is very badly confused */
1521: write_log ("double bus error or corrupted stack, forcing reboot..\n");
1522: regs.panic = 0;
1523: uae_reset ();
1524: }
1525: }
1.1.1.8 root 1526: m68k_run1 (currprefs.cpu_compatible ? m68k_run_1 : m68k_run_2);
1.1 root 1527: }
1.1.1.3 root 1528: in_m68k_go--;
1.1 root 1529: }
1530:
1.1.1.4 root 1531: static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1.1 root 1532: {
1.1.1.3 root 1533: uae_u32 opcode, val;
1534: struct instr *dp;
1535:
1536: opcode = get_iword_1(0);
1537: last_op_for_exception_3 = opcode;
1538: m68kpc_offset = 2;
1539:
1.1.1.8 root 1540: if (cpufunctbl[opcode] == op_illg_1) {
1.1.1.3 root 1541: opcode = 0x4AFC;
1542: }
1543: dp = table68k + opcode;
1544:
1545: if (dp->suse) {
1546: if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
1547: Exception (3, 0);
1548: return;
1549: }
1550: }
1551: if (dp->duse) {
1552: if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
1553: Exception (3, 0);
1554: return;
1555: }
1556: }
1557: }
1558:
1.1.1.11 root 1559: void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1.1.1.3 root 1560: {
1561: uaecptr newpc = 0;
1.1.1.4 root 1562: m68kpc_offset = addr - m68k_getpc ();
1563: while (cnt-- > 0) {
1.1 root 1564: char instrname[20],*ccpt;
1565: int opwords;
1.1.1.3 root 1566: uae_u32 opcode;
1.1 root 1567: struct mnemolookup *lookup;
1568: struct instr *dp;
1.1.1.11 root 1569: fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset);
1.1.1.3 root 1570: for (opwords = 0; opwords < 5; opwords++){
1.1.1.11 root 1571: fprintf (f, "%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1.1 root 1572: }
1.1.1.4 root 1573: opcode = get_iword_1 (m68kpc_offset);
1.1.1.3 root 1574: m68kpc_offset += 2;
1.1.1.8 root 1575: if (cpufunctbl[opcode] == op_illg_1) {
1.1 root 1576: opcode = 0x4AFC;
1577: }
1578: dp = table68k + opcode;
1579: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1580: ;
1.1.1.3 root 1581:
1.1.1.4 root 1582: strcpy (instrname, lookup->name);
1583: ccpt = strstr (instrname, "cc");
1.1 root 1584: if (ccpt != 0) {
1.1.1.4 root 1585: strncpy (ccpt, ccnames[dp->cc], 2);
1.1 root 1586: }
1.1.1.11 root 1587: fprintf (f, "%s", instrname);
1.1.1.3 root 1588: switch (dp->size){
1.1.1.11 root 1589: case sz_byte: fprintf (f, ".B "); break;
1590: case sz_word: fprintf (f, ".W "); break;
1591: case sz_long: fprintf (f, ".L "); break;
1592: default: fprintf (f, " "); break;
1.1 root 1593: }
1594:
1595: if (dp->suse) {
1.1.1.4 root 1596: newpc = m68k_getpc () + m68kpc_offset;
1.1.1.11 root 1597: newpc += ShowEA (f, dp->sreg, dp->smode, dp->size, 0);
1.1 root 1598: }
1599: if (dp->suse && dp->duse)
1.1.1.11 root 1600: fprintf (f, ",");
1.1 root 1601: if (dp->duse) {
1.1.1.4 root 1602: newpc = m68k_getpc () + m68kpc_offset;
1.1.1.11 root 1603: newpc += ShowEA (f, dp->dreg, dp->dmode, dp->size, 0);
1.1 root 1604: }
1605: if (ccpt != 0) {
1606: if (cctrue(dp->cc))
1.1.1.11 root 1607: fprintf (f, " == %08lx (TRUE)", newpc);
1.1.1.3 root 1608: else
1.1.1.11 root 1609: fprintf (f, " == %08lx (FALSE)", newpc);
1.1 root 1610: } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1.1.1.11 root 1611: fprintf (f, " == %08lx", newpc);
1612: fprintf (f, "\n");
1.1 root 1613: }
1.1.1.4 root 1614: if (nextpc)
1615: *nextpc = m68k_getpc () + m68kpc_offset;
1.1 root 1616: }
1617:
1.1.1.11 root 1618: void m68k_dumpstate (FILE *f, uaecptr *nextpc)
1.1 root 1619: {
1620: int i;
1.1.1.3 root 1621: for (i = 0; i < 8; i++){
1.1.1.11 root 1622: fprintf (f, "D%d: %08lx ", i, m68k_dreg(regs, i));
1623: if ((i & 3) == 3) fprintf (f, "\n");
1.1.1.3 root 1624: }
1625: for (i = 0; i < 8; i++){
1.1.1.11 root 1626: fprintf (f, "A%d: %08lx ", i, m68k_areg(regs, i));
1627: if ((i & 3) == 3) fprintf (f, "\n");
1.1 root 1628: }
1.1.1.2 root 1629: if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1630: if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1631: if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1.1.1.11 root 1632: fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1633: regs.usp,regs.isp,regs.msp,regs.vbr);
1634: fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1635: regs.t1, regs.t0, regs.s, regs.m,
1636: GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1.1.1.3 root 1637: for (i = 0; i < 8; i++){
1.1.1.11 root 1638: fprintf (f, "FP%d: %g ", i, regs.fp[i]);
1639: if ((i & 3) == 3) fprintf (f, "\n");
1.1 root 1640: }
1.1.1.11 root 1641: fprintf (f, "N=%d Z=%d I=%d NAN=%d\n",
1642: (regs.fpsr & 0x8000000) != 0,
1643: (regs.fpsr & 0x4000000) != 0,
1644: (regs.fpsr & 0x2000000) != 0,
1645: (regs.fpsr & 0x1000000) != 0);
1.1.1.3 root 1646:
1.1.1.11 root 1647: m68k_disasm (f, m68k_getpc (), nextpc, 1);
1.1.1.4 root 1648: if (nextpc)
1.1.1.11 root 1649: fprintf (f, "next PC: %08lx\n", *nextpc);
1.1 root 1650: }
1.1.1.14 root 1651:
1652:
1653: /* CPU save/restore code */
1654:
1655: #define CPUTYPE_EC 1
1656: #define CPUMODE_HALT 1
1657:
1658: uae_u8 *restore_cpu (uae_u8 *src)
1659: {
1660: int i,model,flags;
1661: uae_u32 l;
1662:
1663: model = restore_u32();
1664: switch (model) {
1665: case 68000:
1666: currprefs.cpu_level = 0;
1667: break;
1668: case 68010:
1669: currprefs.cpu_level = 1;
1670: break;
1671: case 68020:
1672: currprefs.cpu_level = 2;
1673: break;
1674: default:
1675: write_log ("Unknown cpu type %d\n", model);
1676: break;
1677: }
1678:
1679: flags = restore_u32();
1680: currprefs.address_space_24 = 0;
1681: if (flags & CPUTYPE_EC)
1682: currprefs.address_space_24 = 1;
1683: for (i = 0; i < 15; i++)
1684: regs.regs[i] = restore_u32 ();
1685: regs.pc = restore_u32 ();
1.1.1.20 root 1686: regs.irc = restore_u16 ();
1687: regs.ir = restore_u16 ();
1.1.1.14 root 1688: regs.usp = restore_u32 ();
1689: regs.isp = restore_u32 ();
1690: regs.sr = restore_u16 ();
1691: l = restore_u32();
1.1.1.18 root 1692: if (l & CPUMODE_HALT) {
1.1.1.14 root 1693: regs.stopped = 1;
1.1.1.18 root 1694: set_special (SPCFLAG_STOP);
1695: } else
1.1.1.14 root 1696: regs.stopped = 0;
1697: if (model >= 68010) {
1698: regs.dfc = restore_u32 ();
1699: regs.sfc = restore_u32 ();
1700: regs.vbr = restore_u32 ();
1701: }
1702: if (model >= 68020) {
1703: caar = restore_u32 ();
1704: cacr = restore_u32 ();
1705: regs.msp = restore_u32 ();
1706: }
1707: write_log ("CPU %d%s%03d, PC=%08.8X\n",
1708: model/1000, flags & 1 ? "EC" : "", model % 1000, regs.pc);
1709:
1710: return src;
1711: }
1712:
1713: static int cpumodel[] = { 68000, 68010, 68020, 68020 };
1714:
1715: uae_u8 *save_cpu (int *len)
1716: {
1717: uae_u8 *dstbak,*dst;
1718: int model,i;
1719:
1720: dstbak = dst = malloc(4+4+15*4+4+4+4+4+2+4+4+4+4+4+4+4);
1721: model = cpumodel[currprefs.cpu_level];
1722: save_u32 (model); /* MODEL */
1723: save_u32 (currprefs.address_space_24 ? 1 : 0); /* FLAGS */
1724: for(i = 0;i < 15; i++) save_u32 (regs.regs[i]); /* D0-D7 A0-A6 */
1725: save_u32 (m68k_getpc ()); /* PC */
1.1.1.20 root 1726: save_u16 (regs.irc); /* prefetch */
1727: save_u16 (regs.ir); /* instruction prefetch */
1.1.1.14 root 1728: MakeSR ();
1729: save_u32 (!regs.s ? regs.regs[15] : regs.usp); /* USP */
1730: save_u32 (regs.s ? regs.regs[15] : regs.isp); /* ISP */
1731: save_u16 (regs.sr); /* SR/CCR */
1732: save_u32 (regs.stopped ? CPUMODE_HALT : 0); /* flags */
1733: if(model >= 68010) {
1734: save_u32 (regs.dfc); /* DFC */
1735: save_u32 (regs.sfc); /* SFC */
1736: save_u32 (regs.vbr); /* VBR */
1737: }
1738: if(model >= 68020) {
1739: save_u32 (caar); /* CAAR */
1740: save_u32 (cacr); /* CACR */
1741: save_u32 (regs.msp); /* MSP */
1742: }
1743: *len = dst - dstbak;
1744: return dstbak;
1745: }
1.1.1.20 root 1746:
1747: static void exception3f (uae_u32 opcode, uaecptr addr, uaecptr fault, int writeaccess, int instructionaccess)
1748: {
1749: last_addr_for_exception_3 = addr;
1750: last_fault_for_exception_3 = fault;
1751: last_op_for_exception_3 = opcode;
1752: last_writeaccess_for_exception_3 = writeaccess;
1753: last_instructionaccess_for_exception_3 = instructionaccess;
1754: Exception (3, fault);
1755: }
1756:
1757: void exception3 (uae_u32 opcode, uaecptr addr, uaecptr fault)
1758: {
1759: exception3f (opcode, addr, fault, 0, 0);
1760: }
1761:
1762: void exception3i (uae_u32 opcode, uaecptr addr, uaecptr fault)
1763: {
1764: exception3f (opcode, addr, fault, 0, 1);
1765: }
1766:
1767: void exception2 (uaecptr addr, uaecptr fault)
1768: {
1769: write_log ("delayed exception2!\n");
1770: regs.panic_pc = m68k_getpc();
1771: regs.panic_addr = addr;
1772: regs.panic = 2;
1773: set_special (SPCFLAG_BRK);
1774: m68k_setpc (0xf80000);
1775: fill_prefetch_slow ();
1776: }
1777:
1778: void cpureset (void)
1779: {
1780: customreset ();
1781: #if 0
1782: uae_u16 ins;
1783: if (currprefs.cpu_level == 0 && (currprefs.cpu_compatible || currprefs.cpu_cycle_exact)) {
1784: customreset ();
1785: return;
1786: }
1787: ins = get_word (m68k_getpc() + 2);
1788: if ((ins & ~7) == 0x4ed0) {
1789: int reg = ins & 7;
1790: uae_u32 addr = m68k_areg (regs, reg);
1791: write_log ("reset/jmp (ax) combination emulated\n");
1792: customreset ();
1793: if (addr < 0x80000)
1794: addr += 0xf80000;
1795: m68k_setpc (addr);
1796: }
1797: #endif
1798: }
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.