--- uae/src/table68k 2018/04/24 16:39:52 1.1.1.3 +++ uae/src/table68k 2018/04/24 17:18:16 1.1.1.7 @@ -9,6 +9,7 @@ % J: immediate 0..15 % k: immediate 0..7 % K: immediate 0..63 +% p: immediate 0..3 (CINV and CPUSH: cache field) % s: source mode % S: source reg % d: dest mode @@ -24,13 +25,18 @@ % % Arp: --> -(Ar) % ArP: --> (Ar)+ +% L: (xxx.L) % % Fields on a line: % 16 chars bitpattern : -% CPU level / privildge level : +% CPU level / privilege level : % CPU level 0: 68000 % 1: 68010 % 2: 68020 +% 3: 68030 +% 4: 68040 +% 5: 68060 (not used to produce a cputbl) +% [Everything from 68020 possibly allows for FPU emulation] % privilege level 0: not privileged % 1: unprivileged only on 68000 (check regs.s) % 2: privileged (check regs.s) @@ -96,7 +102,7 @@ 0011 DDDd ddss sSSS:00:-----:-----:12: MOVEA.W s,d[Areg] 0011 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.W s,d[!Areg] -0100 0000 zzdd dDDD:00:XxZxC:-----:30: NEGX.z d[!Areg] +0100 0000 zzdd dDDD:00:XxZxC:X-Z--:30: NEGX.z d[!Areg] 0100 0000 11dd dDDD:01:?????:?????:10: MVSR2.W d[!Areg] 0100 0010 zzdd dDDD:00:-0100:-----:20: CLR.z d[!Areg] 0100 0010 11dd dDDD:10:?????:?????:10: MVSR2.B d[!Areg] @@ -142,12 +148,14 @@ 0100 1110 11ss sSSS:00://///://///:80: JMP.L s[!Dreg,Areg,Aipi,Apdi,Immd] 0100 rrr1 11ss sSSS:00:-----:-----:02: LEA.L s[!Dreg,Areg,Aipi,Apdi,Immd],Ar -0101 jjj0 zzdd dDDD:00:-----:-----:13: ADDA.z #j,d[Areg] +0101 jjj0 01dd dDDD:00:-----:-----:13: ADDA.W #j,d[Areg] +0101 jjj0 10dd dDDD:00:-----:-----:13: ADDA.L #j,d[Areg] 0101 jjj0 zzdd dDDD:00:XNZVC:-----:13: ADD.z #j,d[!Areg] -0101 jjj1 zzdd dDDD:00:-----:-----:13: SUBA.z #j,d[Areg] +0101 jjj1 01dd dDDD:00:-----:-----:13: SUBA.W #j,d[Areg] +0101 jjj1 10dd dDDD:00:-----:-----:13: SUBA.L #j,d[Areg] 0101 jjj1 zzdd dDDD:00:XNZVC:-----:13: SUB.z #j,d[!Areg] -0101 cccc 1100 1rrr:00:-----:+++++:31: DBcc.W Dr,#1 -0101 cccc 11dd dDDD:00:-----:+++++:20: Scc.B d[!Areg] +0101 cccc 1100 1rrr:00:-----:-++++:31: DBcc.W Dr,#1 +0101 cccc 11dd dDDD:00:-----:-++++:20: Scc.B d[!Areg] 0101 cccc 1111 1010:20:?????:?????:10: TRAPcc #1 0101 cccc 1111 1011:20:?????:?????:10: TRAPcc #2 0101 cccc 1111 1100:20:?????:?????:00: TRAPcc @@ -158,9 +166,9 @@ 0110 0001 0000 0000:00://///://///:40: BSR.W #1 0110 0001 IIII IIII:00://///://///:40: BSR.B #i 0110 0001 1111 1111:00://///://///:40: BSR.L #2 -0110 CCCC 0000 0000:00:-----:+++++:40: Bcc.W #1 -0110 CCCC IIII IIII:00:-----:+++++:40: Bcc.B #i -0110 CCCC 1111 1111:00:-----:+++++:40: Bcc.L #2 +0110 CCCC 0000 0000:00:-----:-++++:40: Bcc.W #1 +0110 CCCC IIII IIII:00:-----:-++++:40: Bcc.B #i +0110 CCCC 1111 1111:00:-----:-++++:40: Bcc.L #2 0111 rrr0 iiii iiii:00:-NZ00:-----:12: MOVE.L #i,Dr @@ -228,15 +236,33 @@ 1110 1111 11ss sSSS:20:?????:?????:13: BFINS #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16] % floating point co processor -1111 0010 00ss sSSS:30:?????:?????:11: FPP #1,s -1111 0010 01ss sSSS:30:?????:?????:11: FDBcc #1,s[Areg-Dreg] -1111 0010 01ss sSSS:30:?????:?????:11: FScc #1,s[!Areg,Immd,PC8r,PC16] -1111 0010 0111 1010:30:?????:?????:10: FTRAPcc #1 -1111 0010 0111 1011:30:?????:?????:10: FTRAPcc #2 -1111 0010 0111 1100:30:?????:?????:00: FTRAPcc -1111 0010 10KK KKKK:30:?????:?????:11: FBcc #K,#1 -1111 0010 11KK KKKK:30:?????:?????:11: FBcc #K,#2 -1111 0011 00ss sSSS:32:?????:?????:20: FSAVE s[!Dreg,Areg,Aipi,Immd,PC8r,PC16] -1111 0011 01ss sSSS:32:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd] - -1111 0000 00ss sSSS:40:?????:?????:11: MMUOP #1,s +1111 0010 00ss sSSS:20:?????:?????:11: FPP #1,s +1111 0010 01ss sSSS:20:?????:?????:11: FDBcc #1,s[Areg-Dreg] +1111 0010 01ss sSSS:20:?????:?????:11: FScc #1,s[!Areg,Immd,PC8r,PC16] +1111 0010 0111 1010:20:?????:?????:10: FTRAPcc #1 +1111 0010 0111 1011:20:?????:?????:10: FTRAPcc #2 +1111 0010 0111 1100:20:?????:?????:00: FTRAPcc +1111 0010 10KK KKKK:20:?????:?????:11: FBcc #K,#1 +1111 0010 11KK KKKK:20:?????:?????:11: FBcc #K,#2 +1111 0011 00ss sSSS:22:?????:?????:20: FSAVE s[!Dreg,Areg,Aipi,Immd,PC8r,PC16] +1111 0011 01ss sSSS:22:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd] + +% 68030 MMU (allowed addressing modes not checked!) +1111 0000 00ss sSSS:30:?????:?????:11: MMUOP30A s[!Immd],#1 +1111 1000 00ss sSSS:30:?????:?????:11: MMUOP30B s[!Immd] +% Misc MMU +1111 0101 iiii iSSS:40:?????:?????:11: MMUOP #i,s + +% 68040 instructions +1111 0100 pp00 1rrr:42:-----:-----:02: CINVL #p,Ar +1111 0100 pp01 0rrr:42:-----:-----:02: CINVP #p,Ar +1111 0100 pp01 1rrr:42:-----:-----:00: CINVA #p +1111 0100 pp10 1rrr:42:-----:-----:02: CPUSHL #p,Ar +1111 0100 pp11 0rrr:42:-----:-----:02: CPUSHP #p,Ar +1111 0100 pp11 1rrr:42:-----:-----:00: CPUSHA #p +% destination register number is encoded in the following word +1111 0110 0010 0rrr:40:-----:-----:12: MOVE16 ArP,AxP +1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Dreg-Aipi],L +1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 L,d[Areg-Aipi] +1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Aind],L +1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 L,d[Aipi-Aind]