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Annotation of xinu/h/clock.h, revision 1.1.1.1

1.1       root        1: /* clock.h--format of memory mapped registers for timer part of 68230 PI/T */
                      2: 
                      3: struct timercsr {
                      4:   unsigned char tcsr;          /* timer control reg */
                      5:   char dummy1; 
                      6:   unsigned char tivr;          /* timer interrupt vector addr */
                      7:   char dummy2;
                      8:   unsigned char cpr_null;      /* r/w but noop 4th byte for cpr */
                      9:   char dummy3;
                     10:   unsigned char cpr_high;      /* high byte of counter preload reg */
                     11:   char dummy4;
                     12:   unsigned char cpr_med;       /* middle byte of counter preload reg */
                     13:   char dummy5;
                     14:   unsigned char cpr_low;       /* low byte of counter preload reg */
                     15:   char dummy6;
                     16:   unsigned char cnt_null;      /* r/w but noop 4th byte for counter reg */
                     17:   char dummy7;
                     18:   unsigned char cnt_high;      /* high byte, counter--read with clock off */
                     19:   char dummy8;
                     20:   unsigned char cnt_med;       /* mid. byte, counter--read with clock off */
                     21:   char dummy9;
                     22:   unsigned char cnt_low;       /* low byte, counter--read with clock off */
                     23:   char dummy10;
                     24:   unsigned char tstat;         /* bit 0 is zero-detect, rest read as 0 */
                     25:                                /* write 1 to this byte to acknowledge tick */
                     26: };
                     27: 
                     28: /* the memory-mapped location of timer registers, determined by digital */
                     29: /* logic wired onto the mecb--(would be at higher adddress on bigger sys) */
                     30: #define TIMER ((struct timercsr *)0x10021)
                     31: 
                     32: /* bit defs for tcr (timer control register)-- */
                     33: #define CLOCKIE (5<<5)         /* user vectoring, int enabled */
                     34: #define CLOCKDE (4<<5)         /* user vectoring, int disabled */
                     35: #define LOADFROMCPR (0<<4)     /* when count hits 0 */
                     36: #define LETROLLOVER (1<<4)     /* don't use CPR, just let it roll over */
                     37: #define PRESCALE32 (0<<1)      /* count every 32 clock cycles */
                     38:                                /* 1<<1 thru 3<<2 all involve a */
                     39:                                /* pin on port C, for external clocking */
                     40: #define CLOCKON (1<<0)         /* clock running */
                     41: #define CLOCKOFF (0<<0)                /* clock not running */
                     42: 
                     43: /* Note: since PRESCALE32 is the only internal-only setting for bits 1-2, */
                     44: /* we have as a result a timer downcounting every 32 cycles of the 4 Mhz  */
                     45: /* crystal, i.e, 8 usecs/downcount, or 125,000 downcounts/second          */
                     46: 

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