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1.1 root 1: /* deqna.h */
2:
3: /* Definitions Digital Equipment Corporation's DEQNA Ethernet interface */
4:
5: /* Device register layout */
6:
7: struct dqregs { /* deqna registers in I/O space */
8: unsigned short d_addr; /* when read, low order byte of */
9: unsigned short d_addr2; /* these and next 4 regs give */
10: /* 6-byte Ethernet node address*/
11: unsigned short d_rcmd; /* list of read cmds in memory */
12: unsigned short d_rcmdh; /* high order bits of d_rcmd */
13: unsigned short d_wcmd; /* list of write cmds in memory */
14: unsigned short d_wcmdh; /* high order bits of d_wcmd */
15: unsigned short d_vect; /* interrupt vector address */
16: unsigned short d_csr; /* control and status register */
17: };
18:
19: /* Bits in the Control and Status Register */
20:
21: #define DQ_ENBL 0000001 /* Receiver enable */
22: #define DQ_REST 0000002 /* Software reset */
23: #define DQ_NXMI 0000004 /* Nonexistent memory interrupt */
24: #define DQ_BROM 0000010 /* Fetch boot/diagnostic ROM */
25: #define DQ_XLI 0000020 /* Xmit list invalid */
26: #define DQ_RLI 0000040 /* Receive list invalid */
27: #define DQ_IEN 0000100 /* Interrupt Enable */
28: #define DQ_XINT 0000200 /* Xmit interrupt */
29: #define DQ_ILOP 0000400 /* Internal loopback mode */
30: #define DQ_ELOP 0001000 /* External loopback mode */
31: #define DQ_TIME 0002000 /* Sanity timer enable */
32: #define DQ_RES1 0004000 /* Vendor reserved */
33: #define DQ_FUSE 0010000 /* Fuse OK */
34: #define DQ_CARR 0020000 /* Carrier present on ether */
35: #define DQ_RES2 0040000 /* Vendor reserved */
36: #define DQ_RINT 0100000 /* Receive interrupt */
37:
38: /* Command to device as it appears on buffer descriptor list in memory */
39:
40: struct dcmd { /* DEQNA command in memory */
41: unsigned short dc_flag; /* flag word marked USED/UNUSED */
42: unsigned short dc_bufh; /* desc.+ high buf. addr. bits */
43: unsigned short dc_buf; /* buffer addr. (low order bits)*/
44: unsigned short dc_len; /* buffer length (see manual) */
45: unsigned short dc_st1; /* Status word 1 */
46: unsigned short dc_st2; /* Status word 2 */
47: };
48:
49: /* Bits in the flag word of dcm */
50:
51: #define DC_NUSED 0100000 /* This dcmd entry not in use */
52: #define DC_USED 0140000 /* DEQNA using this dcmd entry */
53:
54: /* Bits in the descriptor word of dcm (i.e. in dc_bufh) */
55:
56: #define DC_VALID 0100000 /* This is a valid buffer addr. */
57: #define DC_CADDR 0040000 /* This is a chain address */
58: #define DC_ENDM 0020000 /* Xmit: end of message */
59: #define DC_SETUP 0010000 /* Xmit: setup packet */
60: #define DC_NORM 0000000 /* Xmit: non-setup packet */
61: #define DC_ENDL 0000000 /* Last descriptor in list */
62: #define DC_XRES 0007400 /* Vendor reserved */
63: #define DC_LBIT 0000200 /* Buffer ends on odd address */
64: #define DC_HBIT 0000100 /* Buffer starts on odd address */
65:
66: /* Bits returned to first status word (dc_st1) */
67:
68: #define DC_LUSE 0140000 /* LAST/USE bits (see manual) */
69: #define DC_INIT 0100000 /* Initial value of status word */
70: #define DC_ERRU 0040000 /* ERROR/USED bit (see manual) */
71: #define DC_LOSS 0010000 /* Xmit: lost carrier */
72: #define DC_NCAR 0004000 /* Xmit: no carrier */
73: #define DC_ST16 0002000 /* Xmit: timer enabled */
74: #define DC_ABRT 0001000 /* Xmit: abort */
75: #define DC_FAIL 0000400 /* Xmit: heartbeat failure */
76: #define DC_CCNT 0000360 /* Xmit: collision count */
77: #define DC_ESET 0020000 /* Recv: setup packet */
78: #define DC_DISC 0010000 /* Recv: discard packet */
79: #define DC_RUNT 0004000 /* Recv: runt packet (too short)*/
80: #define DC_HLEN 0003400 /* Recv: bits 10:8 of rec. len. */
81: #define DC_LLEN 0000377 /* Recv: bits 7:0 of rec. len. */
82: #define DC_XLEN 60 /* manual says add 60 to len... */
83: #define DC_RRES 0000370 /* Recv: vendor reserved */
84: #define DC_FRAM 0000004 /* Recv: frame alignment */
85: #define DC_CERR 0000002 /* Recv: CRC error */
86: #define DC_OVER 0000001 /* Recv: overflow error */
87:
88: /* Definitions of device setup packet (see manual for details) */
89:
90: #define DQ_ROWS 16 /* setup has 16 rows */
91: #define DQ_COLS 8 /* setup has 8 columns */
92: #define DQ_SETD 8 /* displacement of 2nd copy */
93: #define DQ_BCST 0377 /* broadcast address bytes */
94:
95: #define dqlen(x) (short) (-(((x)+1)>>1))/* buffer len: map byte length */
96: /* to 2s compl. of word length */
97:
98: #define DQ_RTO 300 /* maximum time to wait for read*/
99:
100: struct dqsetup { /* deqna setup packet strructure*/
101: char dq_set[DQ_ROWS][DQ_COLS];/* holds one setup packet */
102: char dq_echo[DQ_ROWS][DQ_COLS];/* holds echo of packet */
103: char dq_crc[4]; /* allow deqna extra 4 bytes */
104: };
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