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Annotation of xinu/h/intvectors_mecb.h, revision 1.1.1.1

1.1       root        1: /* intvectors_mecb.h: header file for interrupt programming on mecb */
                      2: 
                      3: typedef int (*intvec) ();      /* an intvec is a ptr to a fn */
                      4: 
                      5: /* each vector is at address = 4*(intvec slot #) */
                      6: /* for ex. the console is at vec slot 29, at address 4*29=116=0x74 */
                      7: 
                      8: #define SPURVEC (*(intvec *)0x60) /* spurious interrupt */
                      9: #define SLUVEC1 (*(intvec *)0x74)  /* the SLU1 int vec at addr 0x74: console */
                     10: #define SLU1LEV 5              /* interrupt level for SLU1 */
                     11: #define SLUVEC2 (*(intvec *)0x78) /* SLU2 int vec: "host line" */
                     12: #define SLU2LEV 6              /* int lev for SLU2 */
                     13: #define ABORTVEC (*(intvec *)0x7c) /* int vec for abort interrupt */
                     14: #define ABORTLEV 7             /* nonmaskable, even at CPU pri 7 */
                     15: 
                     16: /* the location of the PI/T timer int vector, in user vector area, 100-3fc-- */
                     17: #define CLOCKVECADDRESS ((intvec *)0x100)   /* we choose this, in 100-3fc */
                     18: 
                     19: /* the int vector itself--at location we chose-- */
                     20: #define CLOCKVEC (*(intvec *)CLOCKVECADDRESS)
                     21: #define CLOCKLEV 2
                     22: 
                     23: /* The parallel port uses level 3--in block of four vectors,             */
                     24: /*   with base address binary XXXXXX0000, XXXXXX from pivr.              */
                     25: /*   Then during interrupt cycle, 68230 sets bits 2 and 3 based          */
                     26: /*   on specific PI event:  00 for H1 event, 01 for H2, 10 for H3, 11 for H4*/
                     27: /*   so we end up with 4 interrupt vectors, one for each handshake line  */
                     28: /*   but the MECB has output buffering on H2 and H4, so only H1 and H3   */
                     29: /*   are really usable for interrupts                                    */
                     30: #define PI_BASEVECADDRESS ((intvec *)0x110)   /* we choose this, in 100-3fc */
                     31: #define PI_H1VECADDRESS PI_BASEVECADDRESS   /* H1 is 0'th of the four */
                     32: #define PI_H3VECADDRESS (PI_BASEVECADDRESS+2) /* H3 is 2nd of the four */
                     33: 
                     34: /* the int vectors themselves--at locations specified above-- */
                     35: #define PI_H1VEC (*(intvec *)PI_H1VECADDRESS)
                     36: #define PI_H3VEC (*(intvec *)PI_H3VECADDRESS)
                     37: #define PILEV 3
                     38: 
                     39: 
                     40: /*  Assembly language envelope routines are available in the mecb
                     41: library for the interrupt handlers needed for each of the vectors
                     42: defined above.   For example, for the console, SLU1, device, there
                     43: is:
                     44: .globl _slu1int                        | make _slu1int extern
                     45:  
                     46:  _slu1int: movel a0,sp@-               | save C scratch regs
                     47:        movel a1,sp@-
                     48:        movel d0,sp@-
                     49:        movel d1,sp@-           | (or use movem for better performance)
                     50:        jsr _slu1intc           | C will save other regs on entry to routine
                     51:        movel sp@+,d1
                     52:        movel sp@+,d0
                     53:        movel sp@+,a1
                     54:        movel sp@+,a0
                     55:        rte                     | return from interrupt
                     56: 
                     57: Similar routines are available for:
                     58: slu2int, calling slu2intc
                     59: clockint, calling clockintc
                     60: spurint, calling spurintc
                     61: */

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