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1.1 root 1: /* procreg.h -- constants associated with DEC processor register mnemonics */
2:
3: #define ASM /* mark for other .h files */
4: #include <conf.h>
5:
6: /* VAX privileged processor registers -- accessed via mtpr and mfpr */
7: #define KSP 0x0 /* kernel stack pointer */
8: #define ESP 0x1 /* executive stack pointer */
9: #define SSP 0x2 /* supervisor stack pointer */
10: #define USP 0x3 /* user stack pointer */
11: #define ISP 0x4 /* interrupt stack pointer */
12: #define P0BR 0x8 /* p0 base register */
13: #define P0LR 0x9 /* p0 length register */
14: #define P1BR 0xa /* p1 base register */
15: #define P1LR 0xb /* p1 length register */
16: #define SBR 0xc /* system base register */
17: #define SLR 0xd /* system length register */
18: #define PCBB 0x10 /* process control block base */
19: #define SCBB 0x11 /* system control block base */
20: #define IPL 0x12 /* interrupt priority level */
21: #define ASTLVL 0x13 /* asynchronous system trap level */
22: #define SIRR 0x14 /* software interrupt request */
23: #define SISR 0x15 /* software interrupt summary */
24: #define CMIER 0x17 /* CMI error (750/751) */
25: #define MCSR 0x17 /* machine check status register */
26: #define ICCS 0x18 /* interval clock control/status */
27: #define NICR 0x19 /* next interval count */
28: #define ICR 0x1a /* interval count */
29: #define TODR 0x1b /* time of day */
30: #define CSRS 0x1c /* console storage receive/status */
31: #define CSDR 0x1d /* console storage receive data */
32: #define CSTS 0x1e /* console storage transmit/status */
33: #define CSTD 0x1f /* console storage transmit data */
34: #define RXCS 0x20 /* console receive control/status */
35: #define RXDB 0x21 /* console receive data buffer */
36: #define TXCS 0x22 /* console transmit control/status */
37: #define TXDB 0x23 /* console transmit data buffer */
38: #define TBDR 0x24 /* translation buffer disable */
39: #define CADR 0x25 /* cache disable */
40: #define MCESR 0x26 /* machine check error summary */
41: #define CAER 0x27 /* cache error */
42: #define ACCS 0x28 /* accelerator control/status */
43: #define IUR 0x37 /* init unibus or Q-bus register */
44: #define MAPEN 0x38 /* memory management enable */
45: #define TBIA 0x39 /* translation buffer invalidate all*/
46: #define TBIS 0x3a /* trans. buffer invalidate single */
47: #define TB 0x3b /* translation buffer */
48: #define PMR 0x3d /* performance monitor enable */
49: #define SID 0x3e /* system identification */
50: #define TBCHK 0x3f /* translation buffer check */
51:
52: #if defined(VAX785)||defined(VAX780)
53: #define ACCR 0x29 /* accelerator maintenance */
54: #define WCSA 0x2c /* WCS address */
55: #define WCSD 0x2d /* WCS data */
56: #define SBIFS 0x30 /* SBI fault and status */
57: #define SBIS 0x31 /* SBI silo */
58: #define SBISC 0x32 /* SBI silo comparator */
59: #define SBIMT 0x33 /* SBI maintenance */
60: #define SBIER 0x34 /* SBI error register */
61: #define SBITA 0x35 /* SBI timeout address */
62: #define SBIQC 0x36 /* SBI quadword clear */
63: #define MBRK 0x3c /* microcode breakpoint */
64: #endif
65:
66: #if defined(VAX8600)
67: #define PAMACC 0x40 /* physical address memory access */
68: #define PAMLOC 0x41 /* physical address memory location */
69: #define CSWP 0x42 /* cache sweep */
70: #define MDECC 0x43 /* mbox data ecc */
71: #define MENA 0x44 /* mbox error enable */
72: #define MDCTL 0x45 /* mbox data control */
73: #define MCCTL 0x46 /* mbox mcc control */
74: #define MERG 0x47 /* mbox error generator */
75: #define CRBT 0x48 /* console reboot */
76: #define DFI 0x49 /* diagnostic fault insertion */
77: #define EHSR 0x4a /* error handling status */
78: #define STXCS 0x4c /* storage transmit control/status */
79: #define STXDB 0x4d /* storage transmit data buffer */
80: #define ESPA 0x4e /* ebox scratchpad address */
81: #define ESPD 0x4f /* ebox scratchpad data */
82: #endif
83:
84: /* masks for processor registers */
85: #define DISABLE 0x1f /* IPL to disable interrupts */
86: #define ENABLE 0x0 /* IPL to enable interrupts */
87: #define NOMAP 0x0 /* value to disable memory mapping */
88: #define MAP 0x1 /* value to enable memory mapping */
89: #define MCESRCLR 0xd /* value to clear MCESR */
90: #define IURSET 0x1 /* value to init bus */
91: #define IURUNSET 0x0 /* value to uninit bus */
92:
93: #if defined(VAX780) || defined(VAX785)
94: #define SBIFSCLR 0 /* value to clear SBIFS */
95: #endif
96:
97: #if defined(VAX8600)
98: #define CACHCLR 0xb /* flush cache, no write-through */
99: #endif
100:
101: #define LOWREGS 0x3f /* mask for saving registers r5-r0 */
102: #define NLOWREG 6 /* number of regs saved w LOWREGS */
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