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Annotation of xinu/h/slu6850.h, revision 1.1.1.1

1.1       root        1: /* slu6850.h--register defs for Motorola 6850 SLU chip */
                      2: /* MC6850 Serial Line Unit (also known as UART, or ACIA) */
                      3: /* MECB has two of these for console and hostline, each with jumpered
                      4:    baudrate up to 9600 baud */
                      5: /* ATT7300 has one for serial keyboard interface, baudrate hardwired
                      6:    for 1200 baud, so not used as console */
                      7: 
                      8: /* control register bits-- */
                      9: #define SLURESET       3               /* write to cntrl reg to reset dev */
                     10: #define SLUDIV16       1               /* division ratio of 16--normal op */
                     11: #define SLUFMTBITS      (7<<2)         /* 3 bits--8 formats, 2 def'd here--*/
                     12: #define SLU8NP1         (5<<2)         /* dataformat of 8 bits, no parity,
                     13:                                           one stop bit (most common) */
                     14: #define SLU7EP1                (2<<2)          /* dataformat of 7 bits, even parity,
                     15:                                           one stop bit (second most common)*/
                     16: #define SLUTRANSBITS    (3<<5)         /* 2 bits--following 4 cases-- */
                     17: #define SLUTRANSDE0    (0<<5)          /* no transmitter interrupt, RTS*=0 */
                     18: #define SLUTRANSDE1    (2<<5)          /* no transmitter int, RTS*=1 */
                     19: #define SLUTRANSIE     (1<<5)          /* transmit int ena:bit5 on,bit6 off*/
                     20: #define SLUBREAK       (3<<5)          /* no trans int, send break signal 
                     21:                                           (continuous space logic level) */
                     22: #define SLURECVDE      (0<<7)          /* no receiver int */
                     23: #define SLURECVIE      (1<<7)          /* receiver int enabled */
                     24: #define SLUINTBITS      (7<<5)          /* all off for no ints, RTS*=0 */
                     25: #define SLUDEFAULT     (SLURECVDE|SLUTRANSDE0|SLU8NP1|SLUDIV16)
                     26:                                        /* counter divide 16, dataformat of
                     27:                                           8 bits, no parity, 1 stop bit,
                     28:                                           RTS*=0, no interrupts */
                     29: /* status register bits-- */
                     30: #define SLURECVREADY   (1<<0)          /* receiver ready bit */
                     31: #define        SLUTRANSREADY   (1<<1)          /* transmitter ready bit */
                     32: #define SLUDCD         (1<<2)          /* data carrier detect bit (always 0
                     33:                                           on mecb--DCD pin is wired to gnd)*/
                     34: #define SLUCTS         (1<<3)          /* clear to send bit--reports logic
                     35:                                           level on CTS pin, wired to DTR on
                     36:                                           console, CTS on hostline port */
                     37: #define SLUFE          (1<<4)          /* framing error (bad stop bit) */
                     38: #define SLUOVRN                (1<<5)          /* overrun err--input char was lost */
                     39: #define SLUPE          (1<<6)          /* parity err--can't happen in 8NP1 */
                     40: #define SLUIRQ         (1<<7)          /* 6850 signaling trans or recv int */
                     41: #define        SLUERMASK       (SLUPE|SLUOVRN|SLUFE) /* mask for error flags */
                     42: 
                     43: /* for receive register-- */
                     44: #define        SLUCHMASK       0xff            /* mask for input character     */
                     45: #define SLUASCII7BITS   0x7f           /* mask for 7 bits of ASCII char,
                     46:                                          to mask off parity bit */
                     47: 
                     48: /* MC6850 device register layout       */
                     49: /* The 6850 uses 2 memory-mapped byte register locations, at addr n,n+2 */
                     50: /* for example, on MECB-- */
                     51: /* 10040: port 1 csr (control and status register) */
                     52: /* 10041: port 2 csr */
                     53: /* 10042: port 1 data buf */
                     54: /* 10043: port 2 data buf */
                     55: /* so look at it as port 1-- csr, dummy, data buf starting at 10040 */
                     56: /*        and       port 2-- csr, dummy, data buf starting at 10041 */
                     57: /* Further, each address accesses 2 different hardware registers */
                     58: /*  in the chip, one on read and another on write. */
                     59: /* 10040, 10041-- status register on read, control register on write */
                     60: /* 10042, 10043-- read buffer on read, write buffer on write */
                     61: 
                     62: struct csr     {
                     63:        unsigned char cstat;    /* read for status, write for control reg */
                     64:        char dummy;       /* skip a byte--only uses even, or odd, addrs */
                     65:        unsigned char cbuf;     /* write for transmit, read for input */
                     66: };
                     67: 

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