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Annotation of xinu/h/sluaccess6850.h, revision 1.1

1.1     ! root        1: /* sluaccess6850.h */
        !             2: /* access macros for the MECB Serial Line Unit */
        !             3: /* The specific chip is the MC6850, by Motorola */
        !             4: 
        !             5: /* get/set_control_reg6850 and slu_init6850 are in the SA and Xinu
        !             6:    libraries to provide an effectively-readable UART control register
        !             7:    even though the hardware SLU (Motorola 6850 "ACIA")
        !             8:    has a write-only control reg.  They simply maintain a copy of the bits
        !             9:    put into the control reg in a private memory location and supply them
        !            10:    via get_control_reg.  Naturally, this system only works if all accesses
        !            11:    to the hardware control reg. go through this package, incl. init. */
        !            12: /* The transmitter control macros assume that the system is running
        !            13:    SLUTRANSDE0 in SLUTRANSBITS when SLU trans ints are disabled,
        !            14:    SLUTRANSIE when trans ints are enabled.  Since no Xinu system
        !            15:    call allows the user to switch the port to SLUTRANSDE1 (RTS*=1,
        !            16:    not 0), this works fine */
        !            17: 
        !            18: #define sluinitcsr(ioaddr)      slu_init6850(ioaddr)
        !            19: #define slutransready(ioaddr)   ((ioaddr->cstat)&SLUTRANSREADY)
        !            20: #define slurecvready(ioaddr)    ((ioaddr->cstat)&SLURECVREADY)
        !            21: #define slugetch(ioaddr)       ((ioaddr)->cbuf)
        !            22: #define sluputch(ioaddr, ch)   ((ioaddr)->cbuf = (ch))
        !            23: #define slurenable(ioaddr)   set_control_reg6850(ioaddr,get_control_reg6850(ioaddr)|SLURECVIE)
        !            24: #define slurdisable(ioaddr)  set_control_reg6850(ioaddr,get_control_reg6850(ioaddr)&~SLURECVIE)
        !            25: /* avoid turning on interrupts if they are already on--may lose output */
        !            26: #define slutenable(ioaddr)  if ((get_control_reg6850(ioaddr)&SLUTRANSIE)==0) \
        !            27:    set_control_reg6850(ioaddr,get_control_reg6850(ioaddr)|SLUTRANSIE)
        !            28: #define slutdisable(ioaddr)  set_control_reg6850(ioaddr,(get_control_reg6850(ioaddr)&~SLUTRANSIE))
        !            29: /* {slusetbrk, slurstbrk} have side effect of disabling trans ints--
        !            30:    caller should disable trans ints first, reinstate later */
        !            31: #define slusetbrk(ioaddr)       set_control_reg6850(ioaddr,((get_control_reg6850(ioaddr)&~SLUTRANSBITS)|SLUBREAK))
        !            32: #define slurstbrk(ioaddr)       set_control_reg6850(ioaddr,((get_control_reg6850(ioaddr)&~SLUTRANSBITS)|SLUTRANSDE0))
        !            33: #define slugetintstate(ioaddr) get_control_reg6850(ioaddr)&SLUINTBITS
        !            34: #define slusetintstate(ioaddr,oldstate) set_control_reg6850(ioaddr,oldstate| \
        !            35:    (get_control_reg6850(ioaddr)&~SLUINTBITS))
        !            36: 
        !            37: 
        !            38: 

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