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Annotation of xinu/sys/slu7201.c, revision 1.1

1.1     ! root        1: #include <slu7201.h>
        !             2: 
        !             3: /* Package to turn the write-only control registers of each of up to MAXSLU/2
        !             4:    NEC7201 SLUs into effectively read-write registers, and also initialize
        !             5:    the SLU for 8 bits, no parity, 1 stop bit, 9600 baud, no interrupts.
        !             6:    To be effective, all references to the control registers need to go
        !             7:    through this package. */
        !             8: 
        !             9: /* space for 2 sets of saved regs, for each channel of one 7201-- */
        !            10: #define MAXSLU 2
        !            11: 
        !            12: static struct {
        !            13:   struct csr *csrptr;          /* which SLU this is */
        !            14:   char vals[6];                        /* its 6 control reg vals */
        !            15: }soft_control_reg[MAXSLU] = {0};
        !            16: 
        !            17: /* initialize UART regs to do async 8 bits, no parity, 1 stop bit, no ints */
        !            18: /* save control reg settings in soft_control_reg for later access */
        !            19: int slu_init7201(struct csr *csrptr)
        !            20: {
        !            21:   int i;
        !            22: 
        !            23:   /* lookup csr or set up new spot in array-- */
        !            24:   for (i=0;i<MAXSLU;i++) {
        !            25:     if (soft_control_reg[i].csrptr == (struct csr *)0) {
        !            26:       soft_control_reg[i].csrptr = csrptr; /* new spot */
        !            27:       break;
        !            28:     } else if (soft_control_reg[i].csrptr == csrptr)
        !            29:       break;
        !            30:   }
        !            31:   if (i==MAXSLU)
        !            32:     panic("Too many SLU devs for soft_control_reg table");
        !            33: 
        !            34:   csrptr->cstat = 0;           /* select reg 0 */
        !            35:   csrptr->cstat = 0;           /* for sure */
        !            36:   csrptr->cstat = SLURESET;
        !            37:   for (i=0;i<10;i++);          /* little delay */
        !            38:   soft_control_reg[i].vals[0] = 0;
        !            39:   csrptr->cstat = 2;
        !            40:   csrptr->cstat = SLUCREG2DEF;
        !            41:   soft_control_reg[i].vals[2] = SLUCREG2DEF;
        !            42:   csrptr->cstat = 4;
        !            43:   csrptr->cstat = SLUCREG4DEF;
        !            44:   soft_control_reg[i].vals[4] = SLUCREG4DEF;
        !            45:   csrptr->cstat = 1;
        !            46:   csrptr->cstat = SLUCREG1DEF;
        !            47:   soft_control_reg[i].vals[1] = SLUCREG1DEF;
        !            48:   csrptr->cstat = 3;
        !            49:   csrptr->cstat = SLUCREG3DEF;
        !            50:   soft_control_reg[i].vals[3] = SLUCREG3DEF;
        !            51:   csrptr->cstat = 5;
        !            52:   csrptr->cstat = SLUCREG5DEF|SLUCREG5DTR;
        !            53:   soft_control_reg[i].vals[5] = SLUCREG5DEF|SLUCREG5DTR;
        !            54:   csrptr->cstat = 0;           /* leave with reg 0 selected */
        !            55:   *SLUSELECT9600 = 0;          /* write to magic addr for 9600 baud */
        !            56:   delay7201();                 /* don't use right away */
        !            57:   return 0;
        !            58: }
        !            59: 
        !            60: set_baudrate(int baudrate)
        !            61: {
        !            62:   switch (baudrate) {
        !            63:   case 1200: *SLUSELECT1200 = 0;
        !            64:     break;
        !            65:   case 2400: *SLUSELECT2400 = 0;
        !            66:     break;
        !            67:   case 4800: *SLUSELECT4800 = 0;
        !            68:     break;
        !            69:   case 9600: *SLUSELECT9600 = 0;
        !            70:     break;
        !            71:   case 19200: *SLUSELECT19200 = 0;
        !            72:     break;
        !            73:   case 38400: *SLUSELECT38400 = 0;
        !            74:     break;
        !            75:   default:  return -1;
        !            76:   }
        !            77:   return 0;
        !            78: }
        !            79: 
        !            80: delay7201()
        !            81: {
        !            82:   int i;
        !            83: 
        !            84:   for (i=0;i<10000;i++)
        !            85:        ;
        !            86: }
        !            87: 
        !            88: /* call this to get current control reg contents-- */
        !            89: get_control_reg7201(csrptr,reg)
        !            90: struct csr *csrptr;    /* ptr to device csr */
        !            91: {
        !            92:   int i;
        !            93: 
        !            94:   for (i=0;i<MAXSLU;i++)
        !            95:     if (soft_control_reg[i].csrptr == csrptr)
        !            96:       return soft_control_reg[i].vals[reg];
        !            97:   panic("Bad csrptr or uninitialized SLU");
        !            98: }
        !            99: 
        !           100: /* must be called to change control reg, so that software var is maintained */
        !           101: set_control_reg7201(csrptr,new_control,reg)
        !           102: struct csr *csrptr;
        !           103: char new_control;
        !           104: {
        !           105:   int i;
        !           106: 
        !           107:   for (i=0;i<MAXSLU;i++)
        !           108:     if (soft_control_reg[i].csrptr == csrptr)
        !           109:       break;
        !           110:   if (i==MAXSLU)
        !           111:     panic("Bad csrptr or uninitialized SLU");
        !           112: 
        !           113:   if (reg==0) {
        !           114:     if (new_control&SLUREGMASK) /* better not set another reg! */
        !           115:       panic("Inconsistent use of set_control_reg7201");
        !           116:     else                       /* OK, do it */
        !           117:       csrptr->cstat = new_control;
        !           118:   }
        !           119:   else {                       /* reg>0--select reg, do it, reselect reg 0 */
        !           120:     csrptr->cstat = reg;       /* select reg */
        !           121:     csrptr->cstat = new_control;
        !           122:     csrptr->cstat = 0;         /*  back to reg 0 */
        !           123:   }
        !           124:   delay7201();                 /* let 7201 have time to process cmd */
        !           125:   soft_control_reg[i].vals[reg] = new_control;
        !           126:   return 0;
        !           127: }
        !           128: /* used by slutenable macro--reenable transmit ints if necessary,
        !           129:    start output with null char */
        !           130: slu_tstart7201(csrptr)
        !           131: struct csr *csrptr;
        !           132: {
        !           133:   short savesr,creg1;
        !           134:   int i;
        !           135: 
        !           136:   for (i=0;i<MAXSLU;i++)
        !           137:     if (soft_control_reg[i].csrptr == csrptr)
        !           138:       break;
        !           139:   if (i==MAXSLU)
        !           140:     panic("Bad csrptr or uninitialized SLU");
        !           141: 
        !           142:   _disable(&savesr);           /* make sure test,set of int bit is atomic  */
        !           143:   if ((creg1 = soft_control_reg[i].vals[1])&SLUTRANSIE) {
        !           144:     _restore(&savesr);
        !           145:     return;                    /* already going */
        !           146:   }
        !           147:   while ((csrptr->cstat&SLUTRANSREADY)==0) ; /* make sure transmitter idle */
        !           148:   set_control_reg7201(csrptr,creg1|SLUTRANSIE,1); /* set int. bit */
        !           149:   csrptr->cbuf = 0;            /* start output */
        !           150:   _restore(&savesr);
        !           151: }
        !           152: 
        !           153: 
        !           154:   

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